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We engineer a scalable and CMOS-friendly RRAM stack using down to 3nm ALD-based Ta 2 O 5 . The 20nm-sized TiN\Ta 2 O 5 \Ta device operated at 50μA exhibits ultra-fast write (~5ns) at moderate voltage ( 10 9 write endurance. We also demonstrate excellent disturb and retention characteristics, which we relate to the appropriate tuning of the oxygen chemical-potential profile along the filament by means of the Ta scavenger material and thickness.

We propose for the first time a systematic evaluation of the performance and underlying trade-off of the use of ternary Hf 1-x Al x O y oxides for RRAM application. We show that intermixing HfO 2 and Al 2 O 3 deposition cycles in a standard ALD process not only prevents crystallization of active layer but also significantly improve intrinsic retention and disturb-immunity properties at the expense of a small increase of programming voltage. We attribute this beneficial effect to the reduced V o diffusivity caused by stronger Al-O bonds as suggested by ab-initio simulations.

In this letter, we demonstrate a one-transistor capacitorless DRAM on standard bulk FinFET, using no additional processing. It is shown that, due to the use of the ground-plane doping and optimization of the READ bias conditions, no special process adjustment is required to obtain wide programming windows and long retention times, even for fin widths down to 20 nm.

This paper describes a method to manufacture bulk fins for finFET. The bulk fins consist of two parts: the straight top of 125nm height which is used as a fin and a sloped bottom of 200nm one that facilitates the trench filling. The method is based on a conventional shallow trench isolation (STI) process flow with an additional @a-C hard mask of 90nm (with antireflective SiOC coating of 35nm) on top of the STI stack (70nm nitride on top of 8nm oxide). The nitride layer and the top straight part of the fin is patterned using CH"2F"2/SF"6/N"2 chemistry and @a-C as a mask, while the bottom sloped part is patterned using Cl"2/O"2/N"2 chemistry and the nitride layer as a mask. After the etching, the STI process flow remains almost unchanged.

One of the key concerns related to low operating current ( 2 /Hf 1T1R RRAM cells. Based on this understanding we demonstrated significant improvement in retention by adding an additional thermal budget into our process flow. The impact of the Forming process on retention property was also investigated and Forming/SET conditions were optimized to improve the retention without increasing the operation current.

In the study, we report for the first time a novel concept for the mitigation of the TSV-induced stress on the CMOS device performance. This solution consists in selectively integrating an airgap at the time of via-middle TSV processing. In addition to the expected benefits in term of stress management, this new approach is also cost effective, as the TSV processing steps, such as deep silicon etching, Cu electroplating, and chemical mechanical polishing remain unchanged. The processing development and the results of the morphological and electrical characterization are given in details in this study. All in all, TSV with integrated airgap is a very versatile building block for TSV integration in presence of stress sensitive next generation of CMOS devices.

We report on the performance and reliability of the Hf/HfO2 RRAM cell with Ultra-Thin Oxide (UTO-RRAM). We show that cells with an oxide thickness of 3 nm have basic performance (including speed, switching voltages, and the on/off window) similar to that of the cells with reference oxide (5-10 nm thickness), while their operation requires a forming step at a voltage of only about 1.5 V for a 40 nm size. This performance can be further optimized by tuning the cap layer thickness. We also demonstrate endurance of at least 108 cy and observe failure modes similar to the reference cells. Endurance optimization needs to take into account, next to the stack structure and pulse characteristics, the target on/off states. UTO-RRAM retention is strongly temperature-activated, with a median cell extrapolating at 125°C/10 yr. Furthermore, we analyze in detail the on-state loss and show how emergence of tail bits relates to the strength (initial level) of the state.

In this work we evaluate the impact of TSV processing and proximity on transistor performance and reliability by monitoring key device parameters after thermal cycling and thermal storage. No transistor degradation related to potential barrier failure, liner breakdown or Cu diffusion was observed and it is concluded that when respecting the keep out zone, the FEOL yield and reliability is not affected by TSV processing.

This work provides for the first time an experimental assessment of the impact of thermo-mechanically induced stresses by copper through-silicon vias, TSVs, on fully depleted Bulk FinFET devices. Both n and p type FinFETs are significantly affected by TSV proximity, exhibiting lower impact on drive current with respect to the planar devices. The obtained results are in agreement with the thermo-mechanical models for Cu-TSV and are supported by the 4 point bending stress calibration.

Higher performance, higher operation speed and volume shrinkage require high 3D TSV interconnect densities. This work focuses on a via-middle 3D process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) and before the back-end-of-line (BEOL) interconnect process. A description of the imec 300 mm TSV platform is given, and challenges towards a reliable process integration of high density high aspect-ratio 3D interconnections are also discussed in details.

This paper reports on experiments assessing 3 potential impacts and reliability risks induced by the thermal mismatch between Cu and Si in Cu filled through-silicon via (TSV) integration in 3D technology. The results show that (1) the Cu stress is a higher contributor to stress in the Si than FEOL film edge effects induced by TSV etch; (2) Cu extrusion induced by BEOL processing does not lead to severe delamination/cracking in low-k BEOL layers above the TSV; (3) stress induced at the TSV bottom does not cause visible damage to the liner or backside passivation after wafer thinning.

Increasing the TSV aspect ratio is a manufacturable approach to meet the requirements of high density 3D interconnections. A good control on the overall cost of ownership of the 3D interconnections clearly points towards the direction of highly conformal thin film deposition techniques for liner, barrier, and seed processing. The SiO 2 liner process, developed within ASM and implemented into imec 3D test vehicles, exhibits near-ideal conformality obtained for deposition temperature as low as 200oC. This is making this liner process a very versatile candidate for integration into via-middle process flow.

Due to their large volume and close proximity to devices, the reliability of copper TSV's is a concern, both with respect to mechanical stresses induced by the TSV in the Si and with respect to copper drift into the liner and the Si. This abstract summarizes recent achievements obtained in imec's 3D-reliability work package where above mentioned reliability concerns are evaluated in detail. To study the impact of mechanical stresses induced by the TSV in the Si, the saturation drain currents I d of transistors have been used as stress sensors. The offset of the I d of transistors closer to a TSV with respect to transistors far away from a TSV has been studied, both directly after processing and after thermal storage and thermal shock. It is shown that stresses generated by the TSV in the Si increase after thermal storage above certain temperatures while thermal shock reduces these stresses. The first is attributed to stress relaxation at high temperatures, while the latter is attributed to cracking/delamination at critical interfaces. To study continuity in TSV-barriers, a method, further referred to as dual ramp rate IV ctrl , is introduced. The method consists of controlled current-voltage sweeps at different rates. The difference in breakdown fields for different ramp rates allows estimating TDDB (=Time Dependent Dielectric Breakdown) field acceleration parameters. Applying a negative voltage to the TSV (−V) does not allow copper to drift into the liner, while when applying a positive voltage (+V) to the TSV, copper can drift into the liner in case of a defective, non-continuous barrier. Comparing TDDB field acceleration parameters of −V versus +V tests gives insight in barrier properties. In our study, weak reliability is observed in systems where the TSV-barriers are not continuous.

In this work we compare techniques to measure the stress in Cu through silicon via's (TSV's) and study the stress as a function of post-plating anneal time and temperature. Our results show that each technique was able to measure the stresses with good agreement. However, wafer curvature was limited to measuring the in-plane stress and the top down Raman spectroscopy geometry is dominated by the out-of-plane stress. Only x-ray diffraction could measure all principal stress components, showing high in-plane stress for longer post-plating anneals that could affect transistor performance.

Higher performance, higher operation speed and volume shrinkage require high 3D interconnect densities. A way to meet the density specifications is to further increase the A.R. of the TSV interconnection. This requires the integration of highly conformal thin films deposition techniques in TSV flows, particularly for metallization. In this study, seed layer enhancement is applied to regular PVD Cu seed for metalizing TSV of diameter of 2μm and aspect-ratio 15:1. The results reported in this paper open a new path for process integration of high A.R. TSVs and provide a versatile and reliable building block for achieving the high density interconnects required for tomorrow's 3D electronics devices.

In this paper, the controlled I-V (IV ctrl ) method is adopted for the barrier integrity characterization of TSVs at wafer level. Planar capacitor structures are used for the initial validation of the IV ctrl method with respect to the traditional time dependent dielectric breakdown (TDDB) methodology. The TDDB field acceleration factor of the TSV liner is extracted by IV ctrl in a reasonable time, and the results demonstrate that defective barriers can degrade TDDB field acceleration factor and thus TSV liner reliability.

Barrier reliability in 3D Through-Si Via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This work focuses on a via-middle process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) process, but before the back-end-of-line (BEOL) interconnect process. This results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400°C range. Thus, it becomes essential to study the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. We report on the thermal stability of Ta and Ti barriers and we show that 5nm Ta barriers are thermally stable, while Ti-barriers require thicknesses above 5nm to guarantee their thermal stability.

The semiconductor industry is witnessing a major shift towards heterogeneous 3D integration. Whether companies are active in high performance or consumer markets systems, 3D offers a myriad of opportunities. We will review the different opportunities, indicate process availability and remaining challenges from both design and technology perspective.

The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O 3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.

This work presents a process to fabricate FinFETs in bulk silicon with advancements in critical fabrication steps such as STI trench oxide recess and adjustment of fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and FinFETs in the same wafer. Morphological and electrical results indicate perfectly filled trenches, better fin height control and bulk FinFET static performance similar to planar CMOS.

FinFET is a promising device structure for scaled CMOS logic/memory applications in 22 nm technology and beyond, thanks to its good short channel effect (SCE) controllability and its small variability. Scaled SRAM and analog circuit are promising candidates for finFET applications and some demonstrations for them are already reported. On the other hand, for finFETs production, quite a lot of process challenges are required due to difficult fin/gate patterning in the 3D structure, conformal doping to fin and high access resistance in extremely thin body, etc. The fin/gate patterning can be improved by optimization of patterning stack, patterning scheme and etch chemistry. Alternative doping techniques show good conformal doping in 3D structure in finFETs. High access resistance is reduced by junction optimization and strain boaster technique.

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Retention times up to 10s at 85°C can be achieved for bulk FinFET 1T-DRAM devices using an optimized biasing scheme which targets the storage of electrons in the fin. The impact of the ground plane doping is investigated and finally the read-out scheme is also demonstrated on SOI FinFET devices.

3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.

The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced mismatch. Using an optimized integration to minimize parasitics we demonstrate high-performing FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk FinFETs and working SRAM cells at VDD=1.0V.

In this paper we report on mass metrology used for the characterization of different process steps (etch, clean, cavity etch, HARP deposition and CMP) of shallow trench isolation (STI) module in conventional CMOS technology. We also report on mass metrology for the characterization of plasma doping and on HfO2 high k gate dielectric deposition process. The performance of the mass balance metrology is benchmarked against state of the art metrology, including ellipsometry and Rutherford Backscattering (RBS).

In this article, we evidence the lower formation energy and improved stability of the conductive filament (CF) formed in TiN\Ta2O5\Ta resistive-switching memory cells treated in NH3 atmosphere at 400 °C. This annealing treatment results in (i) lower forming voltage, (ii) lower CF resistance, and (iii) longer retention lifetime of the oxygen-vacancy (Vo) chain constituting the CF. Atomistic insights into these processes are provided by ab initio calculations performed for hydrogen (H) species incorporated in non-stoichiometric Ta2O5 supercells: (i) Vo formation energy is reduced by the presence of H, (ii) Vo-chain CF conductivity is increased by Vo + OH complex formation, and (iii) Vo-chain retention is strengthened by the stable Vo + OH complex. As a result, efficient CF formation and excellent state stability are obtained after 15 days at 250 °C.

Impact of set/reset pulse duration and amplitude on the endurance failure modes of TiN\Ta2O5\Ta cells is investigated and is related to interaction between Oxygen and TiN bottom electrode during reset. Hourglass electrical switching simulation of conductive filament temperature during reset transient and ab-initio calculation of reaction energy further support this degradation mechanism. Based on this understanding, endurance improvement is achieved by using shorter reset pulse and/or using inert Ru bottom electrode.

In this paper we show that the ultimate limit of Cosilicide expected for 100nm CMOS technology node can be postponed to the next generation thanks to its elevation by selective epitaxy. We demonstrate that conventional Co-silicide combined with elevated S/D can be still compatible with the junctions representative for sub-50nm CMOS devices. Moreover, elevated silicide enables reducing sheet resistance without compromising the junction leakage and degrading transistor performance. Thanks to high drive current and reduced gate sheet resistance excellent RF characteristics were obtained. 70nm NMOS devices exhibit FT of 150GHz and Fmax of 70GHz.

An investigation of the gate stack for 90nm gate length CMOS is presented. The optimised 90nm nMOS and pMOS transistors exhibit state of the art DC and switching characteristics. Nominal nMOS and pMOS Ioff state current of 2nA / DD =1.2V) have been realized. An inverter delay of 15ps at 1.2V operating voltage has also been measured.

Improved metal-insulator-metal capacitor (MIMCAP) stacks with strontium titanate (STO) as dielectric sandwiched between Ru as top and bottom electrode are shown. The Ru/STO/Ru stack demonstrates clearly its potential to reach sub-20 nm technology nodes for dynamic random access memory. Downscaling of the equivalent oxide thickness, leakage current density (Jg) of the MIMCAPs, and physical thickness of the STO have been realized by control of the Sr/Ti ratio and grain size using a heterogeneous TiO2/STO based nanolaminate stack deposition and a two-step crystallization anneal. Replacement of TiN with Ru as both top and bottom electrodes reduces the amount of electrically active defects and is essential to achieve a low leakage current in the MIM capacitor.

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