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In this paper, the reliability of InP/InGaAs DHBTs under high reverse base–collector bias stress is analyzed by experiments and simulation. The DC characteristics and S parameters of the devices under different stress times were measured, and the key parameters with high field stress were also extracted to fully understand and analyze the high-field degradation mechanism of devices. The measurements indicate that the high-field stress leads to an increase in base current, an increase in base–collector (B–C) and base–emitter (B–E) junction leakage current, and a decrease in current gain, and different degrees of degradation of key parameters over stress time. The analysis reveals that the degradation caused by reverse high-field stress mainly occurs in the B–C junction, access resistance degradation, and passivation layer. The physical origins of these failure mechanisms have been studied based on TCAD simulation, and a physical model is proposed to explain the experimental results. [ABSTRACT FROM AUTHOR]

We demonstrated a prototype Gated Lateral power bipolar junction transistor (GLP-BJT) on wide bandgap semiconductor. The device combined the intrinsic advantages of high current gain of a Gated Lateral-BJT and good current handling and voltage blocking capabilities of GaN material. As a result, the common-emitter current gain remained over 300 at a high collector current density of 2 kA/cm2 despite a wide p-base region of 2µm. The open base breakdown voltage BVCEO was over 300 V corresponding to a high critical field of 2.5 MV/cm. These figures of merit show great promise of GaN-based GLP-BJT in power applications and also shed light on the development of state-of-the-art bipolar transistors based on other wide bandgap semiconductors.

Sub-stoichiometric molybdenum oxide (MoO x) has recently been investigated for application in high efficiency Si solar cells as a "hole selective" contact. In this paper, we investigate the electrical and light-emitting properties of MoO x -based contacts on Si from the viewpoint of realizing functional bipolar devices such as light-emitting diodes (LEDs) and transistors without any impurity doping of the Si surface. We realized diodes on n-type Si substrates using e-beam physical vapor deposition of Pd/MoO x contacts and compared their behavior to implanted p + n-Si diodes as a reference. In contrast to majority-carrier dominated conduction that occurs in conventional Schottky diodes, Pd/MoO x /n-Si diodes show minority-carrier dominated charge transport with I–V, C–V, and light-emitting characteristics comparable to implanted counterparts. Utilizing such MoO x -based contacts, we also demonstrate a lateral bipolar transistor concept without employing any doped junctions. A detailed C–V analysis confirmed the excessive band-bending in Si corresponding to a high potential barrier (> --> 0.90 V) at the MoO x /n-Si interface which, along with the observed amorphous SiO x (Mo) interlayer, plays a role in suppressing the majority-carrier current. An inversion layer at the n-Si surface was also identified comprising a sheet carrier density greater than 8.6 × 10 11 cm − 2 , and the MoO x layer was found to be conductive though with a very high resistivity in the 10 4 Ω -cm range. We refer to these diodes as metal/non-insulator/semiconductor diodes and show with our device simulations that they can be mimicked as high-barrier Schottky diodes with an induced inversion layer at the interface. [ABSTRACT FROM AUTHOR]

The multi-chip parallel insulated gate bipolar transistor (IGBT) is the core device in large-capacity power electronic equipment, but its operational reliability is of considerable concern to industry. The application of IGBT online degradation state analysis technology can be beneficial to the improvement of system reliability. The failure mechanism of IGBT devices is discussed in this paper, and a technique for analyzing the degradation state of IGBT based on apparent junction temperature is proposed. First, the distortion consistency of the voltage rise time in various failures is discussed, and the junction temperature dependence of the voltage rise time is then demonstrated. Subsequently, an apparent junction temperature model based on the voltage rise time is established (the fitting accuracy is as high as 94.3%). From the high-frequency model in the switching process of the device, an online extraction technology of key parameters (e.g., voltage rise time) is developed. Finally, an experimental platform for IGBT degradation state estimation is established, and the feasibility of IGBT degradation state estimation based on apparent junction temperature is proved, especially the degradation of bonding-wire and the gate-oxide-layer. The experimental results show that the proposed IGBT degradation state estimation technique based on apparent junction temperature is a reliable online estimation method with non-contact, high accuracy, and comprehensiveness. [ABSTRACT FROM AUTHOR]

Accurate models of power electronic converters can greatly enhance the accuracy of hardware-in-the-loop (HIL) simulators. This can result in faster and more cost-effective design cycles in industrial applications. This paper presents a detailed hardware model of the IGBT and power diode at the device level suggested for emulating power electronic converters on a field programmable gate array (FPGA). The static visualization of the IGBT component involves an arrangement of equivalent models for both the MOSFET and bipolar transistor in a cascading configuration. The dynamic aspect is represented by inter-electrode nonlinear capacitances. In an effort to expedite the development process while still producing reliable results, the algorithm for the simulation system was built utilizing FPGA-based rapid prototyping via the HDL Coder in MATLAB software (R2019b). Essentially, the HDL Coder transforms the Simulink blocks of these devices within MATLAB into a hardware description language (HDL) suitable for implementation on an FPGA. To evaluate the suggested IGBT hardware model and the nonlinear circuit simulation technique, a chopper circuit is replicated, and an FPGA-in-the-loop simulation is carried out to compare the efficacy and accuracy of the model with both offline simulation results and real-time simulation results using MATLAB Simulink software and the Altera FPGA Cyclone IV GX development board. [ABSTRACT FROM AUTHOR]

This paper works on the modelling of solar PV with series parallel connection of the strings for the composite climate location and the detailed study has been done on the gate signal of the chopper used for boosting with three different conditions. As the climate conditions are very important factor for the installation of the project to fulfill the captive requirements, a study has also been done with the help of climate consultant software so that the radiations capacity and potential to develop the energy is with in its maximum output capacity. In the next phase an inverter has also been connected for the conversion into single phase AC output for the testing of the model for the usage in the load or grid. Various methods for the control of the booster has been analyzed and considered. Simulation is done on a Matlab software and the result is analyzed. [ABSTRACT FROM AUTHOR]

Copyright of Electric Power Automation Equipment / Dianli Zidonghua Shebei is the property of Electric Power Automation Equipment Press and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this work, the effects of total dose irradiation on the parasitic bipolar junction transistor (BTJ) in 130 nm PDSOI MOSFETs were investigated. The experimental results demonstrate that irradiation-induced oxide-trap charges can modify the E-B junction barrier, and thereby make the common-emitter gain β 0 of the parasitic BJT in NMOS device increase, while decreasing it in a PMOS device. Additionally, irradiation-generated oxide-trap charges in shallow trench isolation (STI) elevate the surface electrostatic potential of the gate above the STI sidewall, thus providing an additional channel from the emitter to the collector. Moreover, these charges may generate parasitic reverse conductive paths at the STI/Si interface under high dose irradiation, thereby enhancing the leakage current in the front gate channel and diminishing the significance of the parasitic BJT. Under irradiation, the electric field intensity difference between two biases leads to higher β 0 of the parasitic BJT in PG-biased devices than in ON-biased ones. Furthermore, the lifting effect of irradiation on β 0 increases in wide or short channel irradiated devices, which can be explained using simulations and an emitter current crowding effect model. [ABSTRACT FROM AUTHOR]

In this study, the operation of npn-type GaN-based heterojunction bipolar transistors with different net acceptor concentrations in p-base regions was simulated. It was confirmed that there is a critical net acceptor concentration (NA-ND) depending on the thickness of the base region and that if the NA-ND is lower than the critical value, the collector current may anomalously increase, regardless of base current injection. This phenomenon is caused by the punch-through process via the depletion layer extending from the collector–base junction. The effect of the valence band energy offset at the emitter-base heterojunction (ΔEV) on the current gain (β) was also investigated, and the results showed that β peaks when ΔEV is 0.22–0.30 eV. This is determined by the balance between the hot-electron injection and thermal diffusion processes in the electron transport from the emitter to the base. [ABSTRACT FROM AUTHOR]

This paper presents a critical and detailed overview of experimental techniques for the extraction of the thermal resistance of bipolar transistors from simple DC current/voltage measurements. More specifically, this study focuses on techniques based on a thermometer, i.e., the relation between the base-emitter voltage and the junction temperature. The theory behind the techniques is described with a unified and comprehensible nomenclature. Advantages, underlying approximations, and limitations of the methods are illustrated. The accuracy is assessed by emulating the DC measurements with PSPICE electrothermal simulations of a transistor model, applying the techniques to the simulated currents/voltages, and comparing the extracted thermal resistance data with the values obtained from the target formulation embedded in the transistor model. An InGaP/GaAs HBT and an Si/SiGe HBT for high-frequency applications are considered as case-studies. [ABSTRACT FROM AUTHOR]

Copyright of Electric Machines & Control / Dianji Yu Kongzhi Xuebao is the property of Electric Machines & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Severe switching oscillations of SiC MOSFET seriously affect its efficient and reliable application. Herein, a novel inductively coupled RLC damping scheme is proposed to eliminate switching oscillations. Distinctive from existing RLC resonators, the setting that the resonant frequency of the secondary RLC damping is equal to that of the power loop is abandoned. Additionally, prior‐art analytical techniques of RLC resonators are based on seeking the peak impedance, which considerably undermines its suppression effect. First, a two‐port network is linearized from switching oscillations, where the characteristic equations are deduced. Then, parametric regions where the switching oscillations can be eliminated are determined by actively assigning poles via the root locus method. Consequently, the damping effect of the proposed scheme, as well as the resulted switching losses, shows its superiority over the state‐of‐the‐art snubbers. The proposed scheme is favourable in practical applications since it is less insensitive to parasitics enabling selection of snubber resistors with higher power ratings. It also avoids unusual temperature rise resulted by snubber losses due to oscillation suppression in the power loop as snubber losses are transferred to the secondary circuit. Theoretical analysis and experimental comparisons are conducted to verify the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

The effects of high total dose proton irradiation on the reliability of silicon NPN rf power bipolar junction transistor (BJT) were examined by subjecting to 1, 3, and 5 MeV protons in the dose range from 100 Krad to 100 Mrad. The electrical characteristics such as Gummel characteristics (IB, IC-VBE), excess base current (ΔIB = IBpost – IBpre), current gain (hFE), and output characteristics (IC-VCE), built-in potential (Vbi) and the effective doping concentration (Nd) were studied before and after irradiation. SRIM simulation was conducted to understand the range and energy loss of protons in the BJT structure. SRIM and experimental results infer that the proton irradiation at lower energy (1 MeV) was found to degrade the current–voltage(I-V) and capacitance–voltage (C-V) characteristics more severely than higher-energy (3 and 5 MeV) proton irradiation. Thermal annealing on irradiated devices was also conducted to study the parametric recovery of irradiated devices. [ABSTRACT FROM AUTHOR]

An ultra-low power, high accuracy BJT-based CMOS temperature sensor is presented in this paper. The temperature sensor consists of analog front end (AFE) and hybrid ADC. In AFE design, two dynamic element matching (DEM) control modules are applied to current mirrors and bipolar transistors reduce the mismatch greatly and enhance the sensitivity of the temperature sensor. A hybrid ADC that combines ΣΔ ADC and SAR ADC is designed to provide quick conversion results and reduce the power dissipation. The proposed sensor is fabricated in a 0.18 μm CMOS process, occupying an area of 0.14 mm2. The measured results indicate that, the total current is 6.5 μA from a 1.8 V power supply, and achieves an inaccuracy of ±0.15 °C (3δ) from −40 °C to 125 °C. • The temperature sensor consists of analog front end (AFE) and hybrid ADC. • Two DEM applied to current mirrors and bipolar transistors to reduce the mismatch and enhance the sensitivity greatly. • A hybrid ADC combines ΣΔ ADC and SAR ADC is designed to provide quick conversion results and reduce power dissipation. [ABSTRACT FROM AUTHOR]

A high-precision current-mode bandgap reference (BGR) circuit with a high-order temperature compensation is presented in this paper. In order to achieve a high-precision BGR circuit, the equation of the nonlinear current has been modified and the high-order term of the current flowing into the nonlinear compensation bipolar junction transistor (NLCBJT) is compensated further. According to the modified equation, two solutions are designed to improve the output accuracy of BGR circuits. The first solution is to divide the NLCBJT branch into two branches to reduce the coefficient of the nonlinear temperature compensation current. The second solution is to inject the nonlinear current into the two branches based on the first one to further eliminate the temperature coefficient (TC) of the current flowing into the NLCBJT. The proposed BGR circuit has been designed using the Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The simulation results show that the variations in currents flowing into NLCBJTs improved from 148.41 nA to 69.35 nA and 7.4 nA, respectively, the TC of the output reference current of the proposed circuit is approximately 3.78 ppm/°C at a temperature range of −50 °C to 120 °C with a supply voltage of 3.3 V, the quiescent current consumption of the entire BGR circuit is 42.13 μA, and the size of the BGR layout is 0.044 mm2, leading to the development of a high-precision BGR circuit. [ABSTRACT FROM AUTHOR]

This paper presents a low-power sub-bandgap voltage reference. Here, the proportional to absolute temperature (PTAT) voltage obtained from ∆VEB is applied to a subthreshold diode-connected PMOS transistor to yield a current with a positive thermal coefficient (TC). The current is then converted back to a PTAT voltage term using another subthreshold PMOS transistor at the output path. Moreover, utilizing the bipolar transistor achieves a lower process variation VR. A trimming circuit is also applied to improve the TC against the process variation further. Low-power VR is achieved by operating all the MOSFETs under the subthreshold region. The simulation results using the standard 1.8 V, 0.18 µm CMOS process shows a nominal output voltage of 0.75 V, operating from 0.9 V to 1.8 V supply voltage while consuming 41.4 nA at room temperature. The TC is about 21.6 ppm/oC and (σVREF/μVREF) = 1.0 % over a temperature range of 0 °C to 120 °C. In addition, the proposed VR circuit is simulated without a trimming circuit resulting in a reasonable μTC = 29.1 ppm/oC and (σVREF/μVREF) = 1.3%. [ABSTRACT FROM AUTHOR]

Emerging soft ionotronics better match the human body mechanically and electrically compared to conventional rigid electronics. They hold great potential for human‐machine interfaces, wearable and implantable devices, and soft machines. Among various ionotronic devices, ionic junctions play critical roles in rectifying currents as electrical p–n junctions. Existing ionic junctions, however, are limited in electrical and mechanical performance, and are difficult to fabricate and degrade. Herein, the design, fabrication, and characterization of tough transient ionic junctions fabricated via 3D ionic microgel printing is reported. The 3D printing method demonstrates excellent printability and allows one to fabricate ionic junctions of various configurations with high fidelity. By combining ionic microgels, degradable networks, and highly charged biopolymers, the ionic junctions feature high stretchability (stretch limit 27), high fracture energy (>1000 Jm−2), excellent electrical performance (current rectification ratio >100), and transient stability (degrade in 1 week). A variety of ionotronic devices, including ionic diodes, ionic bipolar junction transistors, ionic full‐wave rectifiers, and ionic touchpads are further demonstrated. This study merges ionotronics, 3D printing, and degradable hydrogels, and will motivate the future development of high‐performance transient ionotronics. [ABSTRACT FROM AUTHOR]

A low‐power negative‐positive‐negative (NPN)‐based bandgap voltage reference (BGR) over an ultra‐wide temperature range is presented. The conventional NPN‐based BGRs cannot maintain a low‐temperature coefficient (TC) with low power consumption in an ultra‐wide temperature range due to its inherent reverse junction saturation current of NPN bipolar junction transistors (BJT) in the high‐temperature range. This work introduces a new NPN‐based BGR unaffected by such saturation current. Based on Vanguard International Semiconductor Corporation (VIS) 0.18 μm/0.15 μm complementary metal oxide semiconductor (CMOS) Bipolar‐CMOS‐DMOS (BCD) process, the BGR receives the best 1.25‐mV deviation over the temperature range of −40°C to 150°C, much less than 38.5 mV from Brokaw‐type BGR. Meanwhile, the proposed BGR with the stacked NPNs for higher output voltage was fabricated. It consumes about 2 uA from a 5‐V power supply, and its average temperature coefficient is 14.89 ppm/°C. Also, the average line sensitivity is 0.039%/V. [ABSTRACT FROM AUTHOR]

This brief paper shows that robust chaotic behavior can be detected within a tuned-collector single-stage transistor-based oscillator. The content of this work also contributes to the problem of chaos localization in simplified mathematical model of standard analog building block. Searching for chaos is performed via numerical optimization routine applied onto the principal schematic of oscillator where generalized bipolar transistor is modelled as a two-port described by impedance as well as admittance matrix. In both cases, the presence of dense chaotic attractor is proved via calculation of the largest Lyapunov exponent, while its structural stability is validated by real measurement, i.e., visualization of captured oscilloscope screenshots. [ABSTRACT FROM AUTHOR]

A 13 kV class n-channel 4H–SiC trench gate insulated gate bipolar transistor (IGBT) structure is designed based on Silvaco TCAD device simulator tool. The influence of metal/SiC and SiC MOS interface trap states on the static and dynamic characteristics of SiC IGBT devices are systematically studied. It is found that the electrical properties of SiC IGBTs are insensitive to the donor or acceptor traps at the interface of metal/SiC and the donor traps at the SiC/SiO2 interface. However, the acceptor traps at the SiC/SiO2 interface affect the electrical properties of SiC IGBTs greatly. When the acceptor trap density at the SiC/SiO2 interface (Dita) is up to the level of 1012 cm−2·eV−1, the turn-on voltage drop (VCEON) is increased gradually with the augmentation of Dita. The breakdown voltage (VBR) of the device is increased slightly. Further study of the device's turn-off characteristics shows that the turn-off loss (EOFF) is decreased with the increase in Dita but a large tail current is formed. The mechanism may be that when the electrons are injected from the N+ source region into the N− drift region, the SiC/SiO2 interfacial acceptor traps at the side wall of trench gate capture a large number of electrons. As a result, the minority carrier concentration is decreased, and the conductance modulation effect on the N− drift region is weakened. [ABSTRACT FROM AUTHOR]

A novel Performance Optimized Carrier Stored Trench Gate Bipolar Transistor (CSTBT) with Low Switching Loss has been proposed. By applying a positive DC voltage to the shield gate, the carrier storage effect is enhanced, the hole blocking capability is improved and the conduction loss is reduced. The DC biased shield gate naturally forms inverse conduction channel to speed up turn-on period. Excess holes are conducted away from the device through the hole path to reduce turn-off loss (Eoff). In addition, other parameters including ON-state voltage (Von), blocking characteristic and short circuit performance are also improved. Simulation results demonstrate that our device exhibits a 35.1% and 35.9% decrease in Eoff and turn-on loss (Eon), respectively, in comparison with the conventional shield CSTBT (Con-SGCSTBT). Additionally, our device achieves a short-circuit duration time that is 2.48 times longer. In high-frequency switching applications, device power loss can be reduced by 35%. It should be noted that the additional DC voltage bias is equivalent to the output voltage of the driving circuit, enabling an effective and feasible approach towards high-performance power electronics applications. [ABSTRACT FROM AUTHOR]

The interval Newton method, which combines the Newton method with the interval arithmetic and branch-and-prune algorithm, has been applied to the problem of finding all direct current operating points of nonlinear circuits. The modified linear programming narrowing technique has also been proposed to improve the computational efficiency of the interval Newton method when applying to a circuit whose nonlinear elements are only diodes and bipolar junction transistors. In this paper, a contraction operator based on interval linearization has been applied to further improve the performances. In addition, the application of the proposed method to circuits containing MOSFET is presented. The numerical experimental results on some test nonlinear circuits indicate that the proposed method can further reduce the number of search boxes and improve the computation time. [ABSTRACT FROM AUTHOR]

Well, do you remember when a factor of 2 was good enough? Probably, not unless you have been around secondary ion mass spectrometry (SIMS) since the early 1960s, like one of us has been. This paper will give many references back to the early days of quantification when a local thermal equilibrium model was used to obtain the first results that were accurate to within a factor of 2, but only 60% of the time. It only worked for bulk silicate matrixes. People were not even using SIMS on semiconductors in those days. Several early references showing profiles of ion implants in Si will be referenced, but it was not until 1980 that the first paper was published that explicitly showed how to use ion implants as SIMS standards. People were using ion implants as standards before 1980, but only in limited cases, and with no formal published equations specifying how to use them. But, the samples for which ion implants were used as standards were for dilute concentrations in a single matrix, which had a uniform matrix composition with depth. The rest of the paper will show how we at Eurofins EAG Laboratories tackled the problem of quantification of both major and minor elements in nonuniform, multi-element matrices with continuously graded composition changes using point-by-point CORrected-SIMS. These include SiGe heterostructure bipolar transistors, AlGaAs vertical cavity surface emitting lasers, and B plasma-implanted poly-silicon gates. [ABSTRACT FROM AUTHOR]

We demonstrate high signal-to-noise electrically detected electron-nuclear double resonance measurements on fully processed bipolar junction transistors at room temperature. This work indicates that the unparalleled analytical power of electron-nuclear double resonance in the identification of paramagnetic point defects can be exploited in the study of defects within fully functional solid-state electronic devices. [ABSTRACT FROM AUTHOR]

A novel transistor with a graphene base embedded between two n-type silicon emitter and collector layers (graphene-base heterojunction transistor) is fabricated and characterized electrically. The base voltage controlled current of the device flows vertically from the emitter via graphene to the collector. Due to the extremely short transit time for electrons passing the ultimately thin graphene base, the device has a large potential for high-frequency RF applications. The transistor exhibits saturated output currents and a clear modulation of the collector current by means of the graphene base voltage. The vertical transfer current from the emitter via the graphene base to the collector is much lower than expected from device simulations. A comparison of the graphene-base transistor and a reference silicon n-p-n bipolar transistor is performed with respect to the main DC transistor characteristics. A common-emitter gain of larger than one has been achieved for the reference device while the graphene-base transistor so far exhibits a much lower gain. [ABSTRACT FROM AUTHOR]

The emergence of ionic-junction devices has attracted growing interests due to the potential of serving as signal transmission and translation media between electronic devices and biological systems using ions. Among them, fiber-shaped iontronics possesses a great advantage in implantable applications owing to the unique one-dimensional geometry. However, fabricating stable ionic-junction on curved surfaces remains a challenge. Here, we developed a polyelectrolyte based ionic-junction fiber via an integrated opposite charge grafting method capable of large-scale continuous fabrication. The ionic-junction fibers can be integrated into functions such as ionic diodes and ionic bipolar junction transistors, where rectification and switching of input signals are implemented. Moreover, synaptic functionality has also been demonstrated by utilizing the fiber memory capacitance. The connection between the ionic-junction fiber and sciatic nerves of the mouse simulating end-to-side anastomosis is further performed to realize effective nerve signal conduction, verifying the capability for next-generation artificial neural pathways in implantable bioelectronics. Ionic-junction devices are difficult to integrate with fiber-shaped tissues like nerves and muscles for applications in implantable bioelectronics due to their large size and bulk structure. Authors realize here easy to implant fiber-shaped iontronics through an integrated opposite charge grafting process, enabling the construction of ionic logic gates and artificial neural pathways. [ABSTRACT FROM AUTHOR]

This paper summarizes the results of investigations of bipolar transistors made in VESTIC (Vertical Slit Transistor-based Integrated Circuits) technology. This technology was proposed by W. Maly as an alternative to classical bulk CMOS technology. However, the basic VESTIC cell can be used not only to make field effect transistors but also to make bipolar transistors. Their structures differ in many ways from existing structures of bipolar transistors. The investigations reported here aim to answer the question: can VESTIC-based lateral bipolar transistors be useful as active devices, and can they be made technologically compatible with field effect VESTIC devices? The theoretical studies were followed by the fabrication and measurements of VESTIC-based p-n-p and n-p-n bipolar devices. Although the manufacturing technology available was far from optimal, working bipolar devices were obtained. The results show that VESTIC-based bipolar devices may achieve acceptable parameters if made with state-of-the-art manufacturing technology. The main outcome of the research reported in the paper is that p-n-p and n-p-n bipolar transistors with acceptable parameters may be fabricated, together with field effect devices, in VESTIC-based integrated circuits. As a result, the VESTIC technology could become the new original BiCMOS technology. [ABSTRACT FROM AUTHOR]

The paper considers schematics of low-power Output Stages (OS) and class AB Buffer Amplifiers (BA) for analog microcircuits realized on arsenide gallium n-channel field-effect transistors with control p-n junction and arsenide gallium bipolar p-n transistors within combined processes. The developed output stages are characterized by a relatively small static current consumption (about 100-200 A), provide operation at load resistances greater than 1-2 k, and have, as a rule, an increased input resistance. The maximum values of BA output currents for the positive polarity of the output voltage (vout) are determined by the width of the JFET channel, and for the negative vout half-wave, by the base current amplification factor of the BJT. In this connection, it is recommended to use compound Darlington p-n-p transistors in BA circuits. The results of computer simulation of the amplitude characteristics of pushpull BAs in LTspice at different load resistances show that the proposed circuit solutions provide the maximum amplitudes of positive and negative output voltages, close to the supply voltages. The circuit solutions considered are recommended for use in low-power operational amplifiers, including those operating under harsh operating conditions. The novelty of the paper lies in the investigation of a family of new pushpull class AB output stages for operational amplifiers, protected by 4 Russian patents and implemented under severe circuit restrictions on the types of GaAs transistors used (nJFET and nBJT). [ABSTRACT FROM AUTHOR]

Recently, nanowire detectors have been attracting increasing interest thanks to their advantages of high resolution and gain. The potential of using nanowire detectors is investigated in this work by developing a physically based model for Indium Phosphide (InP) phototransistor as well as by performing TCAD simulations. The model is based on solving the basic semiconductor equations for bipolar transistors and considering the effects of charge distribution on the bulk and on the surface. The developed model also takes into consideration the impact of surface traps, which are induced by photogenerated carriers situated at the surface of the nanowire. Further, photogating phenomena and photodoping are also included. Moreover, displacement damage (DD) is also investigated; an issue arises when the detector is exposed to repeated doses. The presented analytical model can predict the current produced from the incident X-ray beam at various energies. The calculation of the gain of the presented nanowire carefully considers the different governing effects at several values of energies as well as biasing voltage and doping. The proposed model is built in MATLAB, and the validity check of the model results is achieved using SILVACO TCAD device simulation. Comparisons between the proposed model results and SILVACO TCAD device simulation are provided and show good agreement. [ABSTRACT FROM AUTHOR]

The cumulative inverter losses and power consumption of a silicon insulated gate bipolar transistor (Si IGBT) and three types of silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) were evaluated on an electric motor test bench under a worldwide harmonized light vehicles test cycle (WLTC). SiC MOSFETs showed higher performance than Si IGBT regardless of the motor type and test vehicles. In the case of driving an interior permanent magnet synchronous motor (IPMSM), the latest 4th generation SiC MOSFET (SiC-4G) in ROHM has the lowest inverter loss and energy consumption compared with the other generations. In the case of driving an induction motor (IM), on the other hand, the 2nd generation SiC MOSFET (SiC-2G) in ROHM has the best energy consumption despite the fact that the inverter losses of SiC-2G are slightly larger than the loss of SiC-4G. The latest or later generation power device does not necessarily contribute to better performance in a total system by simply replacing early power devices. [ABSTRACT FROM AUTHOR]

In this paper, a low switching loss built-in diode of a high-voltage reverse-conducting insulated gate bipolar transistor (RC-IGBT) is proposed without deteriorating IGBT characteristics. It features a particular shortened P+ emitter (SE) in the diode part of RC-IGBT. Firstly, the shortened P+ emitter in the diode part can suppress the hole injection efficiency resulting in the reduced carriers extracted during the reverse recovery process. The peak of the reverse recovery current and switching loss of the built-in diode during reverse recovery is therefore lowered. Simulation results indicate that the diode's reverse recovery loss of the proposed RC-IGBT is lowered by 20% compared with that of the conventional RC-IGBT. Secondly, the separate design of the P+ emitter prevents the performance of IGBT from deteriorating. Finally, the wafer process of the proposed RC-IGBT is almost the same as that of conventional RC-IGBT, which makes it a promising candidate for manufacturing. [ABSTRACT FROM AUTHOR]

This paper presents a sub-microwatt sub-bandgap voltage and current reference that can generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) currents concurrently. The voltage reference is derived from the process-insensitive silicon bandgap voltage of a bipolar junction transistor, whereas the current reference is made by combining PTAT and CTAT currents. Line regulation is improved by incorporating cascode devices without an operational amplifier (opamp). Fabricated in a standard 0.18-µm CMOS process, the proposed bandgap reference occupies an active area of 0.4 mm2. The current and voltage reference ( I REF and V REF ) are measured as 170 mV and 21 nA, respectively, while the start-up settling response is measured as 20 ms at room temperature. The average temperature coefficient of I REF and V REF is 79.8 ppm/°C and 87.93 ppm/°C across the temperature range from − 40 to 120 °C, respectively. The power consumption is 134 nW at the minimum supply voltage of 1.2 V. The power supply ripple rejection of V REF is measured as − 10 dB at 100 kHz without any filtering capacitor, when the 1.6 V input line voltage is distorted by a 300-mVp-p ripple. The measured line sensitivity of the voltage and current reference is 0.142%/V and 0.757%/V, respectively. [ABSTRACT FROM AUTHOR]

In a high-power semiconductor power module where multiple chips are populated in parallel, the thermal imbalance problem arises. In this article, the next-generation standard high-voltage insulated-gate bipolar transistor module for high-speed railcar traction is investigated to characterize the internal thermal imbalance among paralleling chips and evaluate the impact on temperature distribution in field application. The former is accomplished by a new test algorithm with a purposely designed module sample, while the latter is achieved via an advanced electro-thermal simulation from chip level to system level. The experimentally verified thermal network among paralleling chips reveals the multiple reasons for the thermal imbalance. A comparison between the simulation and experimental results regarding the paralleling chips’ power-cycling scenario helps to confirm the effectiveness of the chip model, the thermal network, and the electro-thermal simulation approach. A further electro-thermal simulation shows that the module internal thermal imbalance can lead to significant junction temperature discrepancy among paralleling chips in traction inverter applications, which should be taken into consideration for the long-term reliability assessment. [ABSTRACT FROM AUTHOR]

A superjunction (SJ) insulated gate bipolar transistor (IGBT) featuring an embedded self-biased (ESB) n-type metal–oxide–semiconductor field-effect transistor (NMOS) between the P-pillar and the emitter is proposed and simulated. During the on-state, the NMOS is turned off to maintain high conductivity modulation, achieving a relatively low on-state voltage (Von). The P-pillar is connected to the emitter through the NMOS in the blocking state, which prevents premature breakdown at the corner of the trench gate. Consequently, a high breakdown voltage (BV) is ensured. During the turn-off period, the embedded self-biased NMOS turns on adaptively with the increasing potential of the P-pillar. An extra path is formed to extract excessive carriers in the drift region, thereby minimizing turn-off losses (Eoff). Numerical simulations show that a 48.9% reduction in Von is achieved for the proposed IGBT when compared with the conventional (Con.) SJ IGBT at the same Eoff. Furthermore, the Eoff of the proposed IGBT is reduced by 23.8% and the BV is improved by 21.5% compared to the SJ IGBT with a floating P-pillar (FP SJ IGBT) at the same Von. [ABSTRACT FROM AUTHOR]

A novel snapback-free superjunction reverse-conducting insulated gate bipolar transistor (SJ-RC-IGBT) is proposed and verified by simulation. In the SJ-RC-IGBT, the parasitic P/N/P/N structure as thyristor or Shockley diode demonstrates large conductivity due to an overabundance of carriers for reverse conduction. By preventing electrons from leaking across the N+ region at the collector side, the extra electron-blocking (EB) layer introduced in the SJ-RC-IGBT can dramatically enhance electron–hole pairs in the N/P-pillars. Hence, the SJ-RC-IGBT demonstrates a low on-state voltage (Von). In addition, snapback-free characteristics and a large safe operating area (SOA) are also achieved in the SJ-RC-IGBT. During the turn-off process, a significant amount of electrons are extracted by parasitic MOS across the EB layer at the collector side to decrease the turn-off loss (Eoff). According to the optimized results, the SJ-RC-IGBT with EB layer obtains an ultralow Eoff of 3.9 mJ/cm2 at Von = 1.38 V with 88% and 81% decreases, respectively, compared with the conventional reverse-conducting IGBT (CRC-IGBT) and superjunction IGBT (SJ-IGBT). [ABSTRACT FROM AUTHOR]

Commutation failure is one of the most important factors threatening the safety of multi-infeed high voltage direct current systems. To mitigate commutation failure, we have proposed a novel hybrid line-commutated converter by adding fully controlled devices to the conventional line-commutated converter. It aims to achieve auxiliary commutation and forced commutation with the help of fully controlled devices. Based on the novel hybrid line-commutated converter topology, the study investigates how to select suitable fully controlled devices and how to design the appropriate parameters of the devices. First, this article studied the general characteristics of reverse-blocking devices, including reverse-blocking integrated gate-commutated thyristor (RB-IGCT) and asymmetrical IGCT with diode (including fast recovery diode and standard recovery diode). Then, the novel commutation principle is carefully proposed and analyzed. The comprehensive simulation results and comparison study of the novel commutation principle are conducted. Then, according to the proposed commutation principle, the voltage and current working stress of devices are illustrated. According to these, vital features of devices, including recovery speed, on-state voltage, current conduction ability, surge current, maximum turn-off current, robustness, and volume of devices, are carefully analyzed and compared. Related experiments are conducted to present the vital characteristics of devices in the equivalent operating conditions in converters. Finally, the advantages and disadvantages of RB-IGCT and IGCT with fast recovery diode and standard recovery diode are comprehensively presented, which offers valuable reference considered in engineering applications. [ABSTRACT FROM AUTHOR]

Owing to the increased use of antibiotics, drug-resistant strains, including those that are resistant to the antibiotic vancomycin, have emerged, which has become a major problem. In Japan, sewage treatments consist of sterilization with chlorine; however, this may not be sufficient to inactivate these bacteria. In this study, impulse voltage was employed instead of chlorine to inactivate drug-resistant bacteria. The results showed that sterilization above 105 CFU/mL is possible with longer application times of applied voltages above 4.5 kV. The effectiveness of impulse-voltage-mediated sterilization increased as the temperature of the bacterial suspension increased. The number of bacteria sterilized via impulse voltage was correlated with conductivity when the number of bacteria sterilized by impulse voltage exceeded 105 CFU/mL. The sterilization rate achieved by the use of impulse voltage could be estimated immediately by measuring the electrical conductivity and without the need for using the culture method. [ABSTRACT FROM AUTHOR]

A 27-MHz wireless system with binary frequency shift keying (BFSK) modulation at 400-kHz is reported. The receiver has been designed to handle in-band interference corrupting the BFSK signal with the use of complex filters and amplitude comparison method. The BFSK modulation is carried out with a voltage-controlled oscillator before up-converting with a 27-MHz local oscillator. The bipolar junction transistors (BJT-based) power amplifier with 30% efficiency pumps 220 mW into a spiral antenna. The inductive-degenerated low-noise amplifier with a voltage of more than 30 dB amplifies an incoming signal before feeding into a mixer for complex direct down conversion. With deliberate Gaussian interference injection, the minimum ratios between the signal with interference and the interference only at the distance of 2.5, 10 and 15 m are 3.3, 8.5 and 11.5 dB, respectively at a maximum data rate of 20 kbps. Without any interference included, the system can achieve a data rate of 40 kbps at the maximum transmission distance of 15 m. Conceptually agreed with the presented bit-error-rate (BER) analysis, the BER measurements with Gaussian and single-tone/two-tone in-band interferences also confirm superiority offered by the amplitude comparison method where the signal-to-noise ratio is at 1 dB for BER=10-3 at 10 kbps (10 dB better than the phase detection counterpart). [ABSTRACT FROM AUTHOR]

Basing our findings on our previous pulsed laser testing results, we have experimentally demonstrated that there is an inflection point of a single event transient (SET) in the silicon-germanium heterojunction bipolar transistors (SiGe HBTs) with a decreasing temperature from +20 °C to −180 °C. Additionally, the changes in the parasitic resistivity of the carrier collection pathway due to incomplete ionization could play a key role. In this paper, we found that the incident-heavy ion's parameters could also have an important impact on the SET inflection point by introducing the ion track structures generated by Geant4 simulation to the TCAD transient simulation. Heavy ion with a low linear energy transfer (LET) will not trigger the ion shunt effect of SiGe HBT and the inflection point will not occur until −200 °C. For high LET ions' incidence, the high-density electron-hole pairs (EHPs) could significantly affect the parasitic resistivity on the pathway and lead to an earlier inflection point. The present results and methods could provide a new reference for the effective evaluation of single-event effects in bipolar transistors and circuits at cryogenic temperatures and provide new evidence of the SiGe technology's potential for applications in extreme cryogenic environments. [ABSTRACT FROM AUTHOR]

When evaluating the individual reliability of semiconductor devices by gradual failures for a given operating time, the value of the electrical parameter of a particular instance for this operating time is predicted using the simulation method. To obtain a prediction of an electrical parameter, it is necessary to have a simulation model in the form of a function of the relationship between a given operating time and the level of simulation impact. The simulation model is obtained with the help of preliminary studies (training experiment) of a training sample of semiconductor devices of the type of interest with the volume of approximately 50 ... 100 copies. The application of the model is reduced to the calculation of the level of simulation impact corresponding to a given operating time. The result of measuring the electrical parameter at the calculated level of the imitation impact in a new specimen of the same type that did not take part in the training experiment should be considered as a prediction of this parameter for a given operating time. An integral part of the preliminary research to obtain a simulation model is the testing of semiconductor devices of the training set for a long operating time, which can be tens of thousands of hours, which necessitates planning and conducting accelerated tests. The article substantiates the conditions for conducting accelerated forced tests in relation to high-power bipolar transistors of the KT872A type. The increased temperature and the reverse voltage applied to the collector junction of the transistors are chosen as factors accelerating the tests. The test acceleration coefficient is calculated relative to the operating mode of the transistors. Based on the results of the accelerated tests for the electrical parameter (collector-emitter saturation voltage), a mathematical model was obtained in the form of a dependence of its average value on the operating time. The presence of this model is necessary to determine the function of recalculating the given operating time of transistors to the value of the simulation impact.

In this paper, a single-event burnout (SEB)-hardened design for silicon-on-insulator lateral double-diffused MOSFET (SOI LDMOS) with a top polysilicon PN-junction diode (PN-LDMOS) is presented. By analyzing the hole current density of the device at different time points after a heavy-ion event, it is found that the introduced top polysilicon diode structure can reduce the hole current flowing to the source remarkably at a certain time. Thus, the voltage drop between the emitter and base of the parasitic NPN bipolar junction transistor (BJT) inherent in the device structure is reduced, and the deep p+ structure provides a low resistance path for the holes. The combined effect of these two structures effectively suppresses the turn-on of parasitic BJT and significantly reduces the risk of SEB occurrence. Compared to the traditional LDMOS (C-LDMOS), at a LET of 0.2 pC/μm, the SEB trigger voltage (V SEB) of PN-LDMOS is improved from 129 V to 200 V, and the safe operating area (SOA) ratio (η) is increased from 58.8 % to 80 %. And the combination of polysilicon diode and field plates also optimizes the surface electric field distribution, increasing the breakdown voltage from 219.4 V to 249.7 V. • Radiation-hardened SOI LDMOS using top polysilicon and SEB failure mechanism is investigated. • The top polysilicon diode reducing the number of holes flowing to the source electrode at the same time within a certain period of time, making the distribution of hole current flowing to the source at different time points more uniform. • The device can operate at a V DS of 199 V even in high energy ions with a LET of 0.2 pC/μm. • The role of the parasitic NPN BJT is critical to the SEB tolerance of the device. [ABSTRACT FROM AUTHOR]

This paper presents a bipolar junction transistor (BJT)-based CMOS temperature sensor for high accuracy, small-scale area, and low power consumption. A structure with a feedback amplifier biasing NPN transistors, combined with dynamic element matching (DEM), is proposed to avoid the effects of errors arising from the limited current gain of substrate PNP transistors in deep-submicron processes. Moreover, the switched capacitor (SC) integrators employ two single-stage cascode amplifiers for alternating cyclic sampling and integration, effectively simplifying the circuit design and reducing the operating voltage. The proposed sensor is fabricated with a standard 180 nm CMOS process, occupying an active chip area of 0.075 mm2. It consumes 39.1 μ W of power at room temperature, operating with a supply voltage of 1.8 V. The measurements indicate that the sensor exhibits an inaccuracy of ±0.97 °C (3 σ) across the temperature range from −40 °C to 120 °C following a single-point temperature calibration. [ABSTRACT FROM AUTHOR]

In this study, we introduced trace amounts of silver and nickel into 500 μm diameter copper wires to form micro-alloyed copper wires used in insulated gate bipolar transistors (IGBT). The addition of silver and nickel enhanced the mechanical properties of the conductors and suppressed the work hardening effect, significantly improving the power cyclic lifetime. Additionally, this study conducted chlorination and high-temperature oxidation test to compare the application characteristics of the heavy micro-alloyed copper wires with pure copper wires, through tensile and bending test, as well as electrical property comparisons. Finally, Cu 50Ni (50 ppm Ni) wires were selected and nickel ceramic substrates for wire bonding to evaluate module electrical properties and bonding reliability. In the chloride test, there was no significant pitting corrosion observed in copper wire, and the micro-alloyed copper wire outperformed the pure copper wires in terms of bending lifetime and power cycling performance. In the high-temperature oxidation test, an oxide layer of cuprous oxide formed on the surface of all wires. The pure copper wire exhibited a significant increase in resistance. Notably, the micro-alloyed copper wires had better resistance to oxidation. Regarding wire bonding, the use of Cu 50Ni wires and nickel ceramic substrates reduced the diffusion rate of nickel atoms from the substrate to the copper wire, forming a thinner alloy diffusion layer. This prevented electrical degradation and achieved high bonding reliability, especially under higher bonding forces. These findings confirm that micro-alloyed copper wires are suitable for high-power applications. • The advantages of adding Ni and Ag for copper micro-alloyed wires • The anti-oxidation mechanism of copper micro-alloyed wires • Two methods of application property analysis: EFM & bending tests [ABSTRACT FROM AUTHOR]

In this paper, we have studied, designed and realized a single-transistor chaotic generator with a smooth power spectrum of about −35 dBm in frequency bandwidth up to 1 GHz. The chaos generator model is described by a continuous-time six-dimensional autonomous system assuming an exponential nonlinearity. Chaotic behavior is characterized by bifurcation diagrams, Lyapunov exponents, phase portraits of the attractors and spectra of the oscillations, using both numerical and circuit simulations. Advanced Design System (ADS)-based simulations were carried out to support the theoretical analysis, and to validate the mathematical model. The simulations are carried out using real transistor parameters and taking into account the properties of the substrate, the influence of the board topology and the characteristics of the layout material. This simulation method known as EM/Circuit Co-Simulation allows the simulation results to approach as closely as possible to those of the experiments. In the light of the positive simulation results, the proposed structure is realized to demonstrate its feasibility, and to confirm the numerical results. The prototype is manufactured and mounted on a breadboard using the surface-mount devices and BFP193 bipolar junction transistor. After realizing the generator, we pushed it further towards perfection, through the proposal and realization of a broadband amplifier, in order to gain more bandwidth to improve the spectral characteristic of the generator, which makes it promising for many communication applications such as spread spectrum communication, direct chaotic communication, etc. [ABSTRACT FROM AUTHOR]

Memristors (abbreviation of memory and resistor), introduced as the fourth fundamental electrical circuit element, remember the electric charge that flowed through it. These nonlinear elements are considered as a class of two terminal resistive devices and offers a lot of possible applications in various areas. In this article, we review the dynamical behaviour of some electrical circuits with memristors. Initially, we show that a simple circuit with a capacitor and an inductor connected to a memristor exhibits periodic and chaotic attractors. After that, we show that the known Chua circuit, with a nonlinear resistance, can generate bifurcations and chaos. Substituting the nonlinear resistance by a memristor, the modified Chua circuit exhibits coexistence of attractors. Another known circuit, the Colpitts, is made of a combination of capacitors and inductors containing a bipolar junction transistor. We show that the modified Colpitts circuit, created by substituting the transistor by a memristor, presents multistability and coexistence of many attractors. [ABSTRACT FROM AUTHOR]

The heterostructure bipolar transistor solar cell architecture offers an attractive route to realize monolithic 3-terminal perovskite/silicon tandem solar cells compatible with both-side contact Si photovoltaic technologies. Essentially, the HBT implements two counter series diodes with the common third terminal realized at the interface between the two diodes through an interdigitated contact. Concrete design solutions require optimizing the HBT multilayer stack for maximum power conversion efficiency of the intrinsic cell and designing appropriate layouts for the current collecting grid of the middle terminal. In this work, we develop a modeling framework that combines electro-optical simulations of the intrinsic tandem stack with circuit-level simulations to quantify the impact of shadow and resistive losses associated with the metal contacts on the scalability of the cell size. We present a design of a HBT with homojunction silicon bottom cell that can surpass 40% efficiency with a perovskite bandgap of 1.55 eV, i.e. much higher than the limit efficiency of a series connected tandem with the same material system. Then, we explore the implications of the middle contact in terms of interdependence between the subcells and parasitic losses, by considering a top interdigitated layout and cell architectures with both homojunction and heterojunction silicon cells. We show that in most configurations proper grid design can enable the scaling up of these devices to large areas, and that the scalability can be markedly improved, especially for the case of Si heterojunction bottom cells, by developing a layout with overlapped grids. [ABSTRACT FROM AUTHOR]

We report a systematic study of process-related electrical defects in symmetric lateral NPN transistors on silicon-on-insulator (SOI) fabricated using ion implantation for all the doped regions. A primary objective of this study is to see if pipe defects (emitter-collector shorts caused by locally enhanced dopant diffusion) are a show stopper for such bipolar technology. Measurements of IC-VCE and Gummel currents in parallel-connected transistor chains as a function of post-fabrication rapid thermal anneal cycles allow several process-related electrical defects to be identified. They include defective emitter-base and collector-base diodes, pipe defects, and defects associated with a dopant-deficient region in an extrinsic base adjacent its intrinsic base. There is no evidence of pipe defects being a major concern in SOI lateral bipolar transistors. [ABSTRACT FROM AUTHOR]

Intelligent display with multifunctional integration is becoming the frontier and focus of current research on novel display technology. How to realize the single chip integration of lighting with other functions such as switching and driving remain the technical and scientific problems that are desiderated to solve. This article proposes a novel idea of a light‐emitting triode (LET), in which light‐emitting diode (LED) and bipolar junction transistor (BJT) are vertically integrated on a single GaN chip with the same GaN processing. The photoelectrical performances of this "LED on BJT" structure are investigated using finite element simulation. It is verified that LET with electrical–optical modulation and amplification capabilities could be achieved simultaneously. By optimizing the device structure and the doping concentrations of each epitaxial layers, the LET can be operated at a low modulation current injection in the range of tens of microamperes. Therefore, the LET is expected to be directly driven by IC circuits without additional amplifier circuits. Meanwhile, the LET cut‐off frequency can reach more than 80 MHz, allowing the applications of pulse width modulation (PWM) driving and visible light communications. [ABSTRACT FROM AUTHOR]

A new precision-aware subthreshold-based MOSFET voltage reference is presented in this paper. The circuit was implemented TSMC−40 nm process technology. It consumed 9.6 μ W at the supply voltage of 1.2 V. In this proposed work, by utilizing subthreshold-based MOSFET instead of bipolar junction transistor (BJT), relatively lower power consumption was obtained in the design while offering comparable precision to that offered by its BJT counterpart. Through the proposed second-order compensation, it achieved the temperature coefficient (T.C.) of 3.0 ppm/ °C in the TT corner case and a 200-sample Monte-Carlo T.C. of 12.51 ppm/ °C from −40 °C to 90 °C. This shows robust temperature insensitivity. The process sensitivity of V r e f without and with trimming was 2.85% and 0.75%, respectively. The power supply rejection (PSR) was 71.65 dB at 100 Hz and 52.54 dB at 10 MHz. The Figure-of-Merit (FOM) for the total variation in output voltage was comparable with representative BJT circuits and better than subthreshold-based MOSFET circuits. Due to low T.C., low process sensitivity, and simplicity of the circuit architecture, the proposed work will be useful for sensor circuits with stringent requirements or other analog circuits that require high precision applications. [ABSTRACT FROM AUTHOR]

In this article, a novel method is proposed to reduce the dc-link capacitance of the brushless dc motor (BLDCM) system. In the proposed strategy, the charging mode of dc-link capacitor is designed to improve the energy stored by dc-link capacitor in the charging process instead of reducing the discharge time of dc-link capacitor used in previous article. The new modulation strategy and controller is designed to pump the dc-link capacitor voltage and ensure that it exceeds the ac voltage peak. The proposed modulation strategy has three vectors. The charging vector is used to improve the dc-link capacitor voltage, and the effective vector and zero vector are used to adjust the motor speed. For practical application, we provide an engineering calculation method to get the dc-link capacitance, and prove that the dc-link voltage can exceed the average voltage of the BLDCM. The experimental results verify the correctness of the theoretical analysis and the feasibility of the proposed method. [ABSTRACT FROM AUTHOR]