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In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 /spl mu/m process parameters, the results show that INL < /spl plusmn/0.4 LSB and DNL < /spl plusmn/0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

This paper presents a novel VLSI architecture for a fully parallel static type content addressable memory with low-power, low-voltage, and high-reliability features. In this paper, the proposed CAM word structure adopts a static pseudo nMOS circuit that not only improves system reliability, but also prevents using a clock signal to drive the overall system. In order to reduce static power occurring in the proposed CAM word structure, a precomputation approach is used to turn off a major part of the pseudo nMOS circuits. The whole design was simulated by HSPICE with the TSMC 0.35 /spl mu/m SPQM CMOS process. With a 128 words by 30 bits CAM size, the simulation results indicate that the proposed circuit operates up to 250 MHz with a power-performance metric less than 59 fJ/bit/search.

This paper presents a novel VLSI architecture for a fully parallel precomputation-based content addressable memory (PB-CAM) with low-power, low-cost, low-voltage, and high-reliability features. This design is based on a precomputation skill that saves not only power consumption of the PB-CAM system, but also reduces transistor count and operating voltage of the PB-CAM cell. In addition, the proposed CAM word structure adopts a static pseudo nMOS circuit design to improve system reliability. The whole design was fabricated with the TSMC 0.35 /spl mu/m SPQM CMOS process parameters under 3.3 V supply voltage. With a 128 words by 30 bits CAM size, the measurement results indicate that the proposed circuit works up to 100 MHz with a power consumption of less than 33 mW. Furthermore, the low voltage measurement results show that the proposed circuit works up to 30 MHz under 1.5 V supply voltage.

Sorting plays an important role in data and digital signal/image processing. We propose a sorter system architecture based upon a novel maskable WTA/MAX circuit design. The proposed sorter is able to sort an arbitrary N items of data with a simple control mechanism. No extra memory space is needed for storing temporary data during the sorting process. To achieve higher sorting speed, the proposed sorting system can be expanded easily by a simple hardware cascade. We use an 8-bit sorter design to verify our proposed architecture. A modular concept is adopted and the circuit interconnection is fairly regular. As a result, the bit-length of our proposed sorter can be easily augmented to 16-bit or 32-bit. The sorter chip has been manufactured by a TSMC 0.35 /spl mu/m 1P4M process with a 32 S/B package. Experimental results show that our chip functions correctly at 50 MHz at 3.3 V power supply voltage.

This paper presents a novel circuit for the pipelined and expandable sorting architecture that processes thirty-two 16-bit patterns at a time. This design is based on a compare-swap cell which can easily be cascaded to improve sorting performance. The sorting architecture combines suitable algorithm to sort arbitrary N data patterns. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The whole design was fabricated by TSMC 0.35/spl mu/m SPQM CMOS process. The estimation results indicate that the sorter can work up to 66MHz with the power consumption less than 20mW under 3.3V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors.

This paper presents a novel circuit for the k-WTA/Sorting network that processes eight 8-bit patterns. This design is based on a maskable WTA/MAX circuit which generates maximum value and winner with maskable skill. It can obtain the whole system functions: WTA/MAX/k-WTA/Sorter without adding any extra components. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The chip was fabricated with the TSMC 0.35/spl square/m SPQM CMOS process. Experimental results indicate this chip can work up to 66 MHz with power consumption less than 10 mW at 3.3 V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors.