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We designed and fabricated 4H-SiC PIN avalanche photodiodes (APD) for UV detection. The thickness of an intrinsic layer in a PIN structure was optimized in order to achieve the highest quantum efficiency at the wavelength of interest. The optimized 4H-SiC PIN APDs exhibited a maximum external quantum efficiency of > 80% at the wavelength of 280nm and a gain greater than 40000. Both electrical and optical characteristics of the fabricated APDs were in agreement with those predicted from simulation.

Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Past studies of many sources of error have led to rosette optimization and demonstrated that temperature-compensated stress extraction should be used whenever possible. In this work, we extend the error analysis to include the inherent uncertainty in the measured values of the sensor resistances and the temperature at time of the measurement. The stresses in an under-filled flip chip package are calculated using finite element simulation and utilized to evaluate the stress dependent sensitivities across the die surface. Monte Carlo simulation results confirm that temperature compensated rosette configurations should be utilized whenever possible.

Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Previous analyses of many sources of error have led to rosette optimization and the realization that temperature compensated stress extraction should be used whenever possible. A previous paper initated a study of the errors in stress extraction due to the inherent uncertainty in knowledge of the values of the piezoresistive coefficients and temperature. In this work, we apply the earlier results to an analysis of the sensitivities and errors in the extracted stresses on an integrated circuit die in a flip-chip package. A finite-element model for a basic flip-chip configuration is utilized to estimate the stress across the surface of the silicon die. These results are used to evaluate the stress sensitivities to coefficient and temperature errors throughout the die surface. The sensitivities are stress dependent and vary widely from very small to very large over the die surface. The results confirm that temperature compensated rosette configurations should be utilized whenever possible.Copyright © 2009 by ASME

Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Previous analyses of many sources of error have led to rosette optimization and the realization that temperature compensated stress extraction should be used whenever possible. However, error in stress extraction due to the inherent uncertainty in knowledge of the values of the piezoresistive coefficients has not been explored in detail. In this work, direct analysis of the sensitivities of the extracted stresses to uncertainties in the piezoresistive coefficients is presented. The sensitivities are found to be stress dependent and therefore vary widely from very small to very large over the die surface. The results indicate that temperature compensated rosette configurations should be utilized whenever possible. Study of these sensitivities may lead to new rosette optimizations.Copyright © 2008 by ASME

Stress sensing test chips are widely utilized to investigate integrated circuit die stresses arising from assembly and packaging operations. The test chips incorporate resistor or transistor sensing elements that are able to measure stresses by observing the changes in their resistivity or carrier mobility. This piezoresistive behavior of such sensors is characterized by three piezoresistive coefficients, which are electro-mechanical material constants. We are interested in stress characterization over a very broad range of temperatures. However, the literature provides limited data over the desired range, and even the data at room temperature, exhibit wide discrepancies in magnitude as well as sign. This work focuses on an extensive experimental study of the temperature dependence of the piezoresistive coefficients, π11 , π12 , and π44 , for both p- and n-type silicon. In order to minimize errors associated with misalignment with the crystallographic axes on (100) silicon wafers, anisotropic wet etching was used in this work to accurately locate the axes. A special four-point bending apparatus has been constructed and integrated into an environmental chamber capable of temperatures from −155 to +300°C. Experimental calibration results for the piezoresistive coefficients as a function of temperature from −150°C to +125°C are presented and compared and contrasted with existing values from literature. Measurements were performed using stress sensors fabricated on (100) silicon mounted on PCB material including both die-on-beam and strip-on-beam mounting techniques. Four-point bending (4PB) was used to generate the required stress, and finite element simulations have been used to determine the actual states of stress in the silicon material.Copyright © 2007 by ASME

Stress sensing test chips are used to investigate die stresses arising from assembly and packaging operations. The chips incorporate resistor or transistor sensing elements that are able to measure stresses via the observation of the changes in their resistivity/mobility. The piezoresistive behavior of such sensors is characterized by three piezoresistive (pi) coefficients, which are electro-mechanical material constants. Stress sensors fabricated on the surface of the (111) silicon wafers offer the advantage of being able to measure the complete stress state compared to such sensors fabricated on the (100) silicon. However, complete calibration of the three independent piezoresistive coefficients is more difficult and one approach utilizes hydrostatic measurement of the silicon “pressure” coefficients. We are interested in stress measurements over a very broad range of temperatures, and this paper present the experimental methods and results for hydrostatic measurements of the pressure coefficient of both n- and p-type silicon over a wide range of temperatures and then uses the results to provide a complete set of temperature dependent piezoresisitive coefficients for the (111) silicon.Copyright © 2007 by ASME

Stress sensing test chips are used to investigate die stresses arising from assembly and packaging operations. The chips incorporate resistor or transistor sensing elements that are able to measure stresses via the observation of the changes in their resistivity/mobility. The piezoresistive behavior of such sensors is characterized by three piezoresistive (pi) coefficients, which are electro-mechanical material constants. In most prior investigations, calibration of the piezoresistive coefficients has been performed at room temperature. The limited data at other temperatures, and even the data at room temperature, exhibit wide discrepancies in magnitude as well as sign. Thus the literature data limits the accuracy of test chip stress measurements made at other temperatures. We are interested in stress measurements over a very broad range of temperatures, 77K - 450K or more, and this work focuses on an extensive experimental study of the temperature dependence of the piezoresistive coefficients of silicon. Calibration has been performed using four-point-bending of chip-on-beam specimens. A special four-point bending apparatus has been constructed and integrated into an environmental chamber capable of conditioning to temperatures from -185 to 300 C. Finite element analysis has been used to calculate the stress states applied to the calibration samples. Our first test results show that the piezoresistive coefficients for p- and n-type silicon decrease monotonically with increasing temperature over the temperature range -150 to 100 C. This work is currently being extended to higher temperature and performing temperature dependent hydrostatic pressure tests

In this study, we investigated the process-dependent dynamic on-resistance [RDS(on)] characteristics of recessed AlGaN/GaN-on-Si metal–oxide–semiconductor heterojunction field-effect transistors with a SiO2 gate oxide. In order to improve the dynamic RDS(on) characteristics, the processing technology was carefully optimized, including post-metallization annealing and field plate formation. A threshold voltage of 2.0 V was achieved with a breakdown voltage of 1070 V. The fabricated device exhibited a DC RDS(on) of 5.22 mΩcm2 with very stable dynamic RDS(on) characteristics, i.e., a less than 20% increase up to the drain voltage of 200 V.