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For device modelling purposes, the geometry dependence of the external collector resistance has been investigated. Firstly, the collector resistance is split into a perfectly 1D vertical resistance and a 2D horizontal contribution. Using specific test structures and DC measurements, geometry independent parameters are then extracted. An analytical scalable formula based on Fourier techniques finally computes both components for a given geometry by taking into account the current distribution in the horizontal layer. This new method is applied to a double poly BiCMOS technology and results are discussed.

Based on different geometries of bipolar transistors, a new scalable method to determine the parasitic capacitances is presented. The total capacitance measured from cold S parameters could be split in an area junction capacitance, a peripheral junction capacitance and a constant oxide contribution. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS technology, and results are discussed.

For process monitoring and device modeling, a new method to determine the different components of the base resistance of bipolar transistors has been developed. Dual base test structures have been improved to extract the sheet resistance value of each of these components using dc measurements. This method is applied to a state-of-art double poly ST BiCMOS technology, and results are discussed.

Both reduction in device sizes and enhanced increase in current densities lead to concern about the impact of self-heating effect on device electrical characteristics. Moreover in power transistors applications, devices are connected in parallel, which follows to also consider thermal interaction between devices. In this study a dedicated structure is designed in order to investigate both thermal phenomena and their effect on electrical measurements. Measurements validate a SPICE model associated to the HICUM level 2 version 2 compact model taking into account temperature variation due to self-heating and thermal coupling.

The recent development of BiCMOS and advanced bipolar and merged bipolar CMOS and DMOS technologies requires the enhancement of both models and parameter extraction strategies for the bipolar device. In order to take into account special behavior such as the base push-out effect or the nonideal base current, new features have been added to the classical SPICE BJT (bipolar junction transistor) model. A flexible software tool has been developed to allow the use of different parameter extraction schemes suitable for a wide range of device behaviors. Experimental validations have been performed in DC analysis. The RMS (root mean square) error on current gain is less than 2%. >

A new method for extracting the area, peripheral and corner capacitance components of bipolar junction transistor, using measurements versus bias on a number of different structures is presented and validated. The same model with different parameters is used for the three components. Validation has been made using a quasi-2D simulator. Finally, it is shown that this method gives accurate results regarding the goodness of fit.

This paper presents an efficient method to evaluate with accuracy the partitioning of the base-collector depletion capacitance through the base resistance by the way of the SPICE Gummel-Poon (SGP) model parameter X/sub CJC/. This parameter is directly extracted, without any optimization, from the real part of the high-frequency small-signal admittance Y/sub 12/ in common emitter configuration.

A new physical model which describes the self-heating phenomena - the device temperature rise due to its own internal power dissipation - is presented. It permits the accurate temporal response determination of the BJT junction's temperature rise. This model is validated using measurements from an silicon-germanium heterojunction bipolar transistor (Si-Ge HBT).

This paper presents a extraction procedure for the transit time parameters of the HICUM bipolar compact model. The extraction routines use as input the measured small-signal current gain in the -20 dB/decade falloff region as a function of the collector current and the collector-emitter (or collector-base) voltage. All HICUM transit time parameters are extracted in a straightforward manner, no optimisation is necessary. Especially the critical current value ICK is determined in a self consistent way.

We present a new method to determine the intrinsic and extrinsic base-emitter and base-collector junction capacitances parameters of bipolar transistors as a function of junction bias. The capacitance specific compact model parameters (pp, V,y) can be extracted for the intrinsic as well as for extrinsic part. The results can be introduced in recent compact bipolar models.

A one micron bipolar process using trench isolation and polysilicon emitter has been evaluated and characterised. The demonstration of yield was achieved on a 10000 gate VLSI circuit.

International audience; This paper presents a unified physical formulation for the avalanche effect in silicon-germanium heterojunction bipolar transistors (SiGe HBTs) at different injection levels. Based on an analytical description of the resulting electric-field distribution, a closed-form analytical expression for the multiplication factor is derived and has been implemented in the HICUM compact model. The model accuracy close to and beyond the common-emitter breakdown voltage BV CEO has been assessed over a wide temperature range in comparison to measurements of SiGe HBTs with different collector doping profiles and emitter geometries. Index Terms-Avalanche, compact model, high injection, impact ionization, kirk effect, safe operating area (SOA), silicon-germanium heterojunction bipolar transistors (SiGe HBTs).

This paper presents an investigation of hot carrier degradation in advanced SiGe HBTs. This failure mechanism is observed under mixed mode stress conditions. Its physical location is examined through DC measurements from 2D transistors $(\mathrm{L_{E}} > > \mathrm{W}_{\mathrm{E}})$ with different emitter width WE. TCAD simulations were performed to confirm its physical origin and location. The methodology permits to identify the origin of the degradation mechanism located at the emitter-base spacer interface. It is based on the scalable analysis of the DC characteristics measured after stressing the devices during 10 000s under mixed mode (MM) stress conditions. This study confirms the mechanism responsible of the MM degradation for SiGe HBTs.

This paper deals with the reduction of the process thermal budget in a 55-nm BiCMOS technology for improving SiGe HBTs transit frequency, f T . Since MOSFETs are directly impacted by this modification, process adjustments are implemented to recover performances and parametric yield. Spike annealing temperature reduction, thermal re-oxidation replacement and Dynamic Surface Annealing implementation are discussed. A 355 GHz F t / F Max HBT compatible with current 55-nm MOSFET models is demonstrated.