Search

Problem statement: The design and implementation of a sinusoidal Pulse-Width Modulation (PWM) generator for a single-phase hybrid power filter is presented. Approach: The PWM was developed in an Altera[R] Flex 10 K Field Programmable Gate Array (FPGA) and the modulation index was selected by calculating the DC bus voltage of the active filter through a digital controller, by Proportional-Integral-Derivative (PID) technique. Results: Experiment results showed the proposed active power filter topology to be capable of compensating the load current and the voltage harmonic, up to IEC limit. Conclusion: The implemented PWM generator using an FPGA required less memory usage while providing flexible PWM patterns whether same phase, lagging, or leading, the reference voltage signal. Key words: Active power filter, PWM, FPGA, power quality, INTRODUCTION Pulse width modulation techniques have been intensively researched in the past few years. Methods, of various concept and performance, have been developed and described. Their design implementation depends on [...]

A fully hardware-based real-time digital wide-band quadrature demodulation processor based on the Hilbert transform is described for processing ultrasound radio frequency signals. The results have shown that the implementation by using only slices and dedicated digital multipliers of a low-cost and low-power field-programmable gate array (FPGA) is accurate relative to a comparable software-based system and they are obtained with a piezoelectric transducer without postprocessing.

A back-end processing system involving high-speed signal processing functions to form and exhibit an image is developed for real-time visualization of the mouse heart. The studies have shown that high-speed back-end processing system is capable of providing high spatial resolution images with fast temporal resolution.

We present a channel signal-to-noise ratio (SNR) estimator for M-ary phase shift keying (M-PSK) and differential M-PSK. The estimator is non data aided and is shown to have the following advantages: 1) It does not require prior carrier synchronization; 2) the estimator has a compact fixed-point hardware implementation suitable for field-programmable gate arrays and application-specific integrated circuits; 3) it requires only 1 sample/symbol; 4) accurate estimates can be generated in real rime; and 5) the estimator is resistant to imperfections in the automatic gain control circuit. We investigate the proposed estimator theoretically and through simulations. In particular, we investigate the required quantization necessary to achieve a good estimator performance. General formulas are developed for SNR estimation in the presence of frequency-flat slow fading, and specific results are presented for Nakagami-m fading. The proposed estimator is then compared with other SNR estimators, and it is shown that the proposed method requires less hardware resources while, at the same time, providing comparable or superior performance. Index Terms--Application-specific integrated circuit (ASIC), binary phase-shift keying (BPSK), carrier loop, channel estimation, demodulation, differential phase-shift keying (DPSK), digital communications, efficient, estimation, fading, field-programmable gate array (FPGA), fixed-point, hardware, implementation, M-ary phase-shift keying (MPSK), modulation, Nakagami, phase-locked loop, quaternary phase-shift keying (QPSK), real-time, receivers, signal-to-noise ratio (SNR), synchronization, wireless.

The CDF Run II [1] Level 2 calorimeter trigger is implemented in hardware and is based on a simple algorithm that was used in Run I. This system has worked well for Run II at low luminosity. As the Tevatron instantaneous luminosity increases, the limitation due to this simple algorithm starts to become clear. As a result, some of the most important jet and MET (Missing ET) related triggers have large growth terms in cross section at higher luminosity. In this paper, we present an upgrade of the L2CAL system which makes the full calorimeter trigger tower information directly available to the Level 2 decision CPU. This upgrade is based on the Pulsar [2], a general purpose VME board developed at CDF and already used for upgrading both the Level 2 global decision crate [3] and the Level 2 Silicon Vertex Tracking [4]. The upgrade system allows more sophisticated algorithms to be implemented in software and both Level 2 jets and MET can be made nearly equivalent to offline quality, thus significantly improving the performance and flexibility of the jet and MET related triggers. This is a natural expansion of the already-upgraded Level 2 trigger system, and is a big step forward to improve the CDF triggering capability at Level 2. This paper describes the design, the hardware and software implementation and the performance of the upgrade system. Index Terms--Calorimeter, CDF, FPGA, HEP, trigger.

Bilateral control systems are strongly required to apply to endoscopic surgeries. It is necessary that the system has enough degrees of freedom for applying various operation procedures including endoscopic surgery. When the degrees of freedom of the system are increased, the amount of control calculation is also increased, and it is hard to keep sampling periods short. The bilateral control systems, however, require comparatively shorter sampling periods, particularly the control system based on an acceleration control system. Hence, it is a difficult issue to increase the degrees of freedom of the bilateral control system. In this paper, the sampling period is kept short in the multi-degree of freedom system by using field programmable gate arrays as processors. The bilateral control system based on the acceleration control system is implemented in a robot system, which has 12 DOF, and some experimental results are shown, and the errors between the response of the master and slave robots are discussed. Index Terms--Acceleration control, bilateral control, field-programmable gate array (FPGA), surgical robot.

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.compeleceng.2008.06.003 Byline: Santi P. Maity (a), Malay K. Kundu (b), Seba Maity (c) Keywords: Authentication; Digital watermarking; Fast Walsh transform; FPGA; QoS; VLSI Abstract: Spread spectrum (SS) watermarking for multimedia signal becomes appealing due to its high robustness attribute and is used widely for various applications. Some of these applications essentially demand development of low cost algorithms so that they can be used for real time services such as broadcast monitoring, security in communication etc. In recent time one popular non-conventional application of digital watermarking becomes promising that assesses blindly the QoS (quality of services) of the multimedia services which is expected to be offered by the future generation mobile radio network. Majority of the existing SS watermarking schemes suffer from high computation cost and complexity leading to the difficulty for real time implementation and limits their usage for the above mentioned applications. This paper proposes fast Walsh transform (FWT) based SS image watermarking scheme that serves the dual purposes of authentication in data transmission as well as QoS assessment for digital media through dynamic estimation of the wireless channel condition. Fast Walsh transform offers low computation cost for implementation, smaller change in image (multimedia signal) information due to data embedding and ease of hardware realization. VLSI implementation using field programmable gate array (FPGA) has been developed to make it suitable for real time implementation. Author Affiliation: (a) Department of Information Technology, Bengal Engineering and Science University, Shibpur P.O. Botanic Garden, Howrah 711 103, India (b) Center for Soft Computing Research and Machine Intelligence Unit, Indian Statistical Institute, 203, B.T. Road, Kolkata 700 108, India (c) Department of EI and ECE, College of Engineering and Management, Kolaghat, P.O. Mecheda, Midnapur East 721 171, India

The 'split ADC' architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms. Index Terms--Adaptive systems, analog-digital conversion, calibration, digital background calibration, mixed analog-digital integrated circuits, self-calibrating.

This paper presents two area-efficient algorithms and their architectures based on CORDIC. While the first algorithm eliminates ROM and requires only low-complexity barrel shifters, the second eliminates barrel shifters completely. As a consequence, both the algorithms consume approximately 50% area in comparison with other CORDIC designs. Further, the proposed algorithms are applicable to the entire range of angles. The FPGA implementations consume approximately 8% LUTs of a Xilinx Spartan XC2S200E device and have a slice-delay product of about 3. Convergence proofs for the algorithms are presented. Experimental comparisons with prior CORDIC designs confirm the efficacy of the proposed designs. Index Terms--Barrel shifter, coordinate rotation digital computer (CORDIC), extended range, low area and high throughput implementation.

The novel field-programmable-gate-array (FPGA) technology is able to combine an embedded processor and an application intellectual property to be a system-on-a-programmable-chip developing environment. Therefore, this paper presents a motion control IC for the X-Y table under this novel FPGA technology. The proposed motion control IC has two modules. One module performs the functions of the motion trajectory and two position/speed controllers for the X-Y table. The other module performs the functions of two current vector controllers of permanent-magnet synchronous motor drives. The former is implemented by software using a Nios II embedded processor due to the complicated control algorithm and low-sampling-frequency control (motion trajectory and position control: less than 1 kHz). The latter is implemented by hardware in the FPGA owing to the requirements of high-sampling-frequency control (current loop: 16 kHz; PWM circuit: 4-8 MHz) but simple computation. As a result, the hardware/software codesign technology can make the motion controller of the X-Y table more compact, flexible, perform better, and less costly. Index Terms--AC motor drives, field-programmable gate arrays (FPGAs), fuzzy control, motion control.

In this paper, we examine the potential of applying concatenated low-density parity-check (LDPC) and Bose-Chaudhuri-Hocquenghem (BCH) coding for magnetic recording read channel with a 4 kB sector format. One key observation for such concatenated coding systems is that the overall error correction capability can be improved by exploiting the iteration-by-iteration bit error number oscillation behavior in case of inner LDPC code decoding failures. Moreover, assisted by field programmable gate array (FPGA)-based simulation platforms, empirical error-correcting performance analysis can reach a very low sector error rate (e.g., [10.sup.-10] and below), which is almost infeasible for LDPC-only coding systems. Finally, concatenated coding can further reduce the silicon cost. By implementing a high-speed FPGA-based perpendicular recording read channel simulator, we investigate a 4 kB rate-15/16 concatenated coding system with a 512-byte rate-19/20 inner LDPC code and an outer 4 kB BCH code. We apply a decoding strategy that can fully utilize the bit error number oscillation behavior of inner LDPC code decoding, and show that its sector error rate drops down to [10.sup.-11]. For the purpose of comparison, we use the FPGA-based simulator to empirically observe the performance of 4 kB rate-15/16 LDPC and Reed-Solomon (RS) codes down to [10.sup.-7]-[10.sup.-8]. Finally, we estimate the silicon cost of this concatenated coding system at 65 nm node, and compare it with that of the RS-only and LDPC-only coding systems. Index Terms--Application-specific integrated circuit (ASIC), BCH, concatenated, field programmable gate array (FPGA), low-density parity-check (LDPC).

This paper proposes a new architecture of delta-sigma (DS) modulator suitable for RF digital transmitter design. This novel architecture considerably reduces the speed requirements of the digital signal processing block. The novelty lies in the implementation of a specific fully digital up-conversion in combination with a low-pass DS modulator to produce high-frequency digital-like signals, which can be used to drive highly efficient switching-mode power amplifiers. The proposed architecture is suitable for reconfigurable all-digital, multistandard and multiband wireless transmitters. The novel transmitter architecture has been validated using simulation and implemented on a field-programmable gate array development board for two different signals, code division multiple access and orthogonal frequency division multiplex. Index Terms--Field-programmable gate array (FPGA), low-pass (LP) delta-sigma (DS), RF transmitter.

This paper investigates the multisampling techniques applied to the current control in active-power-filter (APF) applications. In APF applications with digital control, the main bandwidth limitation derives from A/D conversion and computational delays and the sampling-related delay of the digital pulsewidth modulation (DPWM). Using field-programmable gate arrays and fast A/D converters for the control implementation, it is possible to minimize the former two; thus, the overall phase lag is dominated by the DPWM, which can strongly be reduced by the multiple-sampling approach, breaking bandwidth limitations of single-sampled solutions. Moreover, as the multisampling approach triggers nonlinear behaviors that can negatively impact the filter-compensating capabilities, a solution based on a simple digital filter is proposed which linearizes the system behavior and does not waste the multisampling advantages. Simulation and experimental results on a 10-kVA prototype confirm the theoretical expectations. Index Terms--Active power filters (APFs), digital control, multisampling.

The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used in radiation environments such as space. Triple modular redundancy (TMR) is the most frequently used SEU mitigation technique but is very expensive in terms of area and power costs. These costs can be reduced by sacrificing some reliability and applying TMR to only part of the FPGA design. Our partial TMR method focuses on the most critical sections of the design and increases reliability by applying TMR to continuous sections of the circuit. We introduce an automated software tool that uses the Partial TMR method to apply TMR incrementally at a very fine level until the available resources are utilized. Thus the tool aims to gives the maximum reliability gain for the specified area cost. Index Terms--Aerospace industry, fault injection, fault tolerance, field programmable gate arrays (FPGAs), proton accelerator, radiation effects, reliability, single-event upset (SEU), triple modular redundancy (TMR).

As SRAM-based field-programmable gate arrays (FPGAs) are introduced in safety- or mission-critical applications, the availability of suitable Electronic Design Automation (EDA) tools for predicting systems dependability becomes mandatory for designers. Nowadays designers can opt either for workload-independent EDA tools, which provide information about system's dependability disregarding the workload the system is supposed to elaborate when deployed in the mission, or workload-dependent approaches. In this paper, we compare two tools for predicting the effects of soft errors in circuits implemented using SRAM-based FPGAs, a workload-independent one (STAR) and a workload-dependent one (FLIPPER). Experimental results show that the two tools are complementary and can be used fruitfully for obtaining accurate predictions. Index Terms--Dependability, fault injection, field-programmable gate array (FPGA), single-event effects (SEVs), triple modular redundancy (TMR).

In this paper we present an analytical analysis of the fault masking capabilities of triple modular redundancy (TMR) hardening techniques in the presence of multiple cell upsets (MCUs) in the configuration memory of SRAM-based field-programmable gate arrays (FPGAs). The analytical method we developed allows an accurate study of the MCUs provoking domain crossing errors that defeat TMR. From our analysis we have found that most of the failures affect configurable logic block's routing resources. The experimental analysis has been performed on two realistic case study circuits. Experimental results are presented and discussed showing in particular that 2-bits MCUs may corrupt TMR 2.6 orders of magnitude more than single cell upsets (SCUs). Index Terms--Analytical analysis, field-programmable gate array (FPGA), multiple cell upset, triple modular redundancy (TMR).

We present an experimental analysis of alpha-induced soft errors in 90-nm low-end SRAM-based FPGAs. We first assess the relative sensitivity of the configuration memory bits controlling the different resources in the FPGA. We then study how SEU accumulation in the configuration memory impacts on the reliability of unhardened and hardened-by-design circuits. We analyze different hardening solutions comprising the use of a single voter, multiple voters, and feedback voters implemented with a commercial tool. Finally, we present an analytical model to predict the failure rate as function of the number of bit-flips in the configuration memory. Index Terms--Alpha particles, FPGA, radiation effects, TMR.

For high-speed plane-wave filtering applications, real.time 2-D spatio-temporal linear-array broadband beam filters are required, operating at temporal frame rates in excess of hundreds of megahertz. The corresponding application specific VLSI circuits must have low critical-path latencies. A novel high-speed systolic array architecture for a first-order 2-D broadband frequency-planar spatio-temporal beam filter is proposed for this purpose and employs a field-programmable gate array (FPGA) circuit where the critical path latency is minimized by timing optimization of inter- and intra-parallel processor pipelines, together with 3-D look-ahead techniques. The method facilitates single-chip VLSI circuit implementations operating at real-time frame rates of several hundred megahertz. Index Terms--2-D, array, beam, broadband, digital, digital signal processing (DSP), field-programmable gate array (FPGA), filter, infinite-impulse response (IIR), plane wave, sensors, systolic, VLSI.

Although the maximum-likelihood decision-feedback equalization (ML-DFE) detection method for multi-input multioutput (MIMO) system leads to a good compromise between the performance and the complexity, the computational complexity of the ML part in the ML-DFE is still large. This paper describes a modified maximum-likelihood (MML) algorithm, which reduces the computational complexity of the original ML algorithm significantly without degrading the performance. Then, based on the MML algorithm, we propose the MML-DFE, which has the same performance as the ML-DFE but has much lower complexity. Both the ML-DFE block and MML-DFE block for 4 x 4 MIMO system have been implemented in field-programmable gate array to verify the functional correctness and the complexity advantage. Index Terms--Decision-feedback equalization (DFE), maximum-likelihood (ML) detection, muiti-input multi-output (MIMO).

This article presents an event and pulse node hardware module (EPN) developed for use in control and data acquisition (CODAC) in current and upcoming long discharges nuclear fusion experiments. Its purpose is to allow real time event management and trigger distribution. The use of a mixture of digital signal processing and field programmable gate arrays, with fiber optic channels for event broadcast between CODAC nodes, and short length paths between the EPN and CODAC hardware, allows an effective and low latency communication path. This hardware will be integrated in the ISTTOK CODAC to allow long AC plasma discharges. Index Terms--Event distribution, real-time, synchronism, trigger distribution.

Low complexity and reconfigurability are two key requirements of channel filters in a software defined radio receiver. A new reconfigurable architecture based on frequency response masking (FRM) technique for the implementation of channel filters is proposed in this paper. Our architecture offers reconfigurability at filter and architecture levels, in addition to the inherent low complexity offered by the FRM technique. The proposed reconfigurable filter has been synthesized on 0.18-[micro]m CMOS technology and implemented and tested on Virtex-II 2v3000ff1152-4 field-programmable gate array. Synthesis results show that the proposed channel filter offers average area and power reductions of 53.6% and 57.6%, respectively ,with average improvement in speed of 47.6% compared to other reconfigurable filters in literature. Index Terms--Channel filters, frequency response masking (FRM), low complexity, reconfigurability, software defined radio (SDR).

With the emergence of portable computing and communication system, power awareness is one of the major objectives of VLSI Design. This is its ability to scale power consumption based on the time-varying nature of inputs. Even though the system is not designed for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that some systems are more power aware than others. Equivalently, the system should be able to re designed to increase their power awareness. This research proposes a pipelined Variable precision gating scheme to improve the power awareness of the system. This research illustrates this technique by applying it to FPGA Implementation of multipliers and digital FIR filters. This proposed technique is to clock gating to registers in both data flow direction and vertical to data flow direction within the individual pipeline stage based on the input data precision. For signed multipliers using 2's complement representation, sign extension, which wastes power and causes longer delay, could be avoided by implementing this technique. Very little additional area is needed for this technique. The designed circuit is simulated, synthesized and implemented in Xilinx Spartan 3e FPGA. The Power is analyzed for the designed circuit and the power saving of 18 % obtained for the proposed FIR Filter with 3 % increase in area compared to the existing pipeline gating design Key words: Variable precision pipelining, FPGA implementation, low power, energy scalable, FIR filter, reduced transition, INTRODUCTION Growing of battery-operated multimedia devices requires energy-efficient circuits, particularly digital multipliers which are building blocks of digital signal processors. Though many efforts have been focused on the improvement of [...]

This paper addresses several aspects of implementing a remote control system for a large number of electronics boards in order to perform remote Field Programmable Gate Array (FPGA) programming, hardware configuration, data register access, and monitoring, as well as interfacing it to an expert system. The paper presents a common strategy for the representation of the boards in the abstraction layer of the control system, and generic communication protocols for the access to the board resources. In addition, an implementation is proposed in which the mapping between the functional parameters and the physical registers of the different boards is represented by descriptors in the board representation such that the translation can be handled automatically by a generic translation manager. Using the Distributed Information Management (DIM) package for the control communication with the boards, and the industry SCADA system PVSS II from ETM, a complete control system has been built for the Timing and Fast Control (TFC) system of the LHCb experiment at CERN. It has been in use during the entire prototyping of the TFC system and the developments of the LHCb sub-detector electronics, and is now installed in the online system of the final experiment. Index Terms--Control communication protocol, control interface, control systems, FPGA, LHCB.

In this paper, we describe design and development of the new global decision logic units for the Belle detector at the KEK B-factory. The new units consist of two identical 9U VME modules which are designed using the programmable logic techniques. Each module has an inexpensive programmable logic device that has high density input and output lines. Performance tests of these new modules and existing system are compared and showed good results. Utilizing the nature of the logic device on the board, we also examine possibility of the implementation of an artificial neural network algorithm to the new trigger board for a more efficient data acquisition. Index Terms--Artificial neural network, FPGA, Level 1 trigger.

An FPGA based digital signal processing (DSP) system for biasing and reading out multiplexed bolometric detectors for mm-wavelength telescopes is presented. This readout system is being deployed for balloon-borne and ground based cosmology experiments with the primary goal of measuring the signature of inflation with the Cosmic Microwave Background Radiation. The system consists of analog superconducting electronics running at 250 mK and 4 K, coupled to digital room temperature backend electronics described here. The digital electronics perform the real time functionality with DSP algorithms implemented in firmware. A soft embedded processor provides all of the slow housekeeping control and communications. Each board in the system synthesizes multi-frequency combs of 8 to 32 carriers in the MHz band to bias the detectors. After the carriers have been modulated with the sky-signal by the detectors, the same boards digitize the comb directly. The carriers are mixed down to base-band and low pass filtered. The signal bandwidth of 0.050 Hz-100 Hz places extreme requirements on stability and requires powerful filtering techniques to recover the sky-signal from the MHz carriers. Index Terms--Digital signal processing, field programmable gate arrays, frequency division multiplexing, millimeter wave astronomy, real time systems, SQUIDs.

Infrasound is a low frequency acoustic phenomenon that typically ranges from 0.01 to 20 Hz. The data collected from infrasound microphones are presented online by the infrasound monitoring system operating in Northern Europe, i.e., the Swedish-Finnish Infrasound Network (SFIN). Processing the continuous flow of data to extract optimal feature information is important for real-time signal classification. Performing wavelet decomposition on the real-time signals is an alternative. The purpose of this paper is to present the design and FPGA implementation of discrete wavelet transforms (DWT) for real-time infrasound data processing; our approach uses only two FIR filters, a high-pass and a low-pass filter. A compact implementation was realized with pipelining techniques and multiple use of generalized building blocks. The design was described in VHDL and the FPGA implementation and simulation were performed on the QUARTUS II platform. Index Terms--Discrete wavelet transform (DWT), FPGA, filtering, infrasound.

The new generation of field programmable gate array (FPGA) technologies enables an embedded processor intellectual property (IP) and an application IP to be integrated into a system-on-a-programmable-chip (SoPC) developing environment. Therefore, this study presents a speed control integrated circuit (IC) for permanent magnet synchronous motor (PMSM) drive under this SoPC environment. First, the mathematic model of PMSM is defined and the vector control used in the current loop of PMSM drive is explained. Then, an adaptive fuzzy controller adopted to cope with the dynamic uncertainty and external load effect in the speed loop of PMSM drive is proposed. After that, an FPGA-based speed control IC is designed to realize the controllers. The proposed speed control IC has two IPs, a Nios II embedded processor IP and an application IP. The Nios II processor is used to develop the adaptive fuzzy controller in software due to the complicated control algorithm and low sampling frequency control (speed control: 2 kHz). The designed application IP is utilized to implement the current vector controller in hardware owing to the requirement for high sampling frequency control (current loop: 16 kHz, pulsewidth modulation circuit: 4-8 MHz) but simple computation. Finally, an experimental system is set up and some experimental results are demonstrated. Index Terms--Field programmable gate arrays (FPGAs), fuzzy control, permanent magnet motors, synchronous motor drives, system-on-a-programmable-chip (SoPC).

In this age, where new technological devices such as PDAs and mobile phones are becoming part of our daily lives, providing efficient implementations of suitable cryptographic algorithms for devices built on embedded systems is becoming increasingly important. This paper presents an efficient design of a high-performance hyperelliptic curve cryptosystem for a field programmable gate array which is well suited for embedded systems having limited resources such as memory, space and processing power. In this paper, we investigate two architectures, one using a projective coordinate representation for hyperelliptic systems and the second using a mixed coordinate representation that eliminates the need for field inversions in the point arithmetic, which has been proven to be expensive in both time and space. In addition, both architectures are based on an explicit formula which allows one to compute the point arithmetic directly in the finite field, thereby eliminating a level of arithmetic. The operation time for the HECC system is also improved by considering simplifications of the hypereiliptic curve which are accomplished through simple transformation of variables. As a result, these implementations offer significantly faster operation time and smaller area consumption then other HECC hardware implementations done to date. Keywords: Reconfigurable hardware; Public key cryptosystems; Algorithms implemented in hardware

We present a compact FPGA implementation of a modular exponentiation accelerator suited for cryptographic applications. The implementation efficiently exploits the properties of modern FPGAs. The accelerator consumes 434 logic elements, four 9-bit DSP elements, and 13604 memory bits in Altera Stratix EPIS40. It performs modular exponentiations with up to 2250-bit integers and scales easily to larger exponentiations. Excluding pre- and post-processing time, 1024-bit and 2048-bit exponentiations are performed in 26.39 ms and 199.11 ms, respectively. Due to its compactness, standard interface, and support for different clock domains, the accelerator can effortlessly be integrated into a larger system in the same FPGA. The accelerator and its performance are demonstrated in practice with a fully functional prototype implementation consisting of software and hardware components. Keywords: Security; Cryptography; Modular exponentiation; Hardware; FPGA; Compact

This paper describes the first differential power and electromagnetic analysis attacks performed on a hardware implementation of an elliptic curve cryptosystem. In the same time we also compared the metrics used in differential power and electromagnetic radiation attacks. We describe the use of the Pearson correlation coefficient, the distance of mean test and the maximum likelihood test. For each metric the number of measurements needed to get a clear idea of the right guess of the key-bit is taken as indication of the strength of the metric. Keywords: FPGA; Power analysis; Electromagnetic analysis; Elliptic curve cryptosystems

This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemented to write assembly programs in this teaching tool. In addition to the micro-operation simulation, the complete configuration can be run on Xilinx Spartan-3 FPGA board. Such implementation offers good code density, easy customization, easily developed software, small area, and high performance at low cost. Key Words: Teaching tool, Computer organization and architecture, Processor design, Microprogramming, Assembler design, FPGA implementation., INTRODUCTION Computer organization and architecture is a common course that is offered at universities throughout the world (1). Traditionally, teaching such a course to computer engineering and computer science students [...]

This paper presents a course on digital signal processing with field-programmable gate arrays (FPGA) devices. The course integrates two separate disciplines, digital signal processing (DSP) and very large scale integration (VLSI) design, and focuses on the development of a sophisticated DSP design from simulation to fixed-point implementation. The structure and methodology used in the proposed course are oriented to the design and implementation of an fast Fourier transform (FFT) spectrum analyzer. This application covers most topics included in a DSP course and gives better results that those obtained with typical courses performing independent multiple simple experiments. The project is divided into modules that show specific learning necessities and determine the course contents and organization. Each laboratory part is dedicated to design and implements the block of the analyzer related to the theoretical content presented in the class. At the end of the course the students have designed all the pieces in the DSP project and have completed and verified the system. The used methodology enables students and engineers to understand and develop complex fixed-point applications, looking for the best signal processing algorithms on hardware implementations, and also results in more motivated and active students. Index Terms--Arithmetic, coordinate rotation digital computer (CORDIC), decimate filters, digital circuits, digital signal processing (DSP), direct digital synthesis (DDS), fast Fourier transform (FFT), field-programmable gate arrays (FPGA) implementation, logic design, mixer, real-time applications, signal processing, spectrum analyzer, windowing.