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Your search keyword '"Helaoui, Mohamed"' showing total 333 results
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333 results on '"Helaoui, Mohamed"'

93. Broadband continuous mode power amplifier with on-board harmonic injection.

Author

Latha, Yericharla Mary Asha, Rawat, Karun, Helaoui, Mohamed, and Ghannouchi, Fadhel M.

Subjects
POWER amplifiers, GALLIUM nitride, SURFACE plates, LONG-Term Evolution (Telecommunications), RADIO frequency, MODULATION-doped field-effect transistors, THULIUM
Abstract

This study presents the design of a broadband continuous mode power amplifier (PA) with an active harmonic injection (HI). Since the injected harmonic signal is generated on-board using a frequency doubler, this design has a single radio frequency input. The generated second harmonic is injected at the drain terminal of a gallium nitride high-electron-mobility transistor used in designing continuous class B/J PA. A design space in terms of amplitude and phase of the injected harmonic signal is analysed to obtain the loads that operate the PA in the continuous class B/J mode at the current generator reference plane. The proposed design strategy is verified by designing a prototype with a frequency doubler and a PA using 10 and 15 W gallium nitride high-electron-mobility transistors, respectively. The measured drain efficiency of 60.04-70.96% and output power of 40.17-42.6 dBm is obtained from 1 to 1.9 GHz. This corresponds to a broadband operation of 900 MHz with 62% fractional bandwidth. The designed HI-PA is also tested with a 20 MHz long-term evolution signal whose corresponding adjacent channel power ratio is better than -47.76 dBc in the overall band after applying digital predistortion. [ABSTRACT FROM AUTHOR]

Published
2019
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94. Delay‐compensation block for first‐order low‐pass delta‐sigma modulators.

Author

Ben Arfi, Anis, Helaoui, Mohamed, and Ghannouchi, Fadhel M.

Subjects
*DELTA-sigma modulation, *FIELD programmable gate arrays, *LOGIC circuits, *TRANSFER functions, *SIGNAL-to-noise ratio, *ELECTRIC distortion, *ADJACENT channel interference
Abstract

Implementing the Delta Sigma Modulator (DSM) processing blocks on hardware is challenging due to the additional tap delays required by the digital processing blocks to process and output the result. The tap‐delays, known as latency, are necessary for the Field Programmable Gate Array (FPGA) operation to allow the logic gates to process the data at a given clock rate. These latencies alter the transfer function of the first‐order DSM as they present additional tap‐delays to the inherent delays within the DSM loop. A compensation block for the first‐order DSM is proposed to cancel‐out the effect of these latencies. By studying the transfer function, a combination of delays able to reconstruct the correct transfer function is determined. The solution was implemented on FPGA and tested using a 2.5 MHz signal. The post‐compensated DSM achieved a Signal‐to‐Noise‐and‐Distortion Ratio (SNDR) = 42 dB and an Adjacent Channel Leakage Ratio (ACLR) = 39 dB. [ABSTRACT FROM AUTHOR]

Published
2019
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95. Analysis, Calibration, and Performance Evaluation of a Generalized $N$ -Phase Quadrature Phase Shift Frequency Selective Receiver.

Author

Hasan, Abul and Helaoui, Mohamed

Subjects
*PHASE shifters, *FREQUENCY selective surfaces, *SOFTWARE radio, *COMPARATIVE studies, *DEMODULATION, *ENERGY consumption
Abstract

In this paper, a new low-power and blocker-tolerant receiver architecture, the generalized N-phase quadrature phase shift frequency selective (QPS-FS), is proposed and analyzed that is suitable for radio frequency (RF) energy harvesting networks. A complete comparative analysis of the N-phase QPS-FS receiver with conventional N-path passive mixer (P-M) receiver is also provided. The QPS-FS receiver utilizes the impedance translation concept to improve the receiver selectivity but eliminates the need of an active multiphase clock generation circuit used in the conventional N-path P-M receivers. It uses a single clock signal source at the desired signal carrier frequency and a phase shift network in the RF path of the receiver for frequency downconversion and quadrature (I/Q) demodulation. The QPS-FS receiver requires a slower clock signal source, the frequency of which is equal to the desired band RF signal carrier frequency ($f_{c})$ as opposed to at least N/2 times $f_{c}$ for the conventional N-path P-M receivers. Consequently, the lower frequency clock source requirement extends the frequency coverage of the receiver by a factor of at least N/2 for a given clock source with a fixed maximum frequency. Reduction of the operating frequency and elimination of the active multiphase clock generation circuit would also eventually reduce the overall power consumption for the whole receiver system as confirmed through measurements. A wideband receiver calibration approach provides less than 2% of error vector magnitudes between the transmitted and received constellation points for various modulated signals having bandwidths up to 4 MHz. [ABSTRACT FROM AUTHOR]

Published
2019
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