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The time-dependent dielectric breakdown in thin gate oxides is studied and a new methodology is proposed that is applicable to a wide range of gate stacks for extracting soft breakdown (SBD) and post-SBD wear-out (WO) parameters from measuring the time to hard breakdown ([t.sub.HBD) only. A new complete reliability prediction model is proposed that has included SBD and WO.

The article presents various different techniques that can be employed for the evaluation of the threshold voltage shift induced by the negative bias temperature instability (NBTI). The effects of sensing and recovery are shown to be the major factors that need to be considered during the process of voltage evaluation.

Several stress and recovery experiments are conducted to explain the mechanisms that are shown to initiate the negative bias temperature instability (NBTI) in the pMOS transistors. Generation of defects near the silicon/silicon dioxide interface and hole trapping in the oxide are shown to be the two main mechanisms imvolved in the generation of NBTI.

Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high- ${k}$ /metal gate (HKMG) stacks at a reduced thermal budget (<525 °C). The omission of the customary high-temperature gate-stack annealing results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of “defect decoupling” layers–LaSiOx for nMOS and Al2O3 for pMOS–at the interface between SiO2 and HfO2 as a promising approach to engineer the high- ${k}$ band lineup and minimize charge trapping for improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate this approach in planar transistors, which allows assessing the impact of defect decoupling on carrier mobility. First, a comparative study on the impact of LaSiOx and Al2O3 insertion is performed, highlighting the different strategies for improving positive BTI (PBTI) and negative BTI (NBTI) reliability. Second, a comprehensive investigation on the effects of LaSiOx and Al2O3 insertion is conducted with a focus on BTI reliability and channel carrier mobility: a lack of penalty (Al2O3) or even improved carrier mobility (LaSiOx) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate-stack integration for CMOS flow. A severe PBTI reliability penalty is observed if an Al2O3 layer (for hole trap decoupling) is deposited in the nMOS gate-stack, even if on top of the beneficial LaSiOx (for electron trap decoupling). In contrast, the pMOS gate-stack is found to be more tolerant to the presence of a residual LaSiOx layer on top of the beneficial Al2O3 layer, suggesting a viable strategy for the simplified dual gate-stack integration. Finally, the reliability improvement is validated also on a FinFET test vehicle. [ABSTRACT FROM AUTHOR]

The impact of strain on negative bias temperature instability (NBTI) is assessed by studying devices with polycrystalline-Si/SiON as well as deposited metal gate/high-[kappa] and FUSI/high-[kappa] gate stacks. The studies have shown that there is no degradation of intrinsic NBTI behavior due to process-induced strain.

The design and verification of a theory of the current-ratio (CR) technique in uniform semiconductors, which is widely used to locate gate oxide breakdown (BD) spots in one dimension, is reported. The newly developed technique could be used to interpret BD-spot distributions in 2-D to better predict gate oxide reliability.

We present new original experimental results on the effects produced by single heavy-ion strikes on minimum-size MOSFETs manufactured in a 0.1-[micro]m CMOS technology. We show that, whereas large-width samples do not suffer from any particular degradation when struck by a single ion, minimum size devices, which are the real building block of modern digital circuits, display small but significant changes in the electrical characteristics. In particular, we identify and classify the different types of degradation occurring after irradiation with high-LET particles and attribute them to ion strikes occurring in different parts of the MOSFET: gate oxide, LDD spacers, and STI. Even though the observed changes do not compromise the device functionality, they clearly indicate that, as the feature size is scaled into the decananometer range, single heavy-ion strikes will have a growing effect on digital circuits. Index Terms--CMOS, heavy ions.

The influence of field-effect transistor (FET) gate oxide breakdown on the performance of a ring oscillator circuit is studied using statistical tools, emission microscopy and circuit analysis. It is further demonstrated that many hard breakdowns can occur in this circuit without affecting its overall function.

A consistent picture for field-effect transistors (nFET) with hard gate oxide breakdown is proposed and supported by MEDICI and SPICE simulations. The circuit proposed could be used for determining how strongly gate oxide breakdown affects both digital and analog circuit operation.

The origin of the Fowler-Nordheim-induced substrate hole current was re-examined.

The effects of increased temperature on degradation and lifetime prediction of thin silicon-dioxide films are discussed.