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Modern signal processing and multimedia embedded systems increasingly have heterogeneous system architectures. In these systems, programmable processors provide flexibility to support multiple applications, while dedicated hardware blocks provide high performance for time-critical application tasks. The heterogeneity of these embedded systems and the varying demands of their growing number of target applications greatly complicate the system design.As part of the Artemis project, we are developing a modeling and simulation environment which aims at efficient design space exploration of heterogeneous embedded systems architectures. In this paper, we present an overview of the modeling and simulation methodology used in Artemis. Moreover, using a case study in which we have applied an initial version of our prototype modeling and simulation environment to an M-JPEG encoding application, we illustrate the ease with which alternative candidate architectures can be modeled and evaluated.

Embedded computing systems are becoming very common and embedded computing is starting to find its way into the curriculum. In this talk, I will discuss my views of the relationships between computer architecture education and the teaching of embedded system design. Students of embedded computing need to understand computer architecture in order to understand the characteristics of these critical components of embedded systems. The viewpoint of a user of computer architectures rather than a designer of computer architectures doesn't radically change the fundamentals that one needs to know, but it does introduce new shadings of meaning into those fundamentals.

Embedded systems are informally defined as a collection of programmable parts surrounded by ASICs and other standard components, that interact continuously with an environment through sensors and actuators [5]. In today’s world there is a wide proliferation of such electronic devices in everything from tea kettles to life-critical systems. Up till very recently, embedded systems have been designed in an ad hoc fashion based on manual interference and guidance. With increasing complexity, formal methodologies that incorporate HW/SW trade-off analysis and evaluation, and validation at the highest possible abstraction level have become essential. Obviously, an overhead is incurred in this top-down process: quality of the final output is typically tradedoff with increased productivity, but as we will show, this overhead can be again managed and put within bounds if the methodology includes constraint-driven optimizations; the subject of the upcoming Chapters.

The design space exploration (DSE) subsystem of a design automation tool is responsible for early identification of interesting zones of the design space. Evaluation of the exploration strategy used in a tool is extremely difficult because there is not enough information about either the design space or the actual cost function. This paper describes a software environment for quantitative evaluation of isolated exploration algorithms based on a completely simulated framework. A simple model of the design space allows easy representation of interesting properties of exploration algorithms.

Computers and computer-based appliances are becoming increasingly portable, principally as a consequence of advances in the functionality and power-efficiency of digital VLSI electronics. Other contributory factors, such as improvements in batteries, are modest in comparison to the rate of development of digital electronics technology.

Many embedded systems have substantially different design constraints than desktop computing applications. No single characterization applies to the diverse spectrum of embedded systems. However, some combination of cost pressure, longlife-cycle, real-time requirements, reliability requirements, and design culture dysfunction can make it difficult to be successful applying traditional computer design methodologies and tools to embedded applications. Embedded systems in many cases must be optimized for life-cycle and business-driven factors rather than for maximum computing throughput. There is currently little tool support for expanding embedded computer design to the scope of holistic embedded system design. However,knowing the strengths and weaknesses of current approaches can set expectations appropriately, identify risk areas to tool adopters, and suggest ways in which tool builders can meet industrial needs.

The Wisconsin Multicube , is a large-scale, shared-memory multiprocessor architecture that employs a snooping cache protocol over a grid of buses. Each processor has a conventional (SRAM) cache optimized to minimize memory latency and a large (DRAM) snooping cache optimized to reduce bus traffic and to maintain consistency. The large snooping cache should guarantee that nearly all the traffic on the buses will be generated by I/O and accesses to shared data. The programmer's view of the system is like a multi -- a set of processors having access to a common shared memory with no notion of geographical locality. Thus writing software, including the operating system, should be a straightforward extension of those techniques being developed for multis. The interconnection topology allows for a cache-coherent protocol for which most bus requests can be satisfied with no more than twice the number of bus operations required of a single-bus multi. The total symmetry guarantees that there are no topology-induced bottlenecks. The total bus bandwidth grows in proportion to the product of the number of processors and the average path length. The proposed architecture is an example of a new class of interconnection topologies -- the Multicube -- which consists of N =n k processors, where each processor is connected to k buses and each bus is connected to n processors. The hypercube is a special case where n =2. The Wisconsin Multicube is a two-dimensional Multicube ( k =2), where n scales to about 32, resulting in a proposed system of over 1,000 processors.

This paper proposes a set of efficient primitives for process synchronization in multiprocessors. The only assumptions made in developing the set of primitives are that hardware combining is not implemented in the inter-connect, and (in one case) that the interconnect supports broadcast. The primitives make use of synchronization bits (syncbits) to provide a simple mechanism for mutual exclusion. The proposed implementation of the primitives includes efficient ( i.e. local) busy-waiting for syncbits. In addition, a hardware-supported mechanism for maintaining a first-come first-serve queue of requests for a syncbit is proposed. This queueing mechanism allows for a very efficient implementation of, as well as fair access to, binary semaphores. We also propose to implement Fetch and Add with combining in software rather than hardware. This allows an architecture to scale to a large number of processors while avoiding the cost of hardware combining. Scenarios for common synchronization events such as work queues and barriers are presented to demonstrate the generality and ease of use of the proposed primitives. The efficient implementation of the primitives is simpler if the multiprocessor has a hardware cache-consistency protocol. To illustrate this point, we outline how the primitives would be implemented in the Multicube multiprocessor [GoWo88].

Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and redesign a system to reach near an optimal value. The resulting effect is a long design time. In this paper, we introduce an effective scheme that accelerates design. A system-level pruning of design exploration space speeds up the optimization process. Through a single-pass simulation for a reference customization and a model for estimating and evaluating the system's performance, pruning of design space is achieved. Experimental results show that a substantial reduction in design time is possible.