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51. Data from The Immunopeptidome from a Genomic Perspective: Establishing the Noncanonical Landscape of MHC Class I–Associated Peptides

Author

Bedran, Georges, primary, Gasser, Hans-Christof, primary, Weke, Kenneth, primary, Wang, Tongjie, primary, Bedran, Dominika, primary, Laird, Alexander, primary, Battail, Christophe, primary, Zanzotto, Fabio Massimo, primary, Pesquita, Catia, primary, Axelson, Håkan, primary, Rajan, Ajitha, primary, Harrison, David J., primary, Palkowski, Aleksander, primary, Pawlik, Maciej, primary, Parys, Maciej, primary, O'Neill, J. Robert, primary, Brennan, Paul M., primary, Symeonides, Stefan N., primary, Goodlett, David R., primary, Litchfield, Kevin, primary, Fahraeus, Robin, primary, Hupp, Ted R., primary, Kote, Sachin, primary, and Alfaro, Javier A., primary

Published
2023
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53. The immunopeptidome from a genomic perspective: Establishing the non-canonical landscape of MHC class I–associated peptides

Author

Bedran, Georges, primary, Gasser, Hans-Christof, additional, Weke, Kenneth, additional, Wang, Tongjie, additional, Bedran, Dominika, additional, Laird, Alexander, additional, Battail, Christophe, additional, Zanzotto, Fabio Massimo, additional, Pesquita, Catia, additional, Axelson, Håkan, additional, Rajan, Ajitha, additional, Harrison, David J., additional, Palkowski, Aleksander, additional, Pawlik, Maciej, additional, Parys, Maciej, additional, O'Neill, J Robert., additional, Brennan, Paul M., additional, Symeonides, Stefan N., additional, Goodlett, David R., additional, Litchfield, Kevin, additional, Fahraeus, Robin, additional, Hupp, Ted R., additional, Kote, Sachin, additional, and Alfaro, Javier A., additional

Published
2023
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54. Structural Test Coverage Criteria for Integration Testing of LUSTRE/SCADE Programs

Author

Papailiopoulou, Virginia, Rajan, Ajitha, Parissis, Ioannis, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Salaün, Gwen, editor, and Schätz, Bernhard, editor

Published
2011
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55. Catch Me If You Can: Blackbox Adversarial Attacks on Automatic Speech Recognition using Frequency Masking

Author

Wu, Xiaoliang and Rajan, Ajitha

Subjects
FOS: Computer and information sciences, Sound (cs.SD), Computer Science - Computation and Language, Automatic Speech Recognition, Adversarial Attack, Computer Science - Sound, Software Engineering (cs.SE), Computer Science - Software Engineering, Audio and Speech Processing (eess.AS), Frequency Masking, FOS: Electrical engineering, electronic engineering, information engineering, Computation and Language (cs.CL), Blackbox, Electrical Engineering and Systems Science - Audio and Speech Processing
Abstract

Automatic speech recognition (ASR) models are prevalent, particularly in applications for voice navigation and voice control of domestic appliances. The computational core of ASRs are deep neural networks (DNNs) that have been shown to be susceptible to adversarial perturbations; easily misused by attackers to generate malicious outputs. To help test the security and robustnesss of ASRS, we propose techniques that generate blackbox (agnostic to the DNN), untargeted adversarial attacks that are portable across ASRs. This is in contrast to existing work that focuses on whitebox targeted attacks that are time consuming and lack portability. Our techniques generate adversarial attacks that have no human audible difference by manipulating the audio signal using a psychoacoustic model that maintains the audio perturbations below the thresholds of human perception. We evaluate portability and effectiveness of our techniques using three popular ASRs and two input audio datasets using the metrics - Word Error Rate (WER) of output transcription, Similarity to original audio, attack Success Rate on different ASRs and Detection score by a defense system. We found our adversarial attacks were portable across ASRs, not easily detected by a state-of-the-art defense system, and had significant difference in output transcriptions while sounding similar to original audio., 11 pages, 7 figures and 3 tables

Published
2022
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56. Requirements Coverage as an Adequacy Measure for Conformance Testing

Author

Rajan, Ajitha, Whalen, Michael, Staats, Matt, Heimdahl, Mats P. E., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Liu, Shaoying, editor, Maibaum, Tom, editor, and Araki, Keijiro, editor

Published
2008
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57. BenchPress

Author

Tsimpourlas, Foivos, Petoumenos, Pavlos, Xu, Min, Cummins, Chris, Hazelwood, Kim, Rajan, Ajitha, and Leather, Hugh

Subjects
FOS: Computer and information sciences, Artificial Intelligence (cs.AI), Computer Science - Artificial Intelligence
Abstract

We develop BenchPress, the first ML benchmark generator for compilers that is steerable within feature space representations of source code. BenchPress synthesizes compiling functions by adding new code in any part of an empty or existing sequence by jointly observing its left and right context, achieving excellent compilation rate. BenchPress steers benchmark generation towards desired target features that has been impossible for state of the art synthesizers (or indeed humans) to reach. It performs better in targeting the features of Rodinia benchmarks in 3 different feature spaces compared with (a) CLgen - a state of the art ML synthesizer, (b) CLSmith fuzzer, (c) SRCIROR mutator or even (d) human-written code from GitHub. BenchPress is the first generator to search the feature space with active learning in order to generate benchmarks that will improve a downstream task. We show how using BenchPress, Grewe's et al. CPU vs GPU heuristic model can obtain a higher speedup when trained on BenchPress's benchmarks compared to other techniques. BenchPress is a powerful code generator: Its generated samples compile at a rate of 86%, compared to CLgen's 2.33%. Starting from an empty fixed input, BenchPress produces 10x more unique, compiling OpenCL benchmarks than CLgen, which are significantly larger and more feature diverse., Comment: To appear in PACT 2022

Published
2022
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58. A comprehensive library of canonical and non-canonical MHC class I antigens for cancer vaccine development.

Author

Bedran, Georges, primary, Wang, Tongjie, additional, Pankanin, Dominika, additional, Weke, Kenneth, additional, Laird, Alexander, additional, Battail, Christophe, additional, Zanzotto, Fabio Massimo, additional, Pesquita, Catia, additional, Axelson, Hakan, additional, Rajan, Ajitha, additional, Harrison, David J., additional, Palkowski, Aleksander, additional, Pawlik, Maciej, additional, Parys, Maciej, additional, O'Neill, Robert, additional, Brennan, Paul M., additional, Symeonides, Stefan, additional, Goodlett, David R., additional, Litchfield, Kevin, additional, Fahraeus, Robin, additional, Hupp, Ted R., additional, Kote, Sachin, additional, and Alfaro, Javier A., additional

Published
2022
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59. The Immunopeptidome From a Genomic Perspective: Establishing Immune-Relevant Regions for Cancer Vaccine Design

Author

Bedran, Georges, primary, Wang, Tongjie, additional, Pankanin, Dominika, additional, Weke, Kenneth, additional, Laird, Alexander, additional, Battail, Christophe, additional, Zanzotto, Fabio Massimo, additional, Pesquita, Catia, additional, Axelson, Håkan, additional, Rajan, Ajitha, additional, Harrison, David J., additional, Palkowski, Aleksander, additional, Pawlik, Maciej, additional, Parys, Maciej, additional, O’Neill, Robert, additional, Brennan, Paul, additional, Symeonides, Stefan, additional, Goodlett, David R., additional, Litchfield, Kevin, additional, Fahraeus, Robin, additional, Hupp, Ted R., additional, Kote, Sachin, additional, and Alfaro, Javier A., additional

Published
2022
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65. Introduction

Author

Armengaud, Eric, primary, Bonnet, Stephane, additional, Duffau, Laurent, additional, Fenu, Gianfranco, additional, Griessnig, Gerhard, additional, Hein, Christian, additional, Keis, Andreas, additional, Kundner, Ingrid, additional, Lau, Kung-Kiu, additional, Malot, Marc, additional, Örtel, Markus, additional, Paganelli, Fabien, additional, Pantel, Marc, additional, Persson, Magnus, additional, Priggouris, Nikolaos, additional, Rajan, Ajitha, additional, Ritter, Tom, additional, Rossignol, Alain, additional, Silva, Adeline, additional, Törngren, Martin, additional, Vasaiely, Parham, additional, and Wahl, Thomas, additional

Published
2012
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67. Embedding and classifying test execution traces using neural networks.

Author

Tsimpourlas, Foivos, Rooijackers, Gwenyth, Rajan, Ajitha, and Allamanis, Miltiadis

Subjects
COMPUTER software testing, SUPERVISED learning, COMPUTER network protocols, EXECUTIONS & executioners, DEEP learning, PROBLEM solving
Abstract

Classifying test executions automatically as pass or fail remains a key challenge in software testing and is referred to as the test oracle problem. It is being attempted to solve this problem with supervised learning over test execution traces. A programme is instrumented to gather execution traces as sequences of method invocations. A small fraction of the programme's execution traces is labelled with pass or fail verdicts. Execution traces are then embedded as fixed length vectors and a neural network (NN) component that uses the line‐by‐line information to classify traces as pass or fail is designed. The classification accuracy of this approach is evaluated using subject programs from different application domains—1. Module from Ethereum Blockchain, 2. Module from PyTorch deep learning framework, 3. Microsoft SEAL encryption library components, 4. Sed stream editor, 5. Nine network protocols from Linux packet identifier, L7‐Filter and 6. Utilities library, commons‐lang for Java. For all subject programs, it was found that test execution classification had high precision, recall and specificity, averaging to 93%, 94% and 96%, respectively, while only training with an average 14% of the total traces. Experiments show that the proposed NN‐based approach is promising in classifying test executions from different application domains. [ABSTRACT FROM AUTHOR]

Published
2022
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69. M 3

Author

Collie, Bruce, primary, Ginsbach, Philip, additional, Woodruff, Jackson, additional, Rajan, Ajitha, additional, and O'Boyle, Michael F. P., additional

Published
2020
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70. Coverage Metrics for Requirements-Based Testing: Evaluation of Effectiveness

Author

Staats, Matt, Whalen, Michael W, Heindahl, Mats P. E, and Rajan, Ajitha

Subjects
Mathematical And Computer Sciences (General)
Abstract

In black-box testing, the tester creates a set of tests to exercise a system under test without regard to the internal structure of the system. Generally, no objective metric is used to measure the adequacy of black-box tests. In recent work, we have proposed three requirements coverage metrics, allowing testers to objectively measure the adequacy of a black-box test suite with respect to a set of requirements formalized as Linear Temporal Logic (LTL) properties. In this report, we evaluate the effectiveness of these coverage metrics with respect to fault finding. Specifically, we conduct an empirical study to investigate two questions: (1) do test suites satisfying a requirements coverage metric provide better fault finding than randomly generated test suites of approximately the same size?, and (2) do test suites satisfying a more rigorous requirements coverage metric provide better fault finding than test suites satisfying a less rigorous requirements coverage metric? Our results indicate (1) only one coverage metric proposed -- Unique First Cause (UFC) coverage -- is sufficiently rigorous to ensure test suites satisfying the metric outperform randomly generated test suites of similar size and (2) that test suites satisfying more rigorous coverage metrics provide better fault finding than test suites satisfying less rigorous coverage metrics.

Published
2010

71. Assessing Requirements Quality through Requirements Coverage

Author

Rajan, Ajitha, Heimdahl, Mats, and Woodham, Kurt

Subjects
Mathematical And Computer Sciences (General)
Abstract

In model-based development, the development effort is centered around a formal description of the proposed software system the model. This model is derived from some high-level requirements describing the expected behavior of the software. For validation and verification purposes, this model can then be subjected to various types of analysis, for example, completeness and consistency analysis [6], model checking [3], theorem proving [1], and test-case generation [4, 7]. This development paradigm is making rapid inroads in certain industries, e.g., automotive, avionics, space applications, and medical technology. This shift towards model-based development naturally leads to changes in the verification and validation (V&V) process. The model validation problem determining that the model accurately captures the customer's high-level requirements has received little attention and the sufficiency of the validation activities has been largely determined through ad-hoc methods. Since the model serves as the central artifact, its correctness with respect to the users needs is absolutely crucial. In our investigation, we attempt to answer the following two questions with respect to validation (1) Are the requirements sufficiently defined for the system? and (2) How well does the model implement the behaviors specified by the requirements? The second question can be addressed using formal verification. Nevertheless, the size and complexity of many industrial systems make formal verification infeasible even if we have a formal model and formalized requirements. Thus, presently, there is no objective way of answering these two questions. To this end, we propose an approach based on testing that, when given a set of formal requirements, explores the relationship between requirements-based structural test-adequacy coverage and model-based structural test-adequacy coverage. The proposed technique uses requirements coverage metrics defined in [9] on formal high-level software requirements and existing model coverage metrics such as the Modified Condition and Decision Coverage (MC/DC) used when testing highly critical software in the avionics industry [8]. Our work is related to Chockler et al. [2], but we base our work on traditional testing techniques as opposed to verification techniques.

Published
2008

72. GPU acceleration of finite state machine input execution: Improving scale and performance.

Author

Yaneva, Vanya, Rajan, Ajitha, and Dubach, Christophe

Subjects
FINITE state machines, GRAPHICS processing units
Abstract

Model-based development is a popular development approach in which software is implemented and verified based on a model of the required system. Finite state machines (FSMs) are widely used as models for systems in several domains. Validating that a model accurately represents the required behaviour involves the generation and execution of a large number of input sequences, which is often an expensive and time-consuming process. In this paper, we speed up the execution of input sequences for FSM validation, by leveraging the high degree of parallelism of modern graphics processing units (GPUs) for the automatic execution of FSM input sequences in parallel on the GPU threads. We expand our existing work by providing techniques that improve the performance and scalability of this approach. We conduct extensive empirical evaluation using 15 large FSMs from the networking domain and measure GPU speed-up over a 16-core CPU, taking into account total GPU time, which includes both data transfer and kernel execution time. We found that GPUs execute FSM input sequences up to 9.28x faster than a 16-core CPU, with an average speed-up of 4.53x across all subjects. Our optimizations achieve an average improvement over existing work of 58.95% for speed-up and scalability to large FSMs with over 2K states and 500K transitions. We also found that techniques aimed at reducing the number of required input sequences for large FSMs with high density were ineffective when applied to all-transition pair coverage, thus emphasizing the need for approaches like ours that speed up input execution. [ABSTRACT FROM AUTHOR]

Published
2022
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73. Testing Strategies for Model-Based Development

Author

Heimdahl, Mats P. E, Whalen, Mike, Rajan, Ajitha, and Miller, Steven P

Subjects
Computer Programming And Software
Abstract

This report presents an approach for testing artifacts generated in a model-based development process. This approach divides the traditional testing process into two parts: requirements-based testing (validation testing) which determines whether the model implements the high-level requirements and model-based testing (conformance testing) which determines whether the code generated from a model is behaviorally equivalent to the model. The goals of the two processes differ significantly and this report explores suitable testing metrics and automation strategies for each. To support requirements-based testing, we define novel objective requirements coverage metrics similar to existing specification and code coverage metrics. For model-based testing, we briefly describe automation strategies and examine the fault-finding capability of different structural coverage metrics using tests automatically generated from the model.

Published
2006

75. Speeding up Test Execution with Increased Cache Locality

Author

Stratis, Panagiotis and Rajan, Ajitha

Abstract

As the scale and complexity of software increases, the number of tests needed for effective validation becomes extremely large. Executing these large test suites is expensive, both in terms of time and energy. Cache misses are a significant contributing factor to execution time of software. We propose an approach that helps order test executions in a test suite in such a way that instruction cache misses are reduced. We also ensure that the approach scales to large test suite sizes. We conduct an empirical evaluation with 20 subject programs and test suites from the SIR repository, EEMBC suite and LLVM Symbolizer, comparing execution times and cache misses with test orderings maximising instruction locality versus a traditional ordering maximising coverage and random permutations. We also assess overhead of algorithms in generating the orderings that optimise cache locality. Nature of programs and tests impact the performance gained with our approach. Performance gains were considerable for programs and test suites where the average number of different instructions executed between tests was high. We achieved an average execution speedup of 6.83% and a maximum execution speedup of 17% over subject programs with differing control flow between test executions.

Published
2018
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84. Optimising Energy Consumption of Design Patterns

Author

Noureddine, Adel, Rajan, Ajitha, Laboratory for the Foundations of Computer Science [Edinburgh] (LFCS), University of Edinburgh, and Noureddine, Adel

Subjects
[INFO.INFO-SE] Computer Science [cs]/Software Engineering [cs.SE], 0202 electrical engineering, electronic engineering, information engineering, 020206 networking & telecommunications, 020207 software engineering, 02 engineering and technology, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE]
Abstract

International audience; Software design patterns are widely used in software engineering to enhance productivity and maintainability.However, recent empirical studies revealed the high energy overhead in these patterns. Our vision is to automatically detect and transform design patterns during compilation for better energy efficiency without impacting existing coding practices.In this paper, we propose compiler transformations for two design patterns, Observer and Decorator, and perform an initial evaluation of their energy efficiency.

Published
2015

90. Service specification and validation in the context of the home

Author

Du Bousquet, Lydie, Rajan, Ajitha, Oriat, Catherine, Richier, Jean-Luc, Vega Baez, German Eduardo, Validation de Systèmes, Composants et Objets logiciels (VASCO), Laboratoire d'Informatique de Grenoble (LIG), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)

Subjects
[INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], ComputingMilieux_MISCELLANEOUS
Abstract

International audience; no abstract

Published
2009

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