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SFQ logic (such as RSFQ and ERSFQ) is one of the contenders for future low power, high-speed electronics. SFQ logic can also function as the interface to superconducting quantum qubits. It is therefore essential to have robust SFQ cell libraries that can be used in these designs. One significant challenge in SFQ circuit design is to find the best optimized design, starting from a nominal working circuit, that circuit designers should layout. Various optimization algorithms and tools are available (such as largest inscribed hypersphere, critical margin optimization, particle swarm, and various other algorithms), but all of them have different shortcomings that make them difficult to use with real-world cells. We present a new optimization algorithm, the distance-to-failure-maximization method, that uses some of the insight of the previous algorithms as well as a few new characteristics that make the optimization algorithm practical to use in real-world cases. We also provide an open-source implementation that was used to optimize real-world RSFQ cells for the ColdFlux project. We compare the optimization algorithm with other approaches and show the improvements above the current state of the art.

An automated layout design flow for rapid single-flux-quantum circuits is proposed in this article. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering effective use of JTLs and PTLs. Logic cells are grouped into clusters, and JTLs are used inside clusters. PTLs are used among clusters. The placement process is composed of three steps: first, cell clustering, second, cell placement and JTL routing in each cluster, and third, cluster placement. After the placement process, routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed by the proposed design flow are lower than those of the circuits designed manually.

In recent years, rapid single flux quantum (RSFQ) circuits, which are promising for the development of high-speed digital electronics, have attracted widespread interest. Niobium nitride (NbN) films have also attracted significant attention for high-frequency applications in superconducting electronics because of their superior material parameters, including their high critical temperature T c and large gap voltage V g. To enable the development of all-NbN SFQ circuits, we have developed a fabrication process based on NbN junctions and inductors made of NbN strip lines. It is important to evaluate the inductance because it can affect the performance of an RSFQ circuit and is essential for the RSFQ design. We measured the inductance properties of both epitaxial and polycrystalline NbN strip lines using a superconducting quantum interference device modulation technique at 4.2 K and obtained the width dependence on the inductance of the NbN films. The penetration depth was then calculated from these measurements. The NbN inductance values were calculated numerically with respect to the penetration depth and were then compared with the measured values from the experiments. It was demonstrated that the differences between these values were within 5%. The results reported here will be useful for the design and fabrication of all-NbN RSFQ circuits.

With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz.

Place and route tools for synthesized superconductor logic circuits, either for dc-biased rapid single flux quantum (RSFQ) or ac-biased adiabatic quantum flux parametron (AQFP), are required to automate the design of complex logic circuits. For hand-crafted circuit layout, logic cells, clock, and bias distribution, and signal interconnect can be optimized for tight fit and the adherence to design rules. For complex systems with thousands of logic gates, a hand-crafted approach is not efficient and automated place and route tools are a necessity. Such tools require logic cell layout for placement with a minimum set of rules, followed by an interconnect design that allows maximum routability and strict adherence to layer fill requirements. In this article, we present the design and characterization of a routing architecture that allows rule-based automated place and route for both RSFQ and AQFP logic families. We show that a layout tile size of 10 × 10 μm can be designed to accommodate all design rules for layout fill densities, passive transmission line routing, bias current distribution, and the vias needed to stitch multiple ground planes and provide shielded signal and bias tracks. We also characterize the performance of the layout architecture in terms of transmission line parameters and bias current coupling with powerful simulation tools developed for the SuperTools project. The result is a track layout that doubles as chip fill, is now used for integrated circuit layout under SuperTools and is also applicable to any similar fabrication process with at least eight superconductor metal layers.

Among the major issues in modern large-scale rapid single-flux quantum (RSFQ) circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS-based design algorithms, and extremely deep pipelines, which reduce the effective clock frequency. In this article, asynchronous dynamic single-flux quantum majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large-scale RSFQ circuits, thereby alleviating certain timing issues and reducing the required bias currents. Furthermore, asynchronous logic allows existing design algorithms to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in very large scale integration RSFQ circuits.

Rapid single flux quantum (RSFQ) logic, based on Josephson junctions (JJs), is seeing a resurgence as a way for providing high performance in the era beyond the end of physical scaling of complementary metal-oxide-semiconductor (CMOS). Due to its use of fabrication processes with large feature sizes, the defect density for RSFQ is lower than its CMOS counterpart. Hence, process variations and other RSFQ-specific nonidealities are major causes of chip failures. Because of the nature of its quantized pulse-based operation, even highly distorted pulses are interpreted logically correctly by cells, but the timings are affected. Therefore, timing verification and delay testing increase in importance in RSFQ. Our goal is to ensure that designs and fabricated chips provide desired performance. To achieve this goal, we propose new methods and tools for timing verification and delay testing of fully path balanced RSFQ logic circuits that use concurrent-flow clocking scheme. We address several radically new phenomena in the RSFQ technology, especially the existence of single-pattern delay tests and the need to propagate delayed values via multiple pipeline stages. We then characterize cells under process variations and identify delay excitation conditions, sensitization conditions, and conditions for propagation of the logic errors caused by timing violations due to process variations. We then propose a completely new paradigm for automatic test pattern generation (ATPG) which utilizes these new phenomena to select multicycle paths as targets and to generate test patterns that are guaranteed to excite the worst-case delay along each target multicycle path. Finally, we present theoretical proofs and Monte Carlo simulation results for benchmark circuits under process variations to demonstrate that the patterns generated by our new ATPG are effective (invoke maximum delays of target multicycle paths) and efficient (require small numbers of patterns).

Integrated circuit (IC) camouflaging is a defense to defeat image-based reverse engineering. The security of CMOS ICs has been extensively studied and camouflage techniques have been developed. A camouflaging method is introduced here to protect superconducting electronics, specifically, rapid single flux quantum (RSFQ) technology, from reverse engineering. RSFQ camouflaged units have been developed by applying the structural similarity of RSFQ standard cells. A defense using camouflaged RSFQ cells combined with obfuscating the temporal distribution of inputs to the IC increases the attacker's effort to decamouflage. The approach establishes the complexity class of RSFQ decamouflaging and a model checker is applied to evaluate the strength of the defenses. These techniques have been evaluated on ISCAS’85 combinational benchmarks and the controllers of the OpenSPARC T1 microprocessor. A dummy Josephson junction fabrication process adds two additional mask steps that increase the cost overhead. Camouflaging 100% of the benchmark circuits results in an area and power overhead of almost 40%. In the case of the OpenSPARC processor, the approach requires near-zero area, power, and performance overhead even when 100% of the sensitive parts of the processor are camouflaged.

Devices used for rapid single flux quantum (RSFQ) cell interconnects include passive transmission lines (PTLs) and Josephson transmission lines. In this article, we demonstrate software analysis methods with which reflections on PTLs can be improved through impedance matching without compromising the margins of the connected RSFQ logic cells. RSFQ cells are typically designed to connect to PTL transmitters and receivers before attaching the PTL interconnects. These transmitters and receivers are used as matching and buffer stages between the cell and the PTL; and can be adjusted to minimize impedance mismatching. We integrate PTL transmitters and receivers within the RSFQ cell to decrease the amount of Josephson junctions required to incorporate PTL interconnect functionality. Frequency domain analysis on each cell provides equivalent impedance characteristics used for impedance matching.

Synthesizing general nonlinear sequential circuits in superconducting Single Flux Quantum (SFQ) technology is a challenging task involving the proper leveling of cyclic digraphs, handling nested feedback loops, and ensuring the full path balancing property throughout the synthesis process. This paper presents a precise definition of the level of a node in a cyclic digraph and a polynomial time algorithm for the corresponding level assignment and full path balancing in sequential SFQ circuits, including SFQ Finite State Machines (FSMs). A case study is conducted on a 3-bit counter, as an FSM, which has a power consumption of $44. 7 \mu W$ and $1. 4 \mu W$ using rapid SFQ and energy-efficient rapid RSFQ cells, respectively, with the local clock frequency of 55GHz (throughput of 11GHz) which is significantly higher than the typical CMOS clock frequencies. More results on larger SFQ circuits are also presented.

Recently, we demonstrated a rapid-single-flux-quantum NOT gate comprising a toggle storage loop. In this paper, we present our design and operation of a NOR gate that is a straightforward extension of the NOT gate by attaching a confluence buffer. Parameter margins wider than ±28% were confirmed in simulation. Functional tests using Nb integrated circuits demonstrated correct NOR operation with a bias margin of ±21%.

With the development of rapid single-flux-quantum (RSFQ) circuits, signal integrity issues of interconnects, such as signal distortion and crosstalk, become critical. Josephson junctions, as driver and receiver of interconnects, also affect signal integrity. Hence, it is significant to coanalyze time-domain responses of multicoupled passive transmission lines (PTLs) and Josephson junctions in RSFQ circuits. In this article, an accurate numerical method based on finite-difference time-domain (FDTD) is proposed to coanalyze multicoupled PTLs and Josephson junctions. The FDTD method is used to solve the telegraph equations of PTLs, and an iteration algorithm based on the contractive mapping theorem is proposed to solve the nonlinear equations generated by the Josephson junctions. In addition, the existence and uniqueness conditions of the nonlinear equations are also provided. The numerical and simulation results show that the proposed coanalysis method has the same accuracy as but higher efficiency than WRspice.

In this article, 8-bit bit-slice butterfly processing units (BPUs) are proposed for 64-point rapid single-flux-quantum (RSFQ) fast Fourier transform processors. The BPUs are based on radix-2, mixed-radix, and split-radix algorithms, respectively. Unlike the previously developed bit-serial RSFQ BPUs, the proposed bit-slice BPUs continuously process 64-point data divided into eight slices of eight points each in order to reduce the hardware cost. The BPUs use synchronous concurrent-flow clocking and they can be extended to any $n^2$ -point processing.

Energy-efficient rapid single flux quantum circuits having zero static power dissipation require a feeding Josephson junction transmission line (FJTL) to stabilize the power bus voltage. It is shown how a FJTL can be configured to obtain a desired current-bias window of constant delay, while preserving operability above and below that range as well, as a tradeoff against power and area. A test chip to validate circuit simulation results is designed with a gridded fabric for power delivery and cell placement, with consideration of passive transmission lines, magnetic flux exclusion, power bus isolation, and thermal noise. Measurements made on hardware fabricated in MIT Lincoln Lab's advanced 8-Nb-layer process correlate well with the model and indicate specific FJTL design challenges that need to be addressed.

Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 mu W per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.

As superconducting circuits grow in complexity, full transient simulation and verification at the Josephson junction level using analog circuit simulators become increasingly computationally expensive. To enable faster functional and timing verification using timing back annotation and static timing analysis, logic models of rapid single flux quantum library cells are developed using hardware description languages like Verilog together with the required timing characteristics. These include propagation delays and minimum pin-to-pin pulse arrival time separation at various process and operating corners. These timing parameters must satisfy required margins and yield using Monte Carlo simulations with statistical variations. For each library cell, these timing parameters depend not only on the adjacent cells but also on their internal states. These delay variations are driven by bias current redistribution, load inductance, and load junction critical currents. We present our methodology for extracting these timing parameters to enable timing back annotation and static timing analysis. We demonstrate our methodology with a parallel counter as a reference circuit and show that timing back annotated simulation can closely match results from full circuit simulation.

The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing, an issue of growing importance. In this paper, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Tradeoffs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A tradeoff between the proposed PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of $\pm$ 29% for the bias current of the proposed receiver operating at 20 GHz in a 10 kA/cm $^2$ technology for a 1-mm transmission line is achieved. Summarizing, guidelines and design tradeoffs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.

Nb/Al-AlO x /Nb Josephson junctions are widely used in superconducting quantum interference devices and rapid single flux quantum (RSFQ) circuits. Very large-scale RSFQ integration often has a strict requirement on wafer-scale junction qualities. In particular, Nb film stress in Nb/Al-AlO x /Nb trilayer based Josephson junctions is a critical factor affecting their qualities. In this work, we develop a multi-step sputtering process to prepare Nb films with different combinations of stress and roughness to investigate the correlation between Nb film stress and junction quality. In particular, this method allows us to prepare Nb films with almost the same roughness but different stress, a key factor to study solely the influence of stress on junction qualities. Our measurements indicate that within a very tight range of film roughness (less than 2 nm), tensile film stress is found to decrease the quality of Nb/Al-AlO x /Nb Josephson junctions and larger film roughness has a positive effect on junction quality. By decreasing the total tensile stress and increasing the film roughness properly, we fabricated Nb/Al-AlO x /Nb Josephson junctions with a high quality factor characterized by $R_{sg}/ R_{N}$ (30 on average). The minimum size of junctions was 1 μm.

Long ago, current recycling or serial biasing technique was recognized as a promising solution for the reduction of bias current in VLSI dc biased digital superconductor circuits. Despite a significant number of declarations, not so many successful experiments have been reported so far. In the paper we discuss our recent experiments with serially biased 16-bit counter-flow RSFQ shift registers, connected by special interfaces that are able to transfer SFQ pulses between the galvanically isolated driver and receiver. The required functionality is achieved using a superconductor transformer with isolated input and output coils. The known drawback of such interfaces is their parasitic sensitivity to magnetic fields induced by remote currents. To depress this sensitivity we have implemented a special superconductor guard that uses six superconductor layers. We have achieved stable operations of such registers with 16 current recycling stacks. The circuits have been fabricated at MIT Lincoln Laboratory.

We designed and tested the digital readout circuitry for superconducting nanowire single-photon detectors (SNSPDs). The designed time-to-digital converter (TDC) comprises a decision-making block, a clock controller, and a counter with parallel-to-serial (P2S) interface. We also designed an on-chip pattern generator to imitate a digitized SNSPD response that allowed us to screen the circuitry without bonding actual SNSPDs. Both rapid single-flux quantum (RSFQ) and its energy-efficient rapid single-flux quantum (ERSFQ) versions were designed for comparison and debugging purposes. To optimize the design of the feeding Josephson transmission line (FJTL) required by the ERSFQ variant, we compared different power grid structures and types of FJTLs. Using an 8-bit counter with P2S interface as a device under test, we also investigated the effect of FJTL's size on the bias margins. FJTL with a 75% junction overhead is sufficient for the ERSFQ circuit to match the margins of its RSFQ counterpart. All chips have been fabricated at MIT-LL using the SFQ5ee process node. Experimental results and future research directions are presented.

Energy-efficient rapid single flux quantum (ERSFQ) circuits have become a viable alternative for the implementation of superconducting circuits due to a large amount of static power consumption in RSFQ circuits. ERSFQ circuits are built upon the popular RSFQ logic circuits by replacing the power-dissipating resistor bias network with a bias network consisting of active devices. In this paper, a simulation study of ERSFQ biasing scheme is carried out by building simulation test benches for both synchronous and asynchronous ERSFQ circuits. A study is carried out to present the optimum value of biasing inductance, influence of the feeding Josephson transmission line (FJTL) and the effect of its size, the effect of the feeding clock frequency, and the effect of the circuit operating frequency. An innovative clock-choking mechanism using magnetic Josephson junctions is also proposed for the FJTL in the case of no logic circuit activity for a current-recycling circuit block, which would help in eliminating the dynamic power consumed due to the switching of bias junctions in a logic circuit. Simulation results for current recycling ERSFQ circuits are presented along with a strategy for implementing large superconducting circuits.

This paper presents a path balancing technology mapping algorithm, which is a new algorithm for generating a mapping solution for a given Boolean network such that the average logic level difference among fanin gates of each gate in the network is minimized. Path balancing technology mapping is required in dc-biased Single Flux Quantum (SFQ) circuits for guaranteeing the correct operation, and it is beneficial in CMOS circuits to reduce the hazard issues. We present a dynamic programming based algorithm for path balancing technology mapping which generates optimal solutions for dc-biased SFQ (e.g. Rapid SFQ or RSFQ) circuits with tree structure and acts as an effective heuristic for circuits with general Directed Acyclic Graph (DAG) structure. Experimental results show that our path balancing technology mapper reduces the balancing overhead by up to 2.7 times and with an average of 21% compared to the state-of-the-art academic technology mappers.

Equivalence checking is a key component of the verification methodology for digital circuit designs. In this paper, we propose an equivalence checking framework for superconducting rapid single-flux-quantum (RSFQ) logic circuits which include acyclic circuits and bit-slice-based cyclic circuits. It consists of a structure checker and a logic checker. The structure checker is used to check whether the circuit meets the design rules of superconducting RSFQ logic circuits. The logic checker can be used to check whether two RSFQ gate-level circuits have the same logic function. For the logic checker, we propose a logic equivalence checking method based on logic cone partition. The circuit network is simplified layer by layer and iteratively partitioned into logic cones, each of which is verified by the SMT solver. The experimental results show the feasibility of our approach on superconducting RSFQ logic circuits.

Among the major issues in modern large scale rapid single flux quantum circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS EDA techniques, and extremely deep pipelines which reduce the effective clock frequency. In this chapter, asynchronous dynamic SFQ majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large scale RSFQ circuits, thereby alleviating certain timing issues while reducing the required bias currents. Furthermore, asynchronous logic allows existing EDA tools to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in VLSI RSFQ circuits.

In this chapter, the most popular type of superconductive digital logic—rapid single flux quantum (RSFQ) logic—is described. The basic building blocks of digital RSFQ circuits are described in this chapter. Different types of transmission lines for this technology—JTL and PTL—are introduced, and the advantages and disadvantages of these interconnect structures are discussed. Certain basic structures of RSFQ circuits, flux storage loops, balanced comparators, and buffers, are described here as a framework to demonstrate the operation of more complex gates. Bias current distribution in RSFQ circuits is also discussed in this chapter. Resistive bias distribution, commonly used in RSFQ circuits, is described, and the disadvantages of this approach are reviewed. Energy efficient modifications to RSFQ logic to reduce or eliminate static power dissipation are also introduced, along with the advantages and disadvantages of these different circuit topologies. In particular, the ERSFQ bias scheme, which utilizes inductive current distribution with JJs as current regulators and feeding JTLs as voltage references, is introduced.

The primary operation of any processor is to perform basic arithmetic operations. In all basic arithmetic operations, multiplication consumes more time to be performed. Multiplier is the component which performs the multiplication operation. Its performance speed is going to affect the speed of the entire processing unit. The major operation of multiplier is to generate final product from partial products. To perform this major operation, the required architecture may require more area which intends to increase in latency in operation. In order to improve the performance of processor with minimum area, fast multiplier must be employed to perform multiplication operation. With high speed, the multiplier should occupy less area and consume low power. In the design of multipliers, a new technology called superconductor RSFQ logic is extensively used in order to achieve a multiplier design with less area and minimum latency in operation. From the time of introduction of this technology, different types of RSFQ multipliers are proposed. This paper gives an comparative analysis of rapid single flux quantum(RSFQ) technology multipliers like integer multiplier, matrix multiplier, parallel carry-save pipelined multiplier, floating-point multiplier in terms of area (number of Josephson junctions) and latency.

Rapid single flux quantum (RSFQ) technology promises high performance, energy efficient supercomputers to achieve DoE exascale computing. An important challenge in VLSI complexity RSFQ circuits is ultra-high speed clocking and synchronization. A methodology to support the automated design of clock distribution networks for SFQ circuits is the focus of this paper. Global clock synthesis of SFQ circuits is applied to produce a near zero skew clock network. An algorithm is presented that produces an SFQ H-tree network with asymmetric leaves to propagate the clock signal to all SFQ gates. A Python-based system with location information for the interconnects, splitters, and leaves is described. The algorithm determines the physical locations and connections within the SFQ clock network and is applicable to automated routing and clock tree synthesis.

Rapid single flux quantum (RSFQ) circuits have recently attracted considerable attention as a promising beyond CMOS technology for exascale computing. Unlike conventional CMOS circuits, RSFQ circuits require a specific bias current delivered to each Josephson junction, making robust bias networks an issue of great importance for large scale integration. ERSFQ is an energy efficient, inductive bias scheme for RSFQ circuits, where power dissipation is drastically lowered by eliminating the bias resistors while the cell library remains unchanged. An ERSFQ bias scheme requires the introduction of multiple circuit elements — current limiting Josephson junctions, bias inductors, and Josephson transmission lines. Multiple guidelines exist for the effective design of these structures. In this paper, additional parameter guidelines and design techniques are presented to decrease physical area and dynamic power dissipation while improving bias margins. These guidelines and techniques are applicable to automating the synthesis of bias networks to enable large scale ERSFQ circuits.

Single flux quantum (SFQ) digital circuits have shown the potential for high speed/low power computation applications. Unfortunately, because of the low integration density and low driving capability of SFQ circuits, realizing large-scale memories by using only SFQ circuits is still a challenge. Josephson-CMOS hybrid memory, hybridizing high-speed, low power SFQ circuits, and high-density CMOS memories is already proposed as a solution to the large-scale memory problem in RSFQ digital systems. In this article, an SFQ-based memory controller which works up to 10 GHz clock frequencies is designed for Josephson-CMOS hybrid memory systems. The memory controller acts as a SFQ/CMOS interface between the SFQ circuit and SRAM module and generates the required waveforms for SRAM read and write operations. The circuit which has 4-b data and 2-b address lines is fabricated with AIST 2.5 kA/cm2 STP2 process and operations of the circuits are verified. To demonstrate the scalability of the circuit, memory controller was scaled to 8-b data and 13-b address to control of the 64kb SRAM. Operations of the scaled memory controller are verified with analog simulations. Scaled circuit consumes 0.76 mW power in an area of 1.64 mm × 1.60 mm.

The superconducting rapid single flux quantum (RSFQ) logic circuit has the characteristics of high speed and low power consumption, making it an attractive candidate for future supercomputers. However, computer-aided design (CAD) tools for CMOS cannot be directly applied to RSFQ logic due to their distinct properties. For instance, the RSFQ logic gate can work properly when all its fan-ins have the same logic level. This paper presents the design flow from RTL to RSFQ logic netlist and schematic. First, we implement logic synthesis for RSFQ logic circuits. It achieves path balancing while minimizing the number of DFFs. In addition, we propose an automatic schematic generator for the RSFQ logic circuits. It converts the synthesized netlist into its equivalent schematic. A layer assignment algorithm is proposed, which makes all gates layered in the order of the clock arrival time. Experimental results with ISCAS85 and EPFL benchmarks along with some Kogge-Stone adders have shown a 29.2% reduction in the number of DFFs over the breadth-first first search; moreover, 59.57% and 5.3% decrease in the number of layers of the schematic and number of edge crossings over the ELK tool.

Purpose The lack of reliable and scalable superconducting random access memory (RAM) cells is the main obstacle for full implementation of superconducting rapid single flux quantum(RSFQ) computers. This work points the methodology and the structures that shall be used in future implementation of RSFQ RAM. Design/methodology/approach A new design for RAM using two ferromagnetic strips in proximity to the superconductor in a RSFQ computer is presented (1). The concept of using a RAM RSFQ cell as a tuneable superconducting qubit is also explored. Findings Two basic architectures for superconducting RAM cells were developed with integration schemes in two dimensions. Research limitations/implications The proposed RAM cells as depicted in Figures 7 and 16 offer smaller size and greater 3 scalability in comparison to other suggested schemes (4), (3), (2), (5). Practical implications Currently, the main obstacle in implementation of RSQF computer is lack of reliable RAM cell. RSQF computer shall have potential to take a large fraction of classical supercomputers, as it consumes much less power. Social implications Computation power shall be cheaper when one uses RSQF computers for big data and computational centres. It is a matter of some time. Originality/value The publication presents the new design of superconducting RAM cell for use in RSQF computer. The numerical relaxation method is used to solve biharmonic Ginzburg–Landau equation. The analytic approach as a solution of a specified problem is given.

We propose a scalable readout interface for superconducting nanowire single-photon detector (SSPD) arrays, which we call the AQFP/RSFQ interface. This interface is composed of adiabatic quantum-flux-parametron (AQFP) and rapid single-flux-quantum (RSFQ) logic families. The AQFP part reads out the spatial information of an SSPD array via a single cable, and the RSFQ part reads out the temporal information via a single cable. The hybrid interface has high temporal resolution owing to low timing jitter in the operation of the RSFQ part. In addition, the hybrid interface achieves high circuit scalability because of low supply current in the operation of the AQFP part. Therefore, the hybrid interface is suitable for handling many-pixel SSPD arrays. We demonstrate a four-pixel SSPD array using the hybrid interface as proof of concept. The measurement results show that the hybrid interface can read out all of the pixels with a low error rate and low timing jitter., 10 pages, 6 figures

A 32-bit 4 × 4 bit-slice rapid single-flux-quantum (RSFQ) matrix multiplier is proposed. The multiplier mainly consists of bit-slice multipliers and bit-slice adders. The multiplication of unsigned integer matrices is implemented by control signals. The matrix multiplier used synchronous concurrent-flow clocking. The results show that a 16-bit bit-slice processing has the least latency at 10 GHz.

To meet the specification of the qubits in our laboratory, a 0.4 kA·cm−2 superconducting rapid single flux quantum (RSFQ) circuit was designed and successfully fabricated with an improved Nb-based self-aligned lift-off process. This circuit consists of a single-flux-quantum (SFQ) pulse generator, a Josephson transmission line (JTL) and a T-flip flop (TFF), and it acts as a frequency divider. The values of the inductors in this circuit were extracted using InductEX and the basic function of this circuit was confirmed using the simulation software WRspice before fabrication. After fabrication, the basic parameters of this circuit were measured at ~ 2.5 K in a Janis He-3 cryostat. This work laid the theoretical and experimental basis for the future research on the RSFQ-qubit control circuits.

Static timing analysis in the rapid-single-flux-quantum and energy-efficient RSFQ superconducting digital circuit domain is yet to be achieved in a generic sense. A static timing analysis tool is proposed here for preplacement designs as well as postplaced and routed designs. Preplaced static timing analysis attempts to find a general gauge for the performance of a JSIM/SPICE netlist in the absence of information on wiring delays. The postplaced and routed static timing analysis provides a more accurate analysis of a design in the cadence design exchange format. This design file should include all the wire lengths as well as a complete clocking scheme. Results of this postplaced and routed static timing analysis are then used to determine the maximum clock speed that the design can be run at to prevent timing violations. Results for both methods of analysis are presented and then incorporated in an hardware description language representation of the design to show that there are no timing violations at the presented clock speed. We show the implementation of a static timing analysis method developed as a precursor to the IARPA SuperTools project, and how it applies to circuits with H-tree and HL-tree clocking schemes.

A fast wire-routing method considering wire-length matching of passive transmission lines (PTLs) is proposed. The method deals with channel routing between adjacent columns of active devices, and generates paths of PTLs with specified additional length packed in compact area based on simulated annealing. It uses a generation method of paths from a sequence of symbols for searching solutions efficiently. An automatic layout tool is also shown. It consists of a placer and a router based on the proposed method. The placer uses total extension length of PTLs for length matching as one of the evaluation metrics for detailed placement using simulated annealing. By introducing this metric, total extension length in routing phase is reduced and compact layouts are obtained. Using the tool, design flow from HDL descriptions to layout generation can be established. As an experimental result, a layout of an adder designed by the tool is shown.

A 16-bit bit-slice arithmetic logic unit (ALU) is proposed for 32-/64-bit rapid single-flux-quantum microprocessors. It is based on a Ladner-Fischer adder. The ALU covers all of the ALU operations for MIPS32 instructions set. And each of the two 64-bit operands is divided into four slices of 16 bits each. The ALU uses synchronous concurrent-flow clocking and consists of 11 pipeline stages. The proposed ALU can be used for any 16n-bit processing.

A Josephson junction is a device made of two superconducting electrodes separated by a very thin layer of isolator or normal metal. This relatively simple device has found a variety of technical applications in the form of Superconducting Quantum Interference Devices (SQUIDs) and Single Electron Transistors (SETs). One can expect that in the near future the Josephson junction will find applications in digital electronics technology RSFQ (Rapid Single Flux Quantum) and in the more distant future in construction of quantum computers. Here we concentrate on the relation of the curvature of the Josephson junction with its inductance. We apply a simple Capacitively Shunted Junction (CSJ) model in order to find condition which guarantees consistency of this model with prediction based on the Maxwell and London equations with Landau-Ginzburg current of Cooper pairs. This condition can find direct experimental verification. Keywords: Josephson junction, CSJ model, Fluxon

We present the results of an analytical study and numerical simulation of the dynamics of a superconducting three-Josephson-junction (3JJ) flux qubit magnetically coupled with rapid single-flux quantum (RSFQ) logic circuit, which demonstrate the fundamental possibility of implementing the simplest logic operations at picosecond times, as well as rapid non-destructive readout. It is shown that when solving optimization problems, the qubit dynamics can be conveniently interpreted as a precession of the magnetic moment vector around the direction of the magnetic field. In this case, the role of magnetic field components is played by combinations of the Hamiltonian matrix elements, and the role of the magnetic moment is played by the Bloch vector. Features of the 3JJ qubit model are discussed during the analysis of how the qubit is affected by exposure to a short control pulse, as are the similarities between the Bloch and Landau-Lifshitz-Gilbert equations. An analysis of solutions to the Bloch equations made...

As the digital data links for superconducting circuits advance and higher data throughput per channel becomes possible, timing margins shrink and data integrity becomes a major challenge. Particular interest for multichannel applications is establishing the high-quality data link to interface with subsequent electronics. In this paper, we focus on integration of an on-chip pseudorandom binary sequence (PRBS) generator into a superconducting analog-to-digital converter (ADC) design to facilitate link stability evaluation and automated interchannel synchronization. PRBS generator and the ADC use a common clock source. An on-chip deserializer/demux, which includes the output drivers, is driven by a set of data sources depending on switch selections on-chip. The outputs are connected to a field-programmable gate array (FPGA) at room temperature, which hosts the developed interface circuitry for data reception, data integrity evaluation, and the synchronization mechanism. The integrated circuit (IC) that combines ADC and PRBS7 generator circuit was designed for the HYPRES 4.5 kA/cm2 four-layer standard fabrication process and features four deserialized outputs. A second similar IC was designed comprising an ADC frontend as well as a PRBS15 generator and was fabricated in the MIT-LL 10 kA/cm2 process. The implemented alignment engine that bonds the individual channels into a single data link was proven up to 10 Gbps while taking 1–2 μ s to complete the alignment. We built chip-to-FPGA data links, comprising the on-chip driver and room-temperature interface amplifier, up to 14 Gbps using FPGA serial-link GTY transceiver. Successful data transport from an ADC using multiple parallel data links to an FPGA upon completion of the channel bonding was demonstrated.

Reconfigurable superconducting phase shift elements (PSEs) provide high design flexibility in rapid single flux quantum (RSFQ) circuits. Small ferromagnetic patterns were placed on superconducting loops in an RSFQ circuit. The patterns serve as reconfigurable PSEs providing the direction and magnitude of magnetization can be controlled for each pattern individually. A two-dimensional wire mesh architecture was employed to allow for individual configuration and to reduce the number of wires required. Although opposing magnetic fields may occasionally be generated during half-selection using this architecture, experimentally obtained magnetization curves revealed that the orientation of the magnetic field was maintained. An RSFQ circuit, using a reconfigurable PSE, has been successfully demonstrated, potentially leading to large-scale reconfigurable RSFQ circuits

Efficiently amplifying the high-speed and low-voltage swing outputs of single flux quantum (SFQ) logic to levels that are suitable for interfacing with room temperature electronics has been a long-standing challenge in the field of superconducting electronics. In this work, we investigate the feasibility of using a lossy passive matching network at 4 K, with a pair of differential 100 low-noise amplifiers heatsunk to 18 K and 50 K stages, respectively. The amplifiers were implemented in a 120 nm SiGe BiCMOS technology. The amplification chain is dc coupled and the small-signal link gain was measured to be approximately 48 dB. The power consumption of each of the two amplification stages was 6.3 mW. The chain was measured at 21 K using a high-speed differential nonreturn-to-zero signal having amplitude commensurate with what one would expect from a superconducting circuit, and clean eye diagrams were observed for data rates as high as 30 Gb/s. The chain was also measured when driven from an SFQ/dc interface, with the first gain stage heatsunk to 9 K. In this configuration, clean eye diagrams were observed to 5 Gb/s, with the speed limitation being related to packaging parasitics.

We present design and experimental results of a rapid single-flux-quantum (RSFQ) bit-serial microprocessor with reduced-size embedded random access memories (RAMs) and with a minimal instruction set, called CORE e2h. The microprocessors called CORE e series have been developed for demonstrating small-scale program execution, such as loop calculation and sorting, in order to show the first prototype of a stored-program computer using the RSFQ technology. The CORE e2h is the most simplified variation of the CORE e series, which is equipped with only two registers, and can execute 13 instructions. The target clock frequency for bit-serial operation is 50 GHz, while the designed system clock cycle is 2 GHz. We carefully designed every component, implementing functionality using a small number of Josephson junctions with a small footprint. We fabricated several chips of the CORE e2h microprocessor integrated with two 128-bit shift-register-based RAMs on the same die. We experimentally obtained correct operations for all the instructions, and confirmed high-speed transfer between the instruction memory and controller unit and between the data memory and datapath at around 50 GHz.

A design of a 32 × 32-bit 4-bit bit-slice integer multiplier for rapid single-flux quantum microprocessors is shown. The multiplier carries out both signed and unsigned multiplication. It is designed with synchronous concurrent-flow clocking and target frequency of 50 GHz using the AIST 1.0-μm Nb/AlO x /Nb, nine-layer advanced process 2 fabrication technology with a critical current density of 10 kA/cm 2. It consists of 56 885 Josephson junctions. The area is 12.00 × 6.65 mm2. The simulation results show correct operation with frequency of 50 GHz at the dc bias voltage of 2.5 mV. The throughput is 3.125 × 109 multiplications per second.