322 results on '"Sarkar, Angsuman"'
Search Results
52. Low power and high speed design issues of CMOS Hamming code generation and error detection circuit at 22 nm and 16 nm channel length of MOS transistor
53. Analytical modelling of a Cyl-JLAM MOSFET in the subthreshold region using distinct device geometry
54. Blueshift of Optical Signal in PhC Based Butterworth Filter Due to Joule Heat Dissipation
55. Fast Squaring Technique for Radix Vicinity Numbers for Radix 2 n ± M with Reduced Computational Complexity
56. Computing Surface Potential and Drain Current in Nanometric Double-Gate MOSFET Using Ortiz-Conde Model
57. Special issue on selected papers on experimental research on emerging electronic and optical materials for device applications
58. Secure nano-communication framework using RSCV cryptographic circuit in IBM Q
59. Threshold and surface potential-based sensitivity analysis of symmetrical double gate AlGaN/GaN MOS-HEMT including capacitance effects for label-free biosensing
60. Soft Computing Techniques Based CAD Approach for Power Supply Noise Reduction in System-on-Chip
61. Analytical model and sensitivity analysis of a gate-engineered dielectric modulated junctionless nanowire transistor-based biosensor
62. Contributors
63. Classification of single and double-gate nanoscale MOSFET with different dielectrics from electrical characteristics using soft computing techniques
64. Calculating Transmittance and Field Enhancement of n-Layer MIM Surface Plasmon Structure for Detection of Biological Nano-Objects
65. Investigation of the Effect of Barrier Layer Engineering on DC and RF Performance of Gate-Recessed AlGaN/GaN HEMT
66. Authentic Pedagogy: A Project-Oriented Teaching–Learning Method Based on Critical Thinking
67. Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications.
68. Preface
69. 2D analytical modelling of asymmetric junctionless dual material double gate MOSFET for biosensing applications considering steric hindrance issue
70. Analytical Modeling of Asymmetric Junctionless Dual Material Double Gate MOSFET with Underlap for Enhanced Hot Carrier Reliability
71. Device Performance Analysis for Different Gate Locations in AlGaN/GaN HEMT by Silvaco Simulation
72. Ensemble Learning strategy in modeling of future generation nanoscale devices using Machine Learning
73. Design of Secure Reversible Select, Cross and Variation (RSCV) Architecture in Quantum Computing
74. Single Layer Design of Dual Banyan Network Using Quantum-Dot Cellular Automata
75. Computing Surface Potential and Drain Current in Nanometric Double-Gate MOSFET Using Ortiz-Conde Model
76. An Analytical Surface Potential Model of Surrounding Gate Tunnel FET
77. The Impact of Gate Underlap on Analog and RF Performance of Hetero-Junction FET
78. Fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs
79. Photo-electric Characteristics Analysis of Quantum Corrected Strained Nanowire Drift-Diffusion Model based Si/Si0.98C0.02 Asymmetrical Super-lattice Near Infrared Photo-detector
80. Hetero-structure Junctionless MOSFET with high-k corner spacer for high-speed and energy-efficient applications
81. Tunnel FET based Standard Logic Cell Implementation: A Circuit Perspective
82. Impact of Aspect Ratio and Interface Trap Charge on the Performances of Junctionless MOSFET-Based Adiabatic Logic Circuit
83. Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire Tunnel FET
84. Impact of barrier thickness on Analog, RF and Linearity performance of nanoscale DG heterostructure MOSFET
85. Fast Squaring Technique for Radix Vicinity Numbers for Radix 2n ± M with Reduced Computational Complexity
86. Calculating Transmittance and Field Enhancement of n-Layer MIM Surface Plasmon Structure for Detection of Biological Nano-Objects
87. Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE
88. Investigation of analog/RF performance of staggered heterojunctions based nanowire tunneling field-effect transistors
89. Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study
90. Analytical Modeling of Dielectric Modulated Triple Material Stacked Surrounding Gate Junctionless MOSFET based label free Biosensor
91. Performance Analysis of New Dual-Pocket Tunnel-FET-based Biosensor
92. Analytical Investigation of Gate-to-Drain Leakage Current for Junctionless Accumulation-Mode MOSFET
93. Analytical Modeling of Asymmetric Gate Stack Junctionless Dual Material Surrounding Gate MOSFET for Enhanced Hot Carrier Reliability
94. Design and power analysis of 4 × 4 semiconductor ROM array with row decoder and column decoder at 32, 22 and 16 nm channel length of MOS transistor
95. Analytical modeling and sensitivity analysis of dielectric-modulated junctionless gate stack surrounding gate MOSFET (JLGSSRG) for application as biosensor
96. Chapter 16 - TCAD simulation of emerging nanoscale devices
97. Analytical study of Dual Material Surrounding Gate MOSFET to suppress short-channel effects (SCEs)
98. Protection, Restoration, and Improvement
99. Nonlinear All‐Optical Switch
100. MEMS‐based Optical Switches
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