415 results on '"Tadashi Shibata"'
Search Results
52. A delay-encoding-logic array processor for dynamic programming matching.
53. Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters.
54. A bump-circuit-based motion detector using projected-activity histograms.
55. A real-time VLSI median filter employing two-dimensional bit-propagating architecture.
56. An edge-based face detection algorithm robust against illumination, focus, and scale variations.
57. Multiple-clue face detection algorithm using edge-based feature vectors.
58. A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture.
59. Unsupervised Object Extraction by Contour Delineation and Texture Discrimination Based on Oriented Edge Features.
60. Robust cephalometric landmark identification using support vector machines.
61. A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors.
62. An analog image processing LSI employing scanning line-parallel processing.
63. A Robust Medical Image Recognition System Employing Edge-Based Feature Vector Representation.
64. Speaker and text independent language identification using predictive error histogram vectors.
65. Intelligent Internet Search Applications Based on VLSI Associative Processors.
66. An associative-processor-based mixed signal system for robust grayscale image recognition.
67. A zone-programmed EEPROM with real-time write monitoring for analog data storage.
68. A motion-based analog VLSI saliency detector using quasi-two-dimensional hardware algorithm.
69. Low-power CDMA analog matched filters based on floating-gate technology.
70. Human-perception-like image recognition system based on the Associative Processor architecture.
71. A human-perception-like image recognition system based on PAP vector representation with multi resolution concept.
72. A hardware friendly algorithm for action recognition using spatio-temporal motion-field patches.
73. A Directional-Edge-Based Real-Time Object Tracking System Employing Multiple Candidate-Location Generation.
74. Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology.
75. An analog similarity evaluation circuit featuring variable functional forms.
76. High-precision analog EEPROM with real-time write monitoring.
77. A fast self-convergent flash-memory programming scheme for MV and analog data storage.
78. A hardware-friendly soft-computing algorithm for image recognition.
79. An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine.
80. A Neuron-MOS-Based VLSI Implementation of Pulse-Coupled Neural Networks for Image Feature Generation.
81. An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations.
82. Block-matching-based motion field generation utilizing directional edge displacement.
83. A Case of Traumatic Appendiceal Transection Diagnosed and Treated by Laparoscopic Surgery
84. A neuron-MOS parallel associator for high-speed CDMA matched filter.
85. A Pixel-Parallel Self-Similitude Processing for Multiple-Resolution Edge-Filtering Analog Image Sensors.
86. A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing.
87. A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter.
88. Right brain computing hardware: a psychological brain model on silicon.
89. Neuron-MOS continuous-time winner-take-all circuit for intelligent data processing.
90. Functional-Device-Based VLSI for Intelligent Electronic Systems.
91. A Low-Power Floating-Gate-MOS-Based CDMA Matched Filter Featuring Coupling Capacitor Disconnection.
92. A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture.
93. An Intelligent Action Control System Based on Extended Vector Annotated Logic Program and its Hardware Implementation.
94. Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing.
95. A low-power and compact CDMA matched filter based on switched-current technology.
96. A delay-encoding-logic array processor for dynamic-programming matching of data sequences.
97. Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors.
98. A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications.
99. Analog soft-pattern-matching classifier using floating-gate MOS technology.
100. Guest editorial - Special issue on neural networks hardware implementations.
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