1,726 results on '"Tenhunen, Hannu"'
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52. Global Interconnect Analysis
53. Wires as Interconnects
54. Interactive UHF/UWB RFID tag for mass customization
55. Internet of things for remote elderly monitoring: a study from user-centered perspective
56. PDNOC: An Efficient Partially Diagonal Network-on-Chip Design
57. Path-Based Multicast Routing for 2D and 3D Mesh Networks
58. Will Networks on Chip Close the Productivity Gap?
59. SEA: A Secure and Efficient Authentication and Authorization Architecture for IoT-Based Healthcare Using Smart Gateways
60. LISA: Lightweight Internet of Things Service Bus Architecture
61. OPTNOC: An Optimized 3D Network-on-Chip Design for Fast Memory Access
62. Study of Hierarchical N-Body Methods for Network-on-Chip Architectures
63. A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors
64. Exploring Congestion-Aware Methods for Distributing Traffic in On-Chip Networks
65. A Minimal Average Accessing Time Scheduler for Multicore Processors
66. Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels
67. Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication
68. A Computational Scheme Based on Random Boolean Networks
69. Leveraging Fog Computing for Healthcare IoT
70. Positioning Antifragility for Clouds on Public Infrastructures
71. LISA 2.0: lightweight internet of things service bus architecture using node centric networking
72. Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses
73. Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers
74. A development and verification framework for the SegBus platform
75. Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes
76. Optimal placement of vertical connections in 3D Network-on-Chip
77. Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip
78. Design and implementation of reconfigurable FIFOs for Voltage/Frequency Island-based Networks-on-Chip
79. Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
80. Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture
81. A systematic reordering mechanism for on-chip networks using efficient congestion-aware method
82. The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance
83. A Design of Operational Amplifiers for Sigma Delta Modulators using 0.35um CMOS Process
84. Evaluating Sustainability, Environment Assessment and Toxic Emissions in Life Cycle Stages of Printed Antenna
85. An Optimized Network-on-Chip Design for Data Parallel FFT1
86. Self-aware Early Warning Score System for IoT-Based Personalized Healthcare
87. Design Techniques of 5G Mobile Devices in the Dark Silicon Era
88. A Demand-Response Scheme Using Multi-Agent System for Smart DC Microgrid
89. Real-Time Classification of Pain Level Using Zygomaticus and Corrugator EMG Features
90. A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip
91. A generic adaptive path-based routing method for MPSoCs
92. A study of 3D Network-on-Chip design for data parallel H.264 coding
93. Service based communication for MPSoC platform- SegBus
94. Real-Time Classification of Pain Level Using Zygomaticus and Corrugator EMG Features
95. Context-Aware Early Warning System for In-Home Healthcare Using Internet-of-Things
96. Elderly Monitoring System with Sleep and Fall Detector
97. Private reliability environments for efficient fault-tolerance in CGRAs
98. Special section on advances in methods for adaptive multicore systems
99. Technologies and utilization of Field Programmable Gate Arrays
100. Interconnection alternatives for hierarchical monitoring communication in parallel SoCs
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