534 results on '"Wang, Chua-Chin"'
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52. Lightweight Deep Neural Network for Joint Learning of Underwater Object Detection and Color Conversion
53. A 2.71 fJ/conversion-step 10-bit 50 MSPS split-capacitor array SAR ADC for FOG systems
54. A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic
55. Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique
56. Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process
57. Analysis of Layout Arrangement for CMOS Oscillators to Reduce Overall Variation on Silicon
58. A 100-MHz 3.352-mW 8-bit shift register using low-power DETFF using 90-nm CMOS process
59. A 40-nm CMOS Wide Input Range and Variable Gain Time-Difference Amplifier Based on Current Source Architecture
60. Single-chip DC–DC buck converter design based on PWM with high-efficiency in light load
61. A CMOS On-Chip High-Precision PVTL Detector
62. A 2×VDD output buffer with PVT detector for slew rate compensation
63. A low-power transceiver design for FlexRay-based communication systems
64. A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers
65. Feed-forward Output Swing Prediction AGC design with Parallel-Detect Singular-Store Peak Detector
66. A high precision low dropout regulator with nested feedback loops
67. A high-efficiency DC–DC buck converter for sub-2×VDD power supply
68. An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS
69. A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit
70. A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM
71. A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology
72. A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment
73. A FlexRay Transceiver Design with Bus Guardian for In-car Networking Systems Compliant with FlexRay Standard
74. A low-power 2.45 GHz WPAN modulator/demodulator
75. Ultrasonic transcutaneous energy transfer using a continuous wave 650 kHz Gaussian shaded transmitter
76. Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer
77. On-chip CMOS Corner Detector Design for Panel Drivers*
78. 200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process
79. A 12-bit 100-Msps DAC with 75.3 dB SFDR Using Randomized Biasing Current Source Selection for Real-time FOG Systems
80. An AI AUV Enabling Vision-based Diver-following and Obstacle Avoidance with 3D-modeling Dataset
81. High Resolution Time-to-Digital Converter Design with Anti-PVT-Variation Mechanism
82. A 10-bit 50-MS/s SAR ADC with Split-Capacitor Array Using Unity-Gain Amplifiers Applied in FOG Systems
83. A PFM-controlled LED Driver To Achieve Consistent Illuminance
84. SRAM-Based Computation in Memory Architecture to Realize Single Command of Add-Multiply Operation and Multifunction
85. 67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process
86. A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop
87. A Signed Array Multiplier with Bypassing Logic
88. A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset
89. A low-power ADPLL using feedback DCO quarterly disabled in time domain
90. A single-chip CMOS IF-band converter design for DVB-T receivers
91. A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants
92. Energy-Efficient Double-Edge Triggered Flip-Flop
93. A linear LDO regulator with modified NMCF frequency compensation independent of off-chip capacitor and ESR
94. Low-Power Multiplier Design Using a Bypassing Technique
95. High-PSR sync separator for TV signals
96. Wide-range 5.0/3.3/1.8-V I/O buffer using 0.35-[micro]m 3.3-V CMOS technology
97. Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection
98. 70 dB Dynamic Range CMOS Wideband Digital Variable Gain Amplifier for AGC in DVB-T/H Receivers
99. A 40-nm CMOS Piezoelectric Energy Harvesting IC for Wearable Biomedical Applications
100. Tutorial: Design of High-Speed Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer With High Reliability to PVTL Variations
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