467 results on '"Witters, L."'
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52. Superior NBTI in High- $k$ SiGe Transistors–Part I: Experimental
53. Superior NBTI in High-k SiGe Transistors–Part II: Theory
54. Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: Demonstration of a suitable gate stack for top and bottom tier nMOS
55. Experimental comparison between relaxed and strained Ge pFinFETs
56. Observation and understanding of anisotropic strain relaxation in selectively grown SiGe fin structures
57. Processing Technologies for Advanced Ge Devices
58. Self-heating in FinFET and GAA-NW using Si, Ge and III/V channels
59. Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem?
60. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes
61. Si-passivated Ge nFET towards a reliable Ge CMOS
62. (Invited) Generation-Recombination Noise in Advanced CMOS Devices
63. Beyond-Si materials and devices for more Moore and more than Moore applications
64. Understanding charge traps for optimizing Si-passivated Ge nMOSFETs
65. Patterning challenges in advanced device architectures: FinFETs to nanowires
66. Low frequency noise and fin width study of silicon passivated germanium pFinFETs
67. Self-aligned double patterning process for subtractive Ge fin fabrication at 45-nm pitch
68. Strained c:Si0.55Ge0.45 with embedded e:Si0.75Ge0.25 S/D IFQW SiGe-pFET for DRAM periphery applications
69. Effective hole mobility and low-frequency noise characterization of Ge pFinFETs
70. Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation
71. (Invited) Selective Etch of Si and SiGe for Gate All-Around Device Architecture
72. Advanced channel materials for the semiconductor industry
73. Editors' Choice--Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures.
74. AC NBTI of Ge pMOSFETs: Impact of energy alternating defects on lifetime prediction
75. Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal
76. Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect
77. Characterization of self-heating in high-mobility Ge FinFET pMOS devices
78. Sub-nm EOT high-mobility SiGe-55% channel pFETs: Delivering high performance at scaled VDD
79. Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime
80. First demonstration of 15nm-WFIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain
81. BTI reliability of advanced gate stacks for Beyond-Silicon devices: Challenges and opportunities
82. BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs
83. The device architecture dilemma for CMOS technologies
84. Next Generation FinFET Devices in Bulk Silicon Technology and Their Benefits for ESD Robustness
85. ESD Constraints of Bulk FinFET in Comparison with SOI FinFET Structures
86. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
87. Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to lOnm and 30nm gate length
88. Superior NBTI in High- $k$ SiGe Transistors?Part I: Experimental.
89. Processing Technologies for Advanced Ge Devices.
90. Regulation of mTOR function in response to hypoxia by REDD1 and the TSC1/TSC2 tumor suppressor complex
91. Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins
92. Impact of stressors in future SiGe-based FinFETs: Mobility boost and scalability
93. 15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process
94. Ground plane influence on enhanced dynamic threshold UTBB SOI nMOSFETs
95. Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO2/HfO2 pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks
96. Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process
97. Post-translational modifications of the beta-1 subunit of AMP-activated protein kinase affect enzyme activity and cellular localization
98. (Invited) Status and Trends in Ge CMOS Technology
99. Kinetic Monte Carlo simulations for dopant diffusion and defects in Si and SiGe: Analysis of dopants in SiGe-channel Quantum Well
100. (Invited) Stress Simulations of Si- and Ge-Channel FinFETs for the 14 nm-Node and Beyond
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