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We discuss the prospects and challenges for implementing a quantum computer using superconducting electronics. It appears that Josephson junction devices operating at milli-Kelvin temperatures can achieve a quantum dephasing time of milliseconds, allowing quantum coherent computations of 10/sup 10/ or more steps. This figure of merit is comparable to that of atomic systems currently being studied for quantum computation. [ABSTRACT FROM PUBLISHER]

For being used in the design of Rapid Single Flux Quantum (RSFQ) circuits in a multipurpose manner, we developed a systematic and consistent approach for modeling the nominal circuit behavior using hardware description languages. We are presenting a method for establishing evaluation criteria for the circuit's behavior which can directly be used in the input for circuit simulation and serve as a behavioral reference in yield-driven optimization cycles. Furthermore, this behavioral modeling technique allows for mixed-mode simulation with its advantages of both analysis speed-up and error localization. Finally, we demonstrate the application in high-level circuit synthesis which will be necessary to manage complex design problems. [ABSTRACT FROM PUBLISHER]

We present simple Complementary Josephson Junction circuits using 1 kA/cm/sup 2/ Nb junctions. We use long, sine-shaped junctions in order to achieve gain and suppressed side lobes. We have simulated layout-extracted simple inverter and ring oscillator circuits to evaluate the performance of these circuits in 1 kA/cm/sup 2/ technology. Projected gate delays with possible higher critical current density technologies are also simulated. We have experimentally tested the operation of inverter circuits. [ABSTRACT FROM PUBLISHER]

A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a demultiplexor, and a self-timed high speed digital test system. In this paper, test results of a 4-bit DDST shift register and a high speed on-chip clock generator will be presented to demonstrate the successful DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s. [ABSTRACT FROM PUBLISHER]

Aimed for the design of superconducting digital circuits, a direct method is proposed to estimate the inductance of three-dimensional microscopic superconducting loop. This method directly computes current-density distribution by using the Maxwell equations and the expression of the momentum, which are both discretized; without free-energy minimization technique, we just solve a set of linear equations considering a spatially-discrete model. Computer simulation was carried out for various shapes of superconductors, and the simulated results agreed well with the Chang's formula in a model which can be regarded as two-dimensional. The magnetic field distribution also agreed well with the theoretical value. [ABSTRACT FROM PUBLISHER]

Quantum Flux Parametron (QFP) logic gates were designed and fabricated from a single layer of YBa/sub 2/Cu/sub 3/O/sub 7/ thin film based on step-edge Josephson junctions. Self-inductance (L) of the QFP loop, an important circuit parameter, as is critical current (J/sub c/) of the Josephson junction, was determined by using directly coupled dc superconducting quantum interference devices (SQUIDs). Magnetically coupled dc SQUIDs were used to detect the output signal from the QFP. Simulated waveforms were used to identify the operation modes of the QFP as a function of the circuit parameters. From examination of the output waveforms of the QFP, operation in agreement with simulations was confirmed. [ABSTRACT FROM PUBLISHER]

The use of high-T/sub c/ Josephson junctions for digital applications requires a careful study of the influence of thermal noise on circuit performance. We investigated a balanced current comparator, which contains a basic component of all RSFQ circuits: two overdamped Josephson junctions connected in series. The dependence of the dc-voltage across the Josephson junctions on signal current was measured to determine the threshold uncertainty of switching of the comparator. The experimental data obtained at different sampling pulse frequencies, in a temperature range from 10 to 50 K, were compared with a theoretical model, taking into account the influence of thermal noise as well as of sampling pulse frequency. [ABSTRACT FROM PUBLISHER]

A major drawback of present superconducting electronics is the lack of suitable large scale memory. One approach to circumvent this problem is to use semiconducting CMOS memory in conjunction with the fast Josephson junction (JJ) logic. This requires operating the CMOS memory at cryogenic temperatures. The speed of CMOS circuits has been shown to increase at cryogenic temperatures. Further increase in speed can be obtained by using JJ sense circuits in the CMOS memory. Preliminary results show that access time of 1.5 ns should be possible with this hybrid JJ/CMOS approach using 1.2 micron CMOS, and JJ sense and interface circuits. We also report the results of an analysis of the optimal operating temperature of such hybrid memories in conjunction with refrigeration requirements in light of the emerging cryocooler technologies. [ABSTRACT FROM PUBLISHER]

We propose non-latching gates based on Superconducting QUantum Interference Device (SQUID) and logic circuits based on it. The gate consists of a 3-junction-SQUID coupled with an RF-SQUID inductively. According to numerical simulation, the wide bias margin reached /spl plusmn/52%. Adopting the magnetic coupling to apply input signals, the fan-out larger than unity was obtained without reducing signal current level. These consequences enabled us to realize complicated logic functions using this gate, The gate delay was 4.5ps at Jc=10kA/cm/sup 2/. An EXOR gate composed of two gates had the bias margin of /spl plusmn/35% and the delay time of 12ps. The operation in non-latching mode is also suitable for digital circuits based on HTS junctions. [ABSTRACT FROM PUBLISHER]

The high speed and low power of Single Flux Quantum logic (SFQ) are extremely attractive, and significant capabilities have been demonstrated in Nb technology. However the burden of cooling to 4.2K has been a barrier to its widespread implementation. The advent of High Temperature Superconductors (HTS), raises the prospect of more accessible temperatures. This paper examines some theoretical constraints on the implementation of SFQ in HTS, and derives some ideas about the parameters required of any HTS SFQ technology. [ABSTRACT FROM PUBLISHER]

An integrated multipurpose setup for the automated testing of superconductor devices and circuits has been designed, implemented, and installed in the RSFQ Laboratory of the State University of New York at Stony Brook. The extendable and modular design of the setup allows a wide variety of low-frequency superconductor experiments to be carried out including those that require immediate interaction between the setup and the researcher. [ABSTRACT FROM PUBLISHER]

We present the design and the fabrication of an adder circuit in the extended phase-mode logic family. The phase-mode logic is a single flux quantum (SFQ) logic which utilizes an SFQ as an information bit carrier. The single-bit adder circuit is made up of an INHIBIT gate which is the basic device of the phase-mode logic. The circuit has been designed and fabricated using Nb/AlO/sub x//Nb Josephson junctions with Josephson critical current density of 1.0 kA/cm/sup 2/. In order to confirm the circuit operation, the fabricated adder circuit has been tested at low speed. For investigating the possibility of a high-frequency operation, dc voltages generated by fluxon pulse trains have been measured. From the Josephson voltage-frequency relation, the result shows that the circuit has potential to complete the carry operation within 20 psec. [ABSTRACT FROM PUBLISHER]

We have designed, fabricated and successfully tested three SFQ elements: a toggle flip-flop, a SFQ voltage amplifier, and an RS-flip-flop. The design uses a single superconducting layer and it is optimized by repeated computer simulations and repeated inductance calculations. The inductances are made as narrow slits of 0.5 /spl mu/m width. Their values are calculated numerically taking into account material parameters derived from experiment. The YBCO junctions are either of step edge type on LaAlO/sub 3/ substrates or located on two closely spaced bi-crystal grain boundaries on a novel YSZ tricrystal substrate. Carbon masks were used to form steps on LaAlO/sub 3/ substrates and for the YBCO patterning. Voltage amplifier shows operation up to 60 K, and both flip-flops were observed to operate at temperatures up to 30 K with parameters close to the simulated values. The operation frequency of a T-flip-flop cell of about 150 GHz was achieved and a new measurement technique of the margins of an RS trigger is suggested. [ABSTRACT FROM PUBLISHER]

As the integration level of superconducting digital circuits increases, flux trapping in these devices becomes a serious problem. High resolution A/D converters and other high speed signal processing systems have been demonstrated with junction counts well into the 10/sup 3/ range. Such large circuits require special testing techniques to prevent flux trapping within the gates, which can reduce bias margins and cause malfunctions of these devices. We discuss the results of experiments using single flux quantum shift registers in which we have varied the ground plane hole pattern and magnetic shield degaussing procedure to minimize flux trapping in these circuits. The operating bias margins of the shift registers have been measured as a function of different testing procedures and ground plane hole designs. In situ degaussing of the magnetic shields aids in the reduction of flux trapping and gave the best results. Measurements of the permeability of mu metal at 4.2 K are discussed. [ABSTRACT FROM PUBLISHER]

We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date. [ABSTRACT FROM PUBLISHER]

Circuit level simulation is too slow to be used for verification of function and timing of large RSFQ circuits. The alternative, known from semiconductor digital circuit design, is simulating at the logic (gate) instead of the circuit (transistor or junction) level. Using a hardware description language (HDL) such as Verilog, it is possible to write functional model of each of the RSFQ basic gates. A large RSFQ circuit composed of hundreds gates and thousands Josephson junctions can then be simulated using standard semiconductor industry CAD tools. We have developed a library of Verilog models for over 15 basic RSFQ gates. We describe in detail our model for the DRO RSFQ cell. We show how this model can be generalized for other more complex cells. Our library has been verified by employing it in the design of timing for three large RSFQ circuits. [ABSTRACT FROM PUBLISHER]

A 12 bit Flux Shuttle shift register with a new write and readout gate has been simulated and fabricated using Nb/Al/sub 2/O/sub 3//Nb Josephson junctions. Write, shift and read operations have been tested successfully at 4.2 K. Drive currents are independent from input bit sequence. Although measurements were disturbed by trapped flux, minimum margins are /spl Delta/I=/spl plusmn/10%. The power dissipation of a shift register cell is 9 nW/GHz. Total power losses caused by terminating resistors are 70 /spl mu/W. The minimum line width may be scaled down to 0.5 /spl mu/m, because power losses per unit area of long Flux Shuttle shift registers are extremely low. [ABSTRACT FROM PUBLISHER]

A novel Josephson ternary logic circuit to perform multiplication is proposed. The fundamental circuit of the multiplier is based on Josephson complementary ternary logic circuit (JCTL). In this paper the principle of the ternary multiplier is described. We have fabricated the multiplier using SQUIDs which were made of Nb/AlOx/Al/Nb junctions, and measurements of the logic operation of the circuit were carried out. The results showed satisfactory operation of the multiplier, which agreed well with the results of simulation. The advantages of the proposed ternary multiplier are capability of ultra-high speed computation, low power consumption and very simple construction with less number of elements to perform a ternary multiplication. [ABSTRACT FROM PUBLISHER]

A crossbar switch has been designed using Single Flux Quantum (SFQ) gates exclusively for all internal functions. A 4/spl times/4 prototype has been fabricated in our Nb process foundry with J/sub c/ of 2000 A/cm/sup 2/. We report on the design and performance of the switch and of an individual crosspoint element at high data rates (/spl ges/1 Gbps). A novel design of a double-edge-triggered dc/SFQ converter is discussed. The requirements for output amplification and on-chip versus off-chip amplifier issues will be presented. [ABSTRACT FROM PUBLISHER]

We have investigated the applicability of Single Flux Quantum (SFQ) and Multiple Flux Quanta (MFQ) approaches to communications between RSFQ logic/memory chips. SFQ pulses can be transmitted between chips if inductive discontinuity L lies below 3-5 pH. For larger L one can employ MFQ pulses which have the same width as the SFQ pulses, but M times larger amplitude. For example, for L=20 pH, M=4 is sufficient. We have developed an MFQ driver and a receiver capable of transmitting the data in 10-20 Gbps/pin range for the use in simple flip-chip MCM packages based on Si substrates. [ABSTRACT FROM PUBLISHER]

The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed implementation of residue number system arithmetic. It is surprising that the successful recurrent operation of such a shift register has never been reported m the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits-the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, latencies and areas. These designs differ in the topology of the clock distribution network as well as the type of storage element employed in the data path. Two designs show satisfactory parameter margins and large maximum clock frequency. [ABSTRACT FROM PUBLISHER]

Vertical c-axis microbridges, with dimensions comparable to the penetration depth (/spl lambda//sub c/), have been investigated experimentally and theoretically. Josephson-like effects are observed due to coherent motion of vortices across the bridge. Both the on-chip and chip to chip reproducibility has been improved from previous reports by process optimisation. Within an array it is highly dependent on the oxygenation state and the temperature of the sample. Although the spread in parameters within an array of standard junctions is almost good enough to fabricate many circuits of interest, the I/sub c/ is too high and the R/sub n/ too low for many logic applications. In an attempt to reduce the coupling strength, the growth temperature of a region of the material in the microbridge has been varied. Initial results suggest I/sub c/ can be reduced and R/sub n/ increased to a level which, with further optimisation, might be useful for logic applications, while the reproducibility was not adversely affected. [ABSTRACT FROM PUBLISHER]

Development of a reliable flipped chip mounting technique enables demonstration of high speed, complex digital circuits. Flip chip mounting has greatly reduced parasitic inductance compared to conventional wire bonding, and permits remounting of known good die onto multi-chip modules. Superconductive digital circuits have operated to 4.3 Gb/s in our custom test station. The circuit and carrier are fabricated using TRW's foundry process. The chips are flipped onto a superconducting coplanar carrier using a low temperature solder reflow process reported on at this conference. Testing is performed in a multi-GHz, flip contact, variable temperature probe. This test facility is capable of testing circuits to 12 Gb/s. We will describe the operation and performance of our circuits at high bit rates, and design improvements intended to facilitate operation at higher bit rates with improved yield. In addition, we will discuss the use of a logic simulation tool to analyze the output words, and pinpoint the gate or gates that failed to operate properly. [ABSTRACT FROM PUBLISHER]

The first version of PSCAN program (Personal Superconductor Circuit ANalyzer) was introduced in 1991. The program is a general purpose superconductor circuit simulator with an emphasis on the design of Rapid Single-Flux-Quantum (RSFQ) circuits. In the intervening years a number of new features were gradually added to the program. In particular, verification of the correct circuit behavior was enhanced using a special hierarchical Single-Flux-Quantum Hardware Description Language (SFQHDL). Next, a fast heuristic algorithm for margin optimization was introduced, which increased the number of parameters that can be simultaneously optimized in reasonable CPU times. Finally, recently we improved the numerical algorithm used for the simulation by using sparse symmetric positive definite matrices (instead of general structure band matrices as before). As a result, simulation speed has increased almost tenfold. Now it takes about 30 seconds of a CPU time on HP716/100 workstation to run a 2000 ps simulation of a 120-Josephson-junction circuit, and about a week to optimize all parameters of a two hundred Josephson junction circuit. We have merged all these improvements in a new version of our simulator, PSCAN'96. [ABSTRACT FROM PUBLISHER]

We present a new design of a Rapid Single-Flux-Quantum (RSFQ) all-digital one-bit autocorrelator for submillimeter spectrometry applications, featuring 4 GHz input signal bandwidth, double oversampling quantizer, and 16 Mbps-per-channel output rate. The delay line of the autocorrelator is based on a circular shift register with XOR gates performing multiplication of the delayed and undelayed single-bit signals at every stage. The multiplication results are accumulated by room-temperature electronics after being prescaled in on-chip binary counters consisting of 10 T flip-flops per stage. We report results of experimental testing of a 16-stage autocorrelator delay line with multiplication and for a linear array of 8 low-power T flip-flop binary counters, all fabricated in HYPRES' standard 3.5 /spl mu/m 1000 A/cm/sup 2/ Nb-trilayer process. We also discuss physical and technical limits of the minimal power dissipation in RSFQ circuits. [ABSTRACT FROM PUBLISHER]

We present a revised version of our previous RSFQ (Rapid Single Flux Quantum) microprocessor architecture and discuss approaches that we are using in the design of its functional units. In particular, the data processing pipeline built of D/sup 2/ cells, a 16-bit pipelined register block and an all-RSFQ self-reset decoder suitable for pipelined implementation are described in detail. Methods of VHDL description and verification of RSFQ circuitry are also discussed. [ABSTRACT FROM PUBLISHER]

Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated. The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase. Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transfer-ring data from a flow-clocked circuit to a parallel dual-rail circuit is also proposed, which a fully asynchronous dual-rail demultiplexer. [ABSTRACT FROM PUBLISHER]

A new SFQ data communication switch has been designed and tested. Complete operation of a 4/spl times/4 switch circuit has been demonstrated with address decoding at low-speed. Transmission through a given path in the switch has been demonstrated for data rates up to 4 Gb/s. Circuit simulations show operation of the switch cells up to 30 Gb/s. The circuit was fabricated using HYPRES's standard 1 kA/cm/sup 2/ niobium process. The switch has a crossbar architecture with an RF SQUID based switch cell at each crosspoint. The address is decoded by means of RSFQ shift registers which are integrated into the switch matrix. The design enables high bit-rate, low crosstalk, non-blocking architecture, NRZ or RZ data format, and self routing of variable length data packets. [ABSTRACT FROM PUBLISHER]

We compare the SQUID wheel/Quantum Flux Parametron (QFP) comparator to a new Rapid Single Flux Quantum (RSFQ) compatible design. Both have been simulated to demonstrate /spl sim/0.5 ps threshold accuracy which would permit the construction of a flash analog-to-digital converter with six effective bits of resolution at 10 GHz input bandwidth, over three times better than the best performance demonstrated with any technology, At lower input frequencies, both designs have demonstrated that a 10-bit flash ADC is possible. Although simulations of the QFP-based design are more accurate at high signal slew rates due to its symmetry, the RSFQ-based design has a better signal-to-noise ratio and a faster and more flexible clocking scheme which ultimately prove to be more important. [ABSTRACT FROM PUBLISHER]

We have proposed a new type of voltage-state logic called Complementary Output Switching Logic (COSL). The COSL circuits were optimized for 5-10 GHz operation using a Monte Carlo method. Here we present experimental test results of the basic COSL gates in the frequency range 1-10 GHz, and discuss bit error rate measurements at 2-5 Gb/s. [ABSTRACT FROM PUBLISHER]

A 4 bit 15 sequence SFQ (Single Flux Quantum) pseudorandom bit sequence generator was built with an eight-level Nb/AlO/sub x//Nb Josephson junction integrated circuit process. An SFQ circuit was built into the code generator to enable a rapid restart. The test results showed that the circuit operated correctly at the seed of 3.69 GHz. The XNOR gate and shift register worked correctly at 5 GHz. However, the back delay was longer than 200 psec and the generator acted as a 5 bit 21 sequence code generator at this frequency. At 200 MHz, the code generator was operated continuously to observe its stability. Over the course of two and one half hours, the circuit made only five code errors, indicating a bit error rate of 3/spl times/10/sup -12/. At 2 GHz we collected 10 million samples on the 4023rd bit of the sequence. No wrong signal values were observed, indicating the bit error rate is less than 5/spl times/10/sup -11/ at this frequency. [ABSTRACT FROM PUBLISHER]

For the first time, the bit-error rate of an active SFQ experiment is compared to theoretical prediction. The theory of thermally induced errors is developed using the Fokker-Planck equation. The equivalent noise temperature of the experiment is found to be 11.0 K. The error rate vs. bias current follows an error function dependence and extrapolates to vanishingly small error rate at optimal bias. [ABSTRACT FROM PUBLISHER]

We have developed and verified experimentally a novel high-resolution superconducting ADC architecture based on phase modulation/demodulation principle and implemented in RSFQ logic. We have demonstrated an ADC chip providing full implementation of this architecture, including on-chip decimation filter and multiple-channel synchronizer. We have also developed a digital ADC evaluation system consisting of an interface electronics block converting the low-voltage ADC output to standard TTL form at multi-MHz sampling rate, and a computerized test station performing data acquisition, processing and display in real time. Using this system we have demonstrated that for low-frequency (kHz) signals our ADC chips possess linearity in excess of 16 bits with Spur-Free Dynamic Range over 108 dB, which is an important benchmark for any high-resolution ADC technology. [ABSTRACT FROM PUBLISHER]

Interface circuits for the transfer of data between Single Flux Quantum (SPQ) circuits have been designed, fabricated, and operated at speeds up to 3 Gigabits per second. The circuit employed an improved version of the SFQ/Latch converter, a Modified Variable Threshold Logic (MVTL) OR/AND gate, a 3/spl times/ latching amplifier, and a 3/spl times/-to-10/spl times/ latching amplifier. The amplifier circuits employed stacks of latching junctions. Resistors between the parallel stacks of junctions damped residual currents to prevent flux trapping during reset. Tolerance to critical current variations in the series stacks of junctions was provided by inductive chokes on the input junction shunting resistors. Microwave modeling programs were used to ensure proper distribution of the applied current to all of the latching elements. The circuit transferred data at 3 Gigabits per second from one SFQ circuit up to room temperature and back to another SFQ circuit through 3.4 meters of 50-ohm cable. [ABSTRACT FROM PUBLISHER]

The critical current of long, asymmetric Josephson junctions, I/sub c/, is highly dependent on the applied magnetic field and the geometry. Nearby currents are able to significantly modulate I/sub c/, leading to many possible devices. We have fabricated asymmetric long junctions (1-32 /spl mu/m) in YBCO thin films deposited on SrTiO/sub 3/ bicrystals that show improved sensitivity to control fields compared with symmetrically biased structures. The effect of the size and shape of the structures has been investigated in order to optimise the gain and critical current. We have compared our results to simulations. [ABSTRACT FROM PUBLISHER]

Josephson latching logic gates require an ac power supply for correct operation. Owing to the difficulty in fabricating Josephson regulators for large power currents, multi-phase sinusoidal power supply is the preferred method for multi-gigahertz operation. However, the inherently variable ac power reduces device margin for covering process variations. As a result, there exists a strong relationship between circuit size, maximum operating frequency and circuit throughput for a given available margin. The trade-offs between these performance criteria are analyzed for 3-junction-interferometer-based logic gates. Experimental evaluation of the multi-gigahertz operation of small circuits showed that careful design of power supply networks that reduce power supply fluctuations will be needed to maximize performance. Simulation and experimental results are discussed. [ABSTRACT FROM PUBLISHER]

We have designed and measured single flux quantum (SFQ) circuits for data switching at 2.5 Gbps. A fully functional 2/spl times/2 switching node is presented. The node can be used to form a larger switching fabric (4/spl times/4, 8/spl times/8, etc.). The node accepts data streams at either or both inputs, routing the data based on address bits present in the data stream. This approach allows the data to be self-routing and the switch to be self-synchronous. In addition, the switch can route data correctly on an active input line if the other is idle. [ABSTRACT FROM PUBLISHER]

A single-rail Modified Variable Threshold Logic (MVTL) decimation filter is designed by employing a novel XOR gate, which overcomes the difficulty of the lack of a good inverter in the MVTL logic family. A 10-bit deep-pipelined decimation filter consisting of about 700 junctions in a 5 mm/spl times/5 mm chip with power consumption of 0.4 mW is designed. [ABSTRACT FROM PUBLISHER]

We report on a voltage-state logic family based on shunted Josephson junctions and on the Rapid Single Flux Quantum (RSFQ) concept. Storing information in a voltage-state form makes this Multi-Flux-Quantum Logic (MFQL) easier to match to complementary metal-oxide semiconductor (CMOS) circuits. The switching of MFQL element between the voltage and zero-voltage states takes a minimum of two SFQ pulses, and the switching time of this logic is comparable to that of RSFQ logic. The key logic element is an inverter in the form of an asymmetric interferometer, and the underlying idea is to use a separate superconducting wire to supply a standard dc output voltage for the elements. The asymmetric interferometer, directly coupled to the other elements, is actually a Josephson junction based three-terminal device or transistor. Elements such as NOT, OR, NOR, XOR, XNOR, a toggle flip-flop, and an RS trigger have been simulated, and show margins better than /spl plusmn/24%. The performance of this logic with current circuit fabrication technologies is also discussed. [ABSTRACT FROM PUBLISHER]

The paper describes the architecture of a contention solver (CS) to be used in a superconducting packet switch prototype, and the design and tests of 2/spl times/2 switching elements which compose the CS. The contention solver is based on a Batcher sorter, in which switching elements check for contention between input packets. A priority port is used to guarantee correct operation of the sorter even if a packet is invalidated during the sorting process. A 2/spl times/2 CS switching element with 2-bit data-width was designed in dual-rail logic. It was fabricated using three-junction SQUID gates by a standard Nb tri-layer process, and consists of 102 OR-equivalent gates in an area of 1.2 mm x 1.8 mm. Its correct operation was confirmed completely. [ABSTRACT FROM PUBLISHER]

Communications transmitters, receivers, radar applications, and related test equipment require precise control over generated frequencies which can be provided by digital synthesis. Superconductivity technology offers to greatly improve the operational frequency range at a tiny fraction of the power of present GaAs and Si digital frequency synthesizers, an important consideration for systems with multiple receiver elements and satellite applications. We designed, fabricated, and tested a digital superconducting frequency synthesizer on a 1-cm square substrate in niobium technology and tested at 4 Kelvin. The chip contains a 12-bit pipelined MVTL incremental phase accumulator (simple expansion to 32 bits achieves one part in 4.3/spl times/10/sup 9/ frequency resolution). The most significant 10-bits of the accumulated phase proceed to a Sine ROM which is based on SQUID cells and employs data compression to minimize circuit size. An 8-bit ROM output word proceeds to a superconducting D/A converter to construct the analog output waveform which updates each clock cycle. We have operated the entire superconducting synthesizer above 1 GHz. Our performance goal with present fabrication technology is /spl ges/4 GHz operation. [ABSTRACT FROM PUBLISHER]

Many applications of Single-Flux-Quantum (SFQ) circuits will rely on the transfer of multi-Gigabit per second data streams from SFQ logic to semiconductor logic for further processing. The low output voltages of superconducting circuits currently limit the data rate per channel to a few GHz. We have designed and fabricated an SFQ demultiplexer to reduce data transfer clock rates. The demultiplexer uses clocked data distribution through a binary tree architecture. The circuit was fabricated using an eight level Nb/AlO/sub x//Nb process and tested at 4.2 K. [ABSTRACT FROM PUBLISHER]