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Highlights • Copper pillars are imaged using 6 different 3D imaging techniques. • 3rd generation synchrotron beamlines and lab equipments are assessed. • A new sample preparation for synchrotron tomography is successfully tested. • The final volumes are compared, based on image quality and analysis time. Abstract In microelectronics, recently developed 3D integration offers the possibility to stack the dice or wafers vertically instead of putting their different parts next to one another, in order to save space. As this method becomes of greater interest, the need for 3D imaging techniques becomes higher. We here report a study about different 3D characterization techniques applied to copper pillars, which are used to stack different dice together. Destructive techniques such as FIB/SEM, FIB/FIB, and PFIB/PFIB slice and view protocols have been assessed, as well as non-destructive ones, such as laboratory-based and synchrotron-based computed tomographies. A comparison of those techniques in the specific case of copper pillars is given, taking into account the constraints linked to the microelectronics industry, mainly concerning resolution and sample throughput. Laboratory-based imaging techniques are shown to be relevant in the case of punctual analyses, while synchrotron based tomographies offer highly resolved volumes for larger batches of samples. [ABSTRACT FROM AUTHOR]

3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connected NoCs, in which only a few vertical TSV links are available, have been gaining relevance. To reliably route packets under such conditions, we introduce a lightweight, efficient and highly resilient adaptive routing algorithm targeting partially vertically connected 3D-NoCs named First-Last. It requires a very low number of virtual channels (VCs) to achieve deadlock-freedom (2 VCs in the East and North directions and 1 VC in all other directions), and guarantees packet delivery as long as one healthy TSV connecting all layers is available anywhere in the network. An improved version of our algorithm, named Enhanced-First-Last is also introduced and shown to dramatically improve performance under low TSV availability while still using less virtual channels than state-of-the-art algorithms. A comprehensive evaluation of the cost and performance of our algorithms is performed to demonstrate their merits with respects to existing solutions. [ABSTRACT FROM AUTHOR]

A new vertical field-effect transistor (FET) has been fabricated inside a through silicon VIA (TSV). Front side and backside of a 200- $\mu \text{m}$ -thin p-doped Si wafer were highly n-doped to shape the source/drain areas of the FET. The lateral surface of the TSV forms the channel with a length of $200~\mu \text{m}$ (wafer thickness) and a width of $63~\mu \text{m}$ (circumference of the 20- $\mu \text{m}$ hole). A stack of SiO2 and Al2O3 was used as gate dielectric material and Ru/TaN/Ru was deposited as gate metal using atomic layer deposition. The n-channel TSVFETs showed saturation currents of 150 $\mu \text{A}$ for a gate voltage of 4 V and an ON/OFF current ratio of about 104. [ABSTRACT FROM AUTHOR]

Three dimensional Networks-on-Chip (3D NoCs) have evolved as an ideal solution to the communication demands and complexity of future high density many core architectures. However, the design practicality of 3D NoCs faces several challenges such as thermal issues, high power consumption and area overhead of 3D routers as well as high complexity and cost of vertical link implementation. To mitigate the performance and manufacturing cost of 3D NoCs, inhomogeneous architectures have emerged to combine 2D and 3D routers in 3D NoCs producing lower area and energy consumption while maintaining the performance of homogeneous 3D NoCs. Due to the limited number of vertical links, application mapping on inhomogeneous 3D NoCs can be complex. However, application mapping has a great impact on the performance and energy consumption of NoCs. This paper presents an energy and performance aware application mapping algorithm for inhomogeneous 3D NoCs. The algorithm has been evaluated with various realistic traffic patterns and compared with existing mapping algorithms. Experimental results show NoCs mapped with the proposed algorithm have lower energy consumption and significant reduction in packet delays compared to the existing algorithms and comparable average packet latency with Branch-and-Bound. [ABSTRACT FROM AUTHOR]

Cu-SiO 2 direct hybrid bonding is considered as one of the key enabling technologies for 3D integration. Previous studies showed that the main process parameters influencing the bonding quality are temperature and annealing time, as well as the mechanical stress at the Cu-Cu interface. The latter is influenced by thermo-mechanical stress introduced by the coefficient of thermal expansion mismatch of SiO 2 and Cu and by geometrical effects. The modeling approach of the present study aims to shed light on the influence of surface roughness on the contact area formation between Cu pads. Roughness profiles measured with atomic-force microscopy are directly used as input for the simulation. This introduces considerable computational effort when explicitly modeled within finite element simulation. A sub-modeling technique is used to reduce the numerical cost. The common 2D modeling approach is critically compared to full 3D modeling of the surface topography. The dominant micro-mechanical temperature dependent deformation mechanisms are taken into account by continuum mechanics material models from literature. Accordingly, the stress driven instantaneous dislocation glide and the diffusion triggered climb assisted dislocation glide are taken into account by corresponding plasticity and creep material models. [ABSTRACT FROM AUTHOR]

This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual I D -V DS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage V TH and low supply voltage V DD . [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper, a stacked 3D-technology is proposed to integrate the high voltage (HV) cLDMOS with the low voltage (LV) CMOS using TSV. The impact of the (0.0/42.0 V) HV signal of the future automotive applications on the performance of the LV CMOS inverter, implemented on the standard 0.35 μm BiCMOS technology, is investigated. This impact is performed utilizing a mixed mode simulation by using an equivalent SPICE models for the CMOS devices and finite element method (FEM) for the bulk regions. The CMOS output current is taken as an indicator for the substrate perturbations due to the switching of the applied signals. It is demonstrated that the influence of the HV on the performance of the CMOS signal is dependent on the location of the TSV. This effect can be minimized by adding a P + guard-ring between the pMOS device and the TSV using the same mask of the nMOS P-WELL active area. [ABSTRACT FROM AUTHOR]

An electronic integrated circuit (EIC) and a silicon photonic integrated circuit (PIC) are 3D-integrated. The EIC using the complementary metal–oxide–semiconductor (CMOS) part of STMicroelectronics’ BCD8sp 0.16 μm technology controls all 768 switches in the PIC individually and monitors them with 84 transimpedance amplifiers. A scalable analog–digital approach with a cell size of 100 × 100 μm2 for thermal control of optical ring resonator switch matrices is introduced. An electrical power consumption of 220 mW for all electronic control circuits of the optical switch matrix is resulting in 5.5% of the power needed by a constant-voltage control approach. [ABSTRACT FROM AUTHOR]

Through-silicon-via (TSV) interposer has been proved to be a good solution for three-dimensional integration to achieve high density and improved performance. In this paper, a novel double-sides silicon interposer structure with deep trenches was proposed to achieve high density 3-D hetero-integration. The TSVs in the interposer were fabricated by wet etching method on both sides, which has low cost, good reliability and suitable for batch production. In order to minimize the TSV size and provide a higher interconnect density as well as retain the mechanical reliabilities of the interposer, deep trenches were wet-etched before TSV fabrication, which were also used for chip embedding. To further increase the integration density, multiple interconnects were attempted to be deposited in a single TSV and their electrical properties were systematically characterized. [ABSTRACT FROM AUTHOR]

Single-Photon Avalanche Diodes (SPADs) are p–n junctions operated in Geiger Mode by applying a reverse bias above the breakdown voltage. SPADs have the advantage of featuring single photon sensitivity with timing resolution in the picoseconds range. Nevertheless, their relatively high Dark Count Rate (DCR) is a major issue for charged particle detection, especially when it is much higher than the incoming particle rate. To tackle this issue, we have developed a 3D Silicon Coincidence Avalanche Detector (3D-SiCAD). This novel device implements two vertically aligned SPADs featuring on-chip electronics for the detection of coincident avalanche events occurring on both SPADs. Such a coincidence detection mode allows an efficient discrimination of events related to an incoming charged particle (producing a quasi-simultaneous activation of both SPADs) from dark counts occurring independently on each SPAD. A 3D-SiCAD detector prototype has been fabricated in CMOS technology adopting a 3D flip-chip integration technique, and the main results of its characterization are reported in this work. The particle detection efficiency and noise rejection capability for this novel device have been evaluated by means of a β − strontium-90 radioactive source. Moreover the impact of the main operating parameters (i.e. the hold-off time, the coincidence window duration, the SPAD excess bias voltage) over the particle detection efficiency has been studied. Measurements have been performed with different β − particles rates and show that a 3D-SiCAD device outperforms single SPAD detectors: the former is indeed capable to detect particle rates much lower than the individual DCR observed in a single SPAD-based detectors (i.e. 2 to 3 orders of magnitudes lower). [ABSTRACT FROM AUTHOR]

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. [ABSTRACT FROM AUTHOR]

Silver nanoparticles (Ag NPs) fabricated by physical vapor deposition (PVD) were introduced in Cu-Cu bonding as surface modification layer. The bonding structure consisted of a Ti adhesive/barrier layer and a Cu substrate layer was fabricated on the silicon wafer. Ag NPs were deposited on the Cu surface by magnetron sputtering in a high-pressure environment and a loose structure with NPs was obtained. Shear tests were performed after bonding, and the influences of PVD pressure, bonding pressure, bonding temperature and annealing time on shear strength were assessed. Cu-Cu bonding with Ag NPs was accomplished at 200°C for 3 min under the pressure of 30 MPa without a post-annealing process, and the average bonding strength of 13.99 MPa was reached. According to cross-sectional observations, a void-free bonding interface with an Ag film thickness of around 20 nm was achieved. These results demonstrated that a reliable low-temperature short-time Cu-Cu bonding was realized by the sintering process of Ag NPs between the bonding pairs, which indicated that this bonding method could be a potential candidate for future ultra-fine pitch 3D integration. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents 3D‐integrated and multifunctional all‐soft physical microsystems, which are composed of a soft sensor, a soft interconnector, and a soft readout circuit. The microsystems utilize gallium‐based liquid metal (eutectic gallium‐indium alloy, EGaIn) and poly(dimethylsiloxane) (PDMS) and are fabricated using an advanced EGaIn thin‐line patterning technique based on soft lithography. Combining the scalable fabrication process and a vertical integration approach using EGaIn‐filled soft vias, two types of all‐soft physical microsystems are investigated using analytical, numerical, and experimental approaches and demonstrated to highlight high‐density integration, multifunctional sensing capability, as well as system‐level flexibility and stretchability: (i) a finger‐mountable strain sensing microsystem with reduced temperature sensitivity and (ii) a fingertip microsystem for simultaneous proximity, touch, and pressure sensing. The demonstrated fabrication and integration approaches provide a path towards all‐soft and highly integrated wearable physical microsystems for human‐machine interfaces, soft robotics, and healthcare applications. [ABSTRACT FROM AUTHOR]

True-time-delay devices could significantly contribute to improving the performance of many optical systems in applications such as sensing, ranging, communication and signal processing. Delay devices based on spiral optical waveguides are of special interest due to their small size and relatively low power attenuation. In this paper, we propose to fabricate spirals on both sides of a wafer, where the coupling between them is through a vertical interconnect. The novel through-wafer interconnect has a level of attenuation that compares competitively with that obtained with a conventional s-shaped interconnect between two interleaved spirals and considerably simplifies the waveguide design and fabrication. [ABSTRACT FROM PUBLISHER]

• Impact of 3D integration on the wafer backside on the DC and low-frequency noise of p-channel FinFETs. • Post-bonding annealing consisting of high-pressure and forming gas annealing yields improved gate oxide quality, testified by the lower flicker noise power spectral density. This paper compares the low-frequency noise performance of backside integrated pFinFETs versus their regular frontside-only processed counterparts. We report that no degradation of the dominant flicker noise is observed, comparing front- versus backside processed transistors. At the same time, application of a post backside processing annealing step(s) is shown to enable an improvement of the DC input characteristics and the low-frequency noise power spectral density of the devices. [ABSTRACT FROM AUTHOR]

The mechanical reliability of the future miniaturized interconnects is mainly governed by the intermetallic compounds such as Cu 6 Sn 5. Alloyed Cu 6 Sn 5 with various elements, including Co and In, have been introduced and attracted attention for different reasons, such as the enhancing mechanical reliability and lowering the bonding temperature. Hence, this work aimed to evaluate the microstructural and mechanical properties of Cu 6 Sn 5 -, Cu 6 (Sn,In) 5 -, (Cu,Co) 6 Sn 5 -, and (Cu,Co) 6 (Sn,In) 5 -interconnects. The grain size, grain orientation, and crystal structure of the pure and alloyed Cu 6 Sn 5 phases were analyzed using electron backscatter diffraction. The results revealed that all the joints contained monoclinic and hexagonal crystal structures arbitrarily formed across the bond-line. Furthermore, the Cu 6 Sn 5 grains exhibited random grain orientation and there was no discernible difference between the pure and alloyed Cu 6 Sn 5 interconnects other than Cu 6 (Sn,In) 5 grains elongated along the perpendicular direction to the bonding interface. However, it was found that alloying elements altered the grain sizes. In alloying refined and elongated the Cu 6 Sn 5 grains while the Co alloying enlarged the Cu 6 Sn 5 grains. The mechanical properties of the interconnects were examined using nanoindentation test. The results indicated that the hardness (H) and Young's modulus (E i) values of Cu 6 Sn 5 is increased with the alloying elements. (Cu,Co) 6 (Sn,In) 5 showed the highest E i /H value which indicates its highest plasticity. [Display omitted] [ABSTRACT FROM AUTHOR]

In this work we showed the optimization of the spectral response of several optical elements in a silicon-based optical switch. Integrated thermal resistors induced a local heating of the components. The temperature increase, in turn, caused a thermal shift of the optical response of the component. In this manner, we aligned interleavers and micro-ring resonators to the International Telecommunication Union (ITU) channels, by using a stochastic method named Globalized Bounded Nelder-Mead (GBNM) to determine the proper temperatures. The optimization engine relied on the optical feedback from on-chip monitor photodiodes to drive these photonic elements into the wanted functioning condition. This method is suited for restoring the spectral response of optical elements impaired by fabrication inaccuracies. In the same way, it can be applied to tune in resonance active components, whose transfer function has one or more local optima. We proved the reliability of the GBNM method for the optimization of an integrated optical switch, with more than thousand optical components, each one interfaced with a thermal resistor driven by a dedicated electronic circuit. On the one hand, the GBNM guaranteed the automatic alignment of all active components on the chip, over multiple instances. On the other hand, the method allowed for the proper working of such a complex device.

Emerging non-volatile memory technologies are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. One of the most promising candidates is resistive random access memory (RRAM) based on resistive switching (RS). This paper reviews the development of RS device technology including the fundamental physics, material engineering, three-dimension (3D) integration, and bottom-up fabrication. The device operation, physical mechanisms for resistive switching, reliability metrics, and memory cell selector candidates are summarized from the recent advancement in both industry and academia. Options for 3D memory array architectures are presented for the mass storage application. Finally, the potential application of bottom-up fabrication approaches for effective manufacturing is introduced. [ABSTRACT FROM AUTHOR]

Integration of silicon nanowires (Si NWs) in three-dimensional (3D) devices including integrated circuits (ICs) and microelectromechanical systems (MEMS) leads to enhanced functionality and performance in diverse applications. The immediate challenge to the extensive use of Si NWs in modern electronic devices is their integration with the higher-order architecture. Topography-related limits of integrating Si NWs in the third dimension are addressed in this work. Utilizing a well-tuned combination of etching and protection processes, Si NWs are batch-produced in bulk Si with an extreme trench depth of 40 μm, the highest trench depth obtained in a monolithic fashion within the same Si crystal so far. The implications of the technique for the thick silicon-on-insulator (SOI) technology are investigated. The process is transferred to SOI wafers yielding Si NWs with a critical dimension of 100 nm along with a trench aspect ratio of 50. Electrical measurements verify the prospect of utilizing such suspended Si NWs spanning deep trenches as versatile active components in ICs and MEMS. Introducing a new monolithic approach to obtaining Si NWs and the surrounding higher-order architecture within the same SOI wafer, this work opens up new possibilities for modern sensors and power efficient ICs. [ABSTRACT FROM AUTHOR]

An identified reliability challenge of significant importance to Cu–Sn bonding for 3D integration is Cu–Sn intermetallic void formation. Voids, often referred to as Kirkendall voids, form within the inter-diffusional zone between Cu and Sn, more specifically within the intermetallic compound Cu 3 Sn. The root-cause(s) of void formation is not well understood, therefore this study is designed to understand under what conditions voids form. The two main hypotheses for the root-causes of void formation are (i) the imbalance of diffusion rates between Cu and Sn during the formation of Cu–Sn intermetallic compounds and the resulting residual stresses and (ii) the co-deposition of impurities during Cu electroplating to void formation. Therefore, an ex- and in-situ x-ray diffraction (XRD) study is used to probe the material state as a function of thermal annealing, and a time-of-flight mass spectroscopy (ToF-SIMS) study is used to detect impurities co-deposited during Cu electroplating and to understand the effects of thermal annealing on the impurities' kinetic behaviour. [ABSTRACT FROM AUTHOR]

Cu/adhesive hybrid bonding is an attractive approach to three-dimensional (3D) integration because it provides direct Cu Cu vertical interconnects and high mechanical stability. However, Cu/adhesive hybrid bonding at below 200 °C is still challenging because of bonding temperature mismatch between Cu Cu and polymer adhesives and lacking of effective adhesive-compatible Cu surface activation methods. In this paper, we investigate and demonstrate a “Cu-first” hybrid bonding technique by using hydrogen(H)-containing formic acid (HCOOH) vapor prebonding surface treatment for the first time. In this technique, high-quality Cu Cu bonding is obtained at 180–200 °C that is close to or even lower than the temperature of subsequent adhesive curing. We experimentally investigate the effects of the H-containing HCOOH vapor treatment for Cu Cu bonding and cyclo-olefin polymer adhesive–adhesive bonding. This technique enables Cu/adhesive hybrid bonding at below 200 °C, promising smaller thermal stress, higher throughput, and lower cost comparing to the existing “adhesive-first” hybrid bonding method. [ABSTRACT FROM AUTHOR]

Through silicon vias (TSVs) increase the interconnect bandwidth, reduce the RC delay and improve the power efficiency because the TSVs shorten vertical signal paths greatly. The process of via-reveal on the wafer backside is one of key steps for a successful implementation of 3D-IC stacking using the TSV technique, e.g. the via-first and via-middle TSV integrations. Instead of using a full chemical mechanical polish (CMP) or a dry etch process, we proposed a method of two-step full wet etching in this study. The solutions of HF/HNO 3 and tetramethyl ammonium hydroxide (TMAH) are used in the two steps, respectively. The second etching step is only necessary for the wafers with a large thickness variation. Based on the full wet etching mechanism of silicon, we designed experiments to obtain the satisfied etching rate, selectivity and etching profile with optimized parameters. Using the approach, the via-reveal process was conducted for wafers with different incoming remain silicon thickness (RST) profiles. The sample characterization manifest that the present full wet etching process is well-controlled, efficient and cost effective. [ABSTRACT FROM AUTHOR]

3D integration is a practical solution for overcoming the problems of long and slow global wires in current and future generations of integrated circuits. This emerging technology stacks several die slices on top of each other in a single chip. It provides higher-bandwidth and lower-latency in the third dimension than a 2D design due to extremely shorter inter-layer distances. However, thermal challenges are a key impediment to stacking logic dies on top of each other. Particularly, routers in a 3D network-on-chip (NoC) are a main source of thermal hotspots, limiting the potential performance gains of the 3D integration. In this paper, we take advantage of the low-latency 3D vertical links to design a temperature-aware router architecture for 3D NoCs. This architecture reduces the peak temperature of routers, particularly routers that are farther from the heat sink, by balancing the traffic across all layers in a temperature-aware distributed way. This way, a router with high temperature can borrow the link and crossbar bandwidth of the routers in the layers closer to the heat sink to forward its packets, effectively offloading part of its traffic to them to reduce its temperature. Experimental results show that the proposed method can control the temperature of 3D NoCs and reduce the temperature gradient across the network with minimized negative impact on performance, compared to a state-of-the-art 3D NoC temperature management method. [ABSTRACT FROM AUTHOR]

Copyright of Telecommunication Engineering is the property of Telecommunication Engineering and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copper direct bonding technology is considered to be one of the most promising approaches for matching the miniaturization needs in future tridimensional integrated high performance circuits (3D-IC). However, the bonding mechanism of copper surfaces with an initial dishing effect, induced by the polishing step, must be investigated in order to optimize the adhesion process and prevent further reliability issues. In this study, we present thermomechanical finite element simulations of Cu–SiO 2 hybrid bonding with account for the annealing step and various amplitudes of the initial dishing. A cohesive model that mimics nonlinear interactions between Cu/Cu and SiO 2 /SiO 2 interfaces and related bonding mechanism is implemented within a nonlinear contact mechanics strategy. The bonding process along with the influence of the annealing conditions and the copper plastic response on the closure of the Cu/Cu interface are investigated. [ABSTRACT FROM AUTHOR]

Wafer bonding methods with ultra-thin intermediate bonding layers are critically important in heterogeneous 3D integration technologies for many NEMS and photonic device applications. A promising wafer bonding approach for 3D integration is adhesive bonding. So far however, adhesive bonding processes relied on relatively thick intermediate adhesive layers. In this paper, we present an adhesive wafer bonding process using an ultra-thin intermediate adhesive layer with sub-200 nm thickness. We demonstrate adhesive bonding of silicon wafers with a near perfect bonding yield of >99% and achieve less than ±10% non-uniformity of the intermediate layer thickness across an entire 100 mm-diameter wafer. A bond strength of 4.8 MPa was measured for our polymer adhesive, which is considerably higher than previously reported for other ultra-thin film adhesives. Additionally, the adhesive polymer used in the proposed method features excellent chemical and mechanical stability. We also report on a potential strategy for mitigating the formation of micro-voids in the polymer adhesive at the bond interface. Furthermore, the polymer adhesive can be sacrificially removed by oxygen plasma etching for both isotropic and anisotropic release etching. The characteristics of the adhesive wafer bonding process and its compatibility with CMOS wafers, makes it very attractive for heterogeneous 3D integration processes targeted at CMOS-integrated NEMS and photonic devices. [ABSTRACT FROM AUTHOR]

3DICs with multiple tiers are expected to achieve large benefits (e.g., in terms of power, area) as compared to conventional planar designs. However, few if any previous works study upper bounds on power and area benefits from 3DIC integration with multiple tiers. In this work, we use the concept of implementation with infinite dimension to estimate upper bounds on power and area benefits achievable by 3DICs versus 2DICs. We observe that the maximum power benefit even with infinite dimension can be only 18% versus 2DIC for particular designs. Such benefits reduce further under assumptions of inter-tier variation. We confirm our observation by performing 3D benefit estimation across various technologies. Our study also indicates that it is typically difficult for pure logic-logic 3D integration to achieve a simultaneous (10%, 10%, 10%) improvement in (performance, power, area/cost) compared to the conventional 2D implementation. In addition, we study power of designs across various dimensions (e.g., pseudo-1D, 2D, 3D with two, three and four tiers). 1 1 In this paper, the pseudo-1D implementation indicates the design implementation with high aspect ratio layout. We observe that design power sensitivity to implementation with different dimensions correlates well with placement-based Rent parameter of the netlist. Therefore, placement-based Rent parameter can possibly be a simple indicator of 3D power benefit. Our study also shows that netlist synthesis and optimization should be aware of the target implementation dimension (e.g., 2D versus 3D). Finally, we use a simple example to show that there remain potential large 3DIC benefits versus 2DIC for (block-based) SoC designs. [ABSTRACT FROM AUTHOR]

Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5–2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in between grinding and dry etch it is possible to significantly reduce not only the roughness, but also the remaining vacancies at the subsurface. The surface of grinding + CMP + dry etching gives an equivalent mono vacancy result as to that of grinding + CMP. This combination of thinning processes allows development of extremely thin 3D integration devices with minimal roughness and vacancy surface. [ABSTRACT FROM AUTHOR]

A novel pretreatment of plasma combined self-assembled monolayer (PcSAM) was proposed to improve surface properties of electroplated Cu for low temperature Cu–Sn bonding in 3D integration. Measurement results revealed that self-assemble monolayer (SAM) would be easier absorbed on plasma-activated Cu surface and protect the clean surface from re-oxidation when storage. The absorbed SAM layer could be removed by thermal desorption during bonding process. With optimal PcSAM pretreatment, oxygen content of the Cu surface was reduced to as low as 1.39%. The followed Cu–Sn bonding was realized at low temperature of 200 °C. Finally, bonding interface exhibited a defect-free interconnection, and bonding strength has reached as high as 68.7 MPa. [ABSTRACT FROM AUTHOR]

Although the emerging 3D DRAM products can significantly improve the computing system performance, the relatively high cost is one of the most critical issues that prevent their wide real-life adoption. Intuitively, a strong memory fault tolerance can be leveraged to reduce the fabrication cost of DRAM dies, and the total cost will reduce if the fabrication cost saving can off-set the cost overhead of memory fault tolerance. Nevertheless, such a simple concept can be a practically viable option only for 3D DRAM because: (1) The stacked logic die can solely implement memory fault tolerance inside 3D DRAM chips, obviating any changes on the host CPUs and CPU-DRAM interfaces. (2) With the total ownership of both the logic die and DRAM dies inside 3D DRAM chips, DRAM manufacturers can fully exploit the potential to truly minimize the 3D DRAM bit cost. Following this intuition, we developed a 3D DRAM fault tolerance design strategy. It can achieve a very strong tolerance to weak DRAM cells at very small redundancy and latency overhead. The key is to cohesively leverage the detectability of weak cells and runtime configurability of error correction code (ECC) decoding. In addition, this design strategy can gracefully embrace the inaccuracy of weak cell detection (e.g., weak cell miss-detection and false-detection). We carried out thorough mathematical analysis, and the results show that, under the redundancy overhead of 1:8 (same as today’s ECC DIMM), this design strategy can tolerate the weak cell rate of as high as 10^-4 and 6 \times 10^-5 if 100 and 90 percent of all the weak cells are known in prior. Using Micron’s hybrid memory cube (HMC) 3D DRAM chips as the test vehicle, we evaluated the implementation cost and the results show that it only consumes less than 0.4 mm2 (45 nm node) on the logic die. Using CPU and DRAM simulators, we further carried out simulations over a variety of computing benchmarks and the results show that this design solution only incurs less than 2 percent performance degradation on average. [ABSTRACT FROM AUTHOR]

This paper concerns the study of a temporary bonding process: 3M TM Wafer Support System. This process is dedicated to the handling of thin silicon wafers with a glass carrier bonded with a UV curable polymer. The dismounting process is achieved after a laser treatment. Firstly, the 300 mm bonding process leads to a very homogeneous bonded structure without any bonding defects. The morphology of the bonded structure is mainly dependent of the morphology of the glass. Secondly this process is also compatible with a back – grinding process and the thinned silicon structure can be processed up to 250 °C. When using a blank silicon wafer, the 3M TM dismounting process (laser and peeling) leads to a silicon thin wafer without any cracks, chippings or adhesive traces. Finally the laser process can be removed from the debonding steps and a single mechanical dismounting process can be used. [ABSTRACT FROM AUTHOR]

This paper presents a novel fabrication method for vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT) arrays that are amenable to 3D integration. This paper demonstrates that MEMS structures can be directly built on a glass substrate with preformed through-glass-via (TGV) interconnects. The key feature of this new approach is the combination of copper through-glass interconnects with a vibrating silicon-plate structure suspended over a vacuum-sealed cavity by using anodic bonding. This method simplifies the overall fabrication process for CMUTs with through-wafer interconnects by eliminating the need for an insulating lining for vias or isolation trenches that are often employed for implementing through-wafer interconnects in silicon. Anodic bonding is a low-temperature bonding technique that tolerates high surface roughness. Fabrication of CMUTs on a glass substrate and use of copper-filled vias as interconnects reduce the parasitic interconnect capacitance and resistance, and improve device performance and reliability. A 16\boldsymbol \times 16 -element 2D CMUT array has been successfully fabricated. The fabricated device performs as the finite-element and equivalent circuit models predict. A TGV interconnect shows a 2- \boldsymbol \Omega parasitic resistance and a 20-fF shunt parasitic capacitance for 250- \mu \textm via pitch. A critical achievement presented in this paper is the sealing of the CMUT cavities in vacuum using a PECVD silicon nitride layer. By mechanically isolating the via structure from the active cells, vacuum sealing can be ensured even when hermetic sealing of the via is compromised. Vacuum sealing is confirmed by measuring the deflection of the edge-clamped thin plate of a CMUT cell under atmospheric pressure. The resonance frequency of an 8-cell 2D array element with 78- \mu \textm diameter circular cells and a 1.5- \mu \textm plate thickness is measured as 3.32 MHz at 15-V dc voltage (80% Vpull-in). [2016-0200] [ABSTRACT FROM PUBLISHER]

Bumpless interconnects and ultra-thinning of 300 mm wafers for three-dimensional stacking technology have been studied. In our previous work, thinning effects using device wafers < 10 μm thick were reported. No degradation occurred in the retention time even in a 4-μm-thick DRAM wafer. In this study, the behavior of Cu contamination on a < 3-μm-thick DRAM wafer was investigated. The wafer was thinned down by coarse (#320 grit size) grinding and fine (#2000 grit size) grinding. This thinning condition had 200-nm-thick ground damage remaining for the gettering effect. The DRAM wafer was intentionally contaminated with Cu on the damaged layer, and 250 °C-60 min of heating was carried out during adhesive bonding and de-bonding. Degradation in the device characteristics was found. However, the analytical results indicated that the Cu did not diffuse into the thin Si. Thus, a Cu contaminated blanket wafers having a damaged layer were prepared and annealed until 1000 °C-30 min. Secondary ion mass spectroscopy, transmission electron microscopy and positron annihilation spectroscopy were evaluated. The Cu was trapped in the vacancy-type defects of the 200 nm damaged layer until a 700 °C anneal. After an 800 °C anneal, the Cu was eliminated on the damaged surface because of the Si recrystallization. The gettering ability of the damaged layer is suitable for 3D multi-level stacking regarding thermal stability. [ABSTRACT FROM AUTHOR]

3D sequential integration, such as CoolCube™, allows to stack vertically layer of devices. Levels of interconnection, also called intermediate Back-End-Of-Line, are needed between successive layers of transistors to avoid routing congestion. Thus, thermal stability of the dielectrics must be studied in order to fulfil the CoolCube™ requirement: at least to be stable up to 500 °C during 2 h. Consequently, the stability of several barrier layers and oxide based materials has been studied through optical characterizations (ellipsometry, Fourier Transform InfraRed spectroscopy and ellipsometric–porosimetry). SiCO (k = 4.5), in replacement of standard SiCNH (k = 5.6) material as barrier layer seems very promising. Regarding the inter-layer dielectric stability, the state-of-the-art porous SiOCH (k = 2.5) stays suitable for a thermal budget of 500 °C, 2 h. [ABSTRACT FROM AUTHOR]

Progress in 3D interconnecting technologies paved the way for a new generation of Silicon Photomultipliers (SiPM) and Single Photon Avalanche Diode (SPAD): hybrid devices which combine the integrated functionalities of the digital SiPM with the high performance of custom technologies, like low noise and high detection efficiency. Recently, Fondazione Bruno Kessler (FBK) has been working on the implementation of recently developed 3D integration technologies, on SiPMs devices, to improve both performances and functionalities by creating backside-illuminated (BSI) devices and Through Silicon Vias (TSV) interconnections. Two different technology platforms have been investigated: a BSI design for near-infrared (NIR) sensitive SiPMs and TSV interconnections for near- and vacuum-ultraviolet (NUV/VUV) sensitive detectors. For NIR applications, electrical characterization of ultra-thin (about 10 μ m) SiPM wafers with a metal reflector on the frontside has shown an improved photon detection efficiency (PDE) when operated in BSI configuration compared with non-thinned front-side illuminated (FSI) devices, allowing at the same time full high-segmentation access to the SiPM output from the front-side. Instead, for NUV/VUV applications, a FSI stacked approach is considered more suitable since the junction depth needs to be shallower. In this case, TSV interconnections using two different approaches (named Via-Mid and Via-Last) have been implemented allowing the placement of the contacts on the backside of the wafer. • A first demonstrator of BSI SiPM for NIR light detection was developed at FBK. • SiPMs with thick epitaxial layer and metal reflector on top show the highest PDE. • Two fabrication process flows with TSV for VUV detection are proposed. • Via-Mid approach shows proper electrical isolation between the TSV and bulk-silicon. • TSV filling with a dielectric polymer has been demonstrated for Via-Last approach. [ABSTRACT FROM AUTHOR]