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1,237 results on '"Baek, Kwang-Hyun"'

143. A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS

Author

Jo, Yong-Jun, Kim, Ju Eon, Baek, Kwang-Hyun, Kim, Tony Tae-Hyoung, School of Electrical and Electronic Engineering, Chung-Ang University, and Centre for Integrated Circuits and Systems

Subjects
Electrical and electronic engineering::Integrated circuits [Engineering], Compute-in-Memory, SAR ADC
Abstract

A 0.007mm 2 0.6V 6MS/s 10b double rail-to-rail input range SAR ADC is implemented in 65-nm technology. The extended input range broadens the applications of the low-power SAR ADCs such as compute-in-memory. The proposed ADC occupies less area since it only needs additional two series-connected capacitors and a differential-difference comparator for double rail-to-rail operation. The set-and-down operation reduces the input-referred noise of the comparator by over ten times than complementary switching. The novel metal-insulator-metal and metal-oxide-metal capacitor hybrid cap-DAC architecture minimize the gain error of ADC. The prototype achieves SNR of 53.90-dB, SNDR of 52.12-dB, and SFDR of 60.39-dB, power of 12.98- μW, and FoM of 6.6-fJ/conv.-step.

Published
2021

144. A 3.2-GHz 178-fs rms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier.

Author

Yoon, Dong-Hyun, Jung, Dong-Kyu, Seong, Kiho, Han, Jae-Soub, Chung, Keun-Yong, Kim, Ju-Eon, Kim, Tony Tae-Hyoung, and Baek, Kwang-Hyun

Subjects
PHASE-locked loops, COMPLEMENTARY metal oxide semiconductors, PHASE noise, ELECTROSTATIC discharges, VOLTAGE-controlled oscillators
Abstract

This article proposes a 3.2-GHz subsampling phase-locked loop (SSPLL)-based injection-locked clock multiplier (ILCM) using a subsampling delay-locked loop (SSDLL). The proposed ILCM achieves a superior noise reduction effect at low offset frequency because of the high feedback gain of SSPLL. Also, SSDLL is proposed for background phase calibration between SSPLL and injection. Since SSPLL and SSDLL use identical SSCP, the power consumption of the frequency and phase calibration is only 1.32 mW. This work is fabricated in a 65-nm CMOS process, and the 10-kHz phase noise is improved by 8.6 dB. The rms jitter from 10 kHz to 30 MHz is 178 fs. The chip-to-chip variations (20 chips) are 17 and 169 fs with/without SSDLL, respectively. The measured results show that FoM1, FoM2, and total power consumption are −245.1, −260.1 dB, and 9.85 mW, respectively. [ABSTRACT FROM AUTHOR]

Published
2022
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