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143 results on '"Clermidy, Fabien"'

105. A 477mW NoC-based digital baseband for MIMO 4G SDR

Author

Clermidy, Fabien, primary, Bernard, Christian, additional, Lemaire, Romain, additional, Martin, Jerome, additional, Miro-Panades, Ivan, additional, Thonnart, Yvain, additional, Vivet, Pascal, additional, and Wehn, Norbert, additional

Published
2010
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124. A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip

Author

Lattard, Didier, primary, Beigne, Edith, additional, Bernard, Christian, additional, Bour, Catherine, additional, Clermidy, Fabien, additional, Durand, Yves, additional, Durupt, Jean, additional, Varreau, Didier, additional, Vivet, Pascal, additional, Penard, Pierre, additional, Bouttier, Arnaud, additional, and Berens, Friedbert, additional

Published
2007
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126. A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC.

Author

Helmstetter, Claude, Basset, Sylvain, Lemaire, Romain, Clermidy, Fabien, Vivet, Pascal, Langevin, Michel, Pilkington, Chuck, Paulin, Pierre, and Fuin, Didier

Abstract

As Systems-on-Chip size increase, the communication costs become critical and Networks-on-Chip (NoC) bring innovative solutions. Efficient stream-based protocols over NoC have been widely studied to address dataflow communications. They are usually controlled by a set of static parameters. However, new applications, such as high-resolution video decoders, present more data-dependent behaviors forcing communication protocols to support higher dynamicity. For this purpose, we present in this paper dynamic stream links for stream-based end-to-end NoC communications by introducing two link protocols, both independent of the transfer size, allowing to improve the hardware/software control flexibility. The proposed protocols have been modeled in a MPSoC virtual platform and the hardware cost evaluated. Based on simulations, we provide guidelines to exploit these protocols according to application needs. [ABSTRACT FROM PUBLISHER]

Published
2013
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128. Platform 2012, a Many-Core Computing Accelerator for Embedded SoCs: Performance Evaluation of Visual Analytics Applications.

Author

Melpignano, Diego, Benini, Luca, Flamand, Eric, Jego, Bruno, Lepley, Thierry, Haugou, Germain, Clermidy, Fabien, and Dutoit, Denis

Subjects
NETWORKS on a chip, SYSTEMS on a chip, FEATURE extraction, VISUAL analytics, COMPUTER vision, COMPLEMENTARY metal oxide semiconductor design & construction, SIMULTANEOUS multithreading processors
Abstract

P2012 is an area- and power-efficient many-core computing accelerator based on multiple globally asynchronous, locally synchronous processor clusters. Each cluster features up to 16 processors with independent instruction streams sharing a multibanked one-cycle access L1 data memory, a multi-channel DMA engine and specialized hardware for synchronization and aggressive power management. P2012 is 3D stacking ready and can be customized to achieve extreme area and energy efficiency by adding domain-specific HW IPs to the cluster. The first P2012 SoC prototype in 28nm CMOS will sample in Q3, featuring four 16-processor clusters, a 1MB L2 memory and delivering 80GOPS (with 32 bit single precision floating point support) in 18mm2 with 2W power consumption (worst-case). P2012 can run standard OpenCLTM and proprietary Native Programming Model SW components to achieve the highest level of control on applicationto- resource mapping. A dedicated version of the OpenCV vision library is provided in the P2012 SW Development Kit to enable visual analytics acceleration. This paper will discuss preliminary performance measurements of common feature extraction and tracking algorithms, parallelized on P2012, versus sequential execution on ARM CPUs. [ABSTRACT FROM AUTHOR]

Published
2012

129. Platform 2012, a many-core computing accelerator for embedded SoCs.

Author

Melpignano, Diego, Benini, Luca, Flamand, Eric, Jego, Bruno, Lepley, Thierry, Haugou, Germain, Clermidy, Fabien, and Dutoit, Denis

Abstract

P2012 is an area- and power-efficient many-core computing accelerator based on multiple globally asynchronous, locally synchronous processor clusters. Each cluster features up to 16 processors with independent instruction streams sharing a multi-banked one-cycle access L1 data memory, a multi-channel DMA engine and specialized hardware for synchronization and aggressive power management. P2012 is 3D stacking ready and can be customized to achieve extreme area and energy efficiency by adding domain-specific HW IPs to the cluster. The first P2012 SoC prototype in 28nm CMOS will sample in Q3, featuring four 16-processor clusters, a 1MB L2 memory and delivering 80GOPS (with 32 bit single precision floating point support) in 18mm [ABSTRACT FROM AUTHOR]

Published
2012
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130. Bipolar ReRAM Based non-volatile flip-flops for low-power architectures.

Author

Onkaraiah, Santhosh, Reyboz, Marina, Clermidy, Fabien, Portal, Jean-Michel, Bocquet, Marc, Muller, Chritophe, Hraziia, Anghel, Costin, and Amara

Abstract

Resistive Random Access Memories (ReRAMs) fabricated in the back-end-of-line are a promising breakthrough for including permanent retention mechanisms in embedded systems. This low-cost solution opens the way to advanced power management schemes. In this paper, we propose novel design architecture of a non-volatile flip-flop based on Bipolar ReRAMs (Bi-RNVFF). Compared to state-of-the-art Data-Retention flip-flop (with Balloon latch), the proposed design is 25% smaller due to 6T structure compared to the 8T structure of Data-Retention flip-flop. Moreover, being non-volatile, the proposed architecture exhibits a zero leakage compared to a Data-Retention Flip-Flop, which consumes ∼3.2µW in sleep mode (leakage) for a 10K Flip-Flop design implemented in 22nm FDSOI technology. Our simulation results show that Bi-RNVFF is a true alternative for future “Power-on, Power-off” application adding Non-Volatility without significant burdening of the existing architectures. [ABSTRACT FROM PUBLISHER]

Published
2012
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131. BackMatter.

Author

Gaillardon, Pierre-Emmanuel, O'Connor, Ian, and Clermidy, Fabien

Published
2012

132. FrontMatter.

Author

Gaillardon, Pierre-Emmanuel, O'Connor, Ian, and Clermidy, Fabien

Published
2012

138. An Asynchronous Power Aware and Adaptive NoC Based Circuit.

Author

Beigné, Edith, Clermidy, Fabien, Lhermet, Hélëne, Miermont, Sylvain, Thonnart, Yvain, Xuan-Tu Tran, Valentian, Alexandre, Varreau, Didier, Vivet, Pascal, Popon, Xavier, and Lebreton, Hugo

Subjects
NETWORKS on a chip, COMPLEMENTARY metal oxide semiconductors, MICROCONTROLLERS, ROBUST control, EMBEDDED computer systems, TOPOLOGY, POWER resources
Abstract

In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an issue at SoC grain. A fully power-aware globally-asynchronous locally-synchronous network-on-chip (NoC) circuit is presented in this paper. Network-on-chip architecture combined with a globally-asynchronous locally-synchronous paradigm is a natural enabler for DVFS mechanisms. The circuit is arranged around an asynchronous network-on-chip providing scalable communication and a 17 Gb/s throughput while automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each synchronous NoC units. No fine control software is required during voltage and frequency scaling. Power control is localized and a minimal latency cost is observed. [ABSTRACT FROM AUTHOR]

Published
2009
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139. A low complexity stopping criterion for reducing power consumption in turbo decoders

Author

Département Electronique (ELEC) ; Télécom Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest, Laboratoire d'Electronique et des Technologies de l'Information (LETI) ; CEA, Lab-STICC_TB_CACS_IAS ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - ENST Bretagne (ENST BRETAGNE) ; ENST Brest - ENST Brest - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Département Electronique (ELEC) ; Télécom Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire en sciences et technologies de l'information, de la communication et de la connaissance [Brest] (Lab-STICC) ; CNRS - Télécom Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Lab-STICC_TB_CACS_IAS ; Traitement Algorithmique et Matériel de la Communication, de l'Information et de la Connaissance (TAMCIC) ; CNRS - Ecole Nationale Supérieure des Télécommunications de Bretagne - CNRS - Ecole Nationale Supérieure des Télécommunications de Bretagne - ENST Bretagne (ENST BRETAGNE) ; ENST Brest - ENST Brest - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Département Electronique (ELEC) ; Télécom Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire en sciences et technologies de l'information, de la communication et de la connaissance [Brest] (Lab-STICC) ; CNRS - Télécom Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Reddy, Pallavi, Clermidy, Fabien, BAGHDADI, Amer, JEZEQUEL, Michel, Département Electronique (ELEC) ; Télécom Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest, Laboratoire d'Electronique et des Technologies de l'Information (LETI) ; CEA, Lab-STICC_TB_CACS_IAS ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - ENST Bretagne (ENST BRETAGNE) ; ENST Brest - ENST Brest - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Département Electronique (ELEC) ; Télécom Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire en sciences et technologies de l'information, de la communication et de la connaissance [Brest] (Lab-STICC) ; CNRS - Télécom Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Lab-STICC_TB_CACS_IAS ; Traitement Algorithmique et Matériel de la Communication, de l'Information et de la Connaissance (TAMCIC) ; CNRS - Ecole Nationale Supérieure des Télécommunications de Bretagne - CNRS - Ecole Nationale Supérieure des Télécommunications de Bretagne - ENST Bretagne (ENST BRETAGNE) ; ENST Brest - ENST Brest - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Département Electronique (ELEC) ; Télécom Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire en sciences et technologies de l'information, de la communication et de la connaissance [Brest] (Lab-STICC) ; CNRS - Télécom Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Reddy, Pallavi, Clermidy, Fabien, BAGHDADI, Amer, and JEZEQUEL, Michel

Abstract

International audience, Turbo codes are proposed in most of the advanced digital communication standards, such as 3GPP-LTE. However, due to its computational complexity, the turbo decoder is one of the most power hungry blocks in digital baseband. To alleviate this issue, one way is to avoid surplus computing phases thanks to the early termination of the iterative decoding process. The use of stopping criteria is one of the most common algorithm level power reduction methods in literature. These methods always come with some hardware overhead. In this paper, a new trellis based stopping criterion is proposed. The novelty of this approach is the lower hardware overhead thanks to the use of trellis states as key parameter to stop the iterative process. Results are showing the importance of this added hardware in terms of method efficiency. Compared to state-of-the-art Log Likelihood Ratio (LLR) based techniques, proposed Low Complexity Trellis Based (LCTB) is demonstrating 23% less power consumption on average, for comparable performance level in terms of Bit Error Rate (BER) and Frame Error Rate (FER).

142. Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Author

Ivan Miro-Panades, Fabien Clermidy, Philippe Flatresse, Jeremy Constantin, Frank K. Gurkaynak, Andreas Burg, Michael Gautschi, Antonio Pullini, Edith Beigne, Adam Teman, Luca Benini, Davide Rossi, Igor Loi, Rossi, Davide, Pullini, Antonio, Loi, Igor, Gautschi, Michael, Gurkaynak, Frank Kagan, Teman, Adam, Constantin, Jeremy, Burg, Andrea, Miro-Panades, Ivan, Beigne, Edith, Clermidy, Fabien, Flatresse, Philippe, and Benini, Luca

Subjects
Power management, parallel processing, Reduced instruction set computing, Computer science, business.industry, 020208 electrical & electronic engineering, UTBB FD-SOI, 02 engineering and technology, Parallel computing, 020202 computer hardware & architecture, Memory management, Software, body biasing, Parallel processing (DSP implementation), Hardware and Architecture, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, System on a chip, power management, Electrical and Electronic Engineering, business, energy efficiency, Computer hardware, Efficient energy use
Abstract

This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achieves 193 million operations per second (MOPS) per mW at 162 MOPS (32 bits), improving the first-generation Parallel Ultra-Low-Power (PULP) architecture by 6.4 and 3.2 times in performance and energy efficiency, respectively.

Published
2017

143. 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing

Author

Antonio Pullini, Jeremy Constantin, Adam Teman, Philippe Flatresse, Frank K. Gurkaynak, Igor Loi, Fady Abouzeid, Ivan Miro-Panades, Edith Beigne, Michael Gautschi, Andreas Burg, Fabien Clermidy, Davide Rossi, Luca Benini, Rossi, Davide, Pullini, Antonio, Loi, Igor, Gautschi, Michael, Gurkaynak, Frank Kagan, Teman, Adam, Constantin, Jeremy, Burg, Andrea, Miro-Panades, Ivan, Beign, Edith, Clermidy, Fabien, Abouzeid, Fady, Flatresse, Philippe, and Benini, Luca

Subjects
Power management, Signal processing, Multi-core processor, Hardware_MEMORYSTRUCTURES, business.industry, Computer science, Energy Efficiency, Parallel Processing, microprocessor chips, UTBB FD-SOI, MOPS, multiprocessing systems, chemistry.chemical_compound, Parallel processing (DSP implementation), chemistry, Power Management, Hardware and Architecture, energy efficicency, Computer cluster, business, Computer hardware, Block (data storage), Efficient energy use, Body Biasing
Abstract

Low power (mW) and high performance (GOPS) are strong requirements for compute-intensive signal processing in E-health, Internet-of-Things, and wearable applications. This work presents a building block for programmable Ultra-Low Power accelerators, namely a tightly-coupled computing cluster that supports parallel and sequential execution at high energy efficiency over a wide range of workload requirements. The cluster, implemented in 28nm UTBB FD-SOI technology, achieves peak energy efficiency in the near-threshold (NVT) operating region: 193 MOPS/mW at 162 MOPS for parallel workloads, and 90 MOPS/mW at 68 MOPS for sequential workloads at 0.46V and 0.5V, respectively. The energy efficient operating range is wide (0.32V to 1.15V), also meeting the design goal of 1 GOPS within a 10 mW power envelope (at 0.66V).

Published
2016

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