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We consider the computation of the Euclidean (or L2) norm of an n-dimensional vector in floating-point arithmetic. We review the classical solutions used to avoid spurious overflow or underflow and/or to obtain very accurate results. We modify a recently published algorithm (that uses double-word arithmetic) to allow for a very accurate solution, free of spurious overflows and underflows. To that purpose, we use a double-word square-root algorithm of which we provide a tight error analysis. The returned L2 norm will be within very slightly more than 0.5 ulp from the exact result, which means that we will almost always provide correct rounding. [ABSTRACT FROM AUTHOR]

We introduce an algorithm to decompose matrix representations of the symmetric group over the reals into irreducible representations, which as a by-product also computes the multiplicities of the irreducible representations. The algorithm applied to a d-dimensional representation of Sn\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$S_n$$\end{document} is shown to have a complexity of O(n2d3)\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$${\mathcal {O}}(n^2 d^3)$$\end{document} operations for determining which irreducible representations are present and their corresponding multiplicities and a further O(nd4)\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$${\mathcal {O}}(n d^4)$$\end{document} operations to fully decompose representations with non-trivial multiplicities. These complexity bounds are pessimistic and in a practical implementation using floating point arithmetic and exploiting sparsity we observe better complexity. We demonstrate this algorithm on the problem of computing multiplicities of two tensor products of irreducible representations (the Kronecker coefficients problem) as well as higher order tensor products. For hook and hook-like irreducible representations the algorithm has polynomial complexity as n increases. We also demonstrate an application to constructing a basis of homogeneous polynomials so that applying a permutation of variables induces an irreducible representation. [ABSTRACT FROM AUTHOR]

Due to the increasing popularity of application scenarios such as cloud computing, and the growing concern of users about the security and privacy of their data, information security and privacy protection technologies are facing new challenges. Consequently, Homomorphic Encryption (HE) technology has been developed. HE technology has evolved from Partially Homomorphic Encryption (PHE) to fully homomorphic encryption, from theory to practice Recently, the surge in machine learning applications has brought new challenges to HE technology. These applications require floating-point arithmetic numbers while adapting to a certain degree of precision loss, which has brought approximate homomorphic encryption (AHE) technology into the forefront of information security research. This work examines the development trajectory from PHE to AHE, and summarizes and analyzes the research works related to AHE from the three aspects: bootstrapping, improved precision, and variants. In addition, this work shows three different application scenarios of AHE from low level to high level, and combs the related works to present the readers with the latest application trend of AHE schemes. [ABSTRACT FROM AUTHOR]

The aim of this paper is to describe a Matlab package for computing the simultaneous Gaussian quadrature rules associated with a variety of multiple orthogonal polynomials. Multiple orthogonal polynomials can be considered as a generalization of classical orthogonal polynomials, satisfying orthogonality constraints with respect to r different measures, with r ≥ 1. Moreover, they satisfy (r + 2) -term recurrence relations. In this manuscript, without loss of generality, r is considered equal to 2. The so-called simultaneous Gaussian quadrature rules associated with multiple orthogonal polynomials can be computed by solving a banded lower Hessenberg eigenvalue problem. Unfortunately, computing the eigendecomposition of such a matrix turns out to be strongly ill-conditioned and the Matlab function balance.m does not improve the condition of the eigenvalue problem. Therefore, most procedures for computing simultaneous Gaussian quadrature rules are implemented with variable precision arithmetic. Here, we propose a Matlab package that allows to reliably compute the simultaneous Gaussian quadrature rules in floating point arithmetic. It makes use of a variant of a new balancing procedure, recently developed by the authors of the present manuscript, that drastically reduces the condition of the Hessenberg eigenvalue problem. [ABSTRACT FROM AUTHOR]

The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with highperformance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP multiplier is created using a 24x24 Wallace tree multiplier. In contrast, the reciprocal unit of the RFP divider is designed using Newton Raphson’s method. The RFPA unit and its submodules are executed in parallel by utilizing one clock cycle individually. The RFPA unit and its submodules are synthesized separately on the Vivado IDE environment and obtained the implementation results on Artix-7 field programmable gate array (FPGA). The RFPA unit utilizes only 18.44% slice look-up tables (LUTs) by consuming the 0.891 W total power on Artix-7 FPGA. The RFPA unit sub-models are compared with existing approaches with better performance metrics and chip resource utilization improvements. [ABSTRACT FROM AUTHOR]

Addition is a ubiquitous operation frequently carried out in most computing applications. Traditionally, three-operand addition is done using either two adders or a carry–save adder. However, there exist applications such as digital signal processing, image processing, floating point arithmetic, etc. wherein among the three operands, one is constant. For such cases, we propose a flagged constant addition methodology, applicable to any constant, to compute the result with the least area, delay and power. The resulting architecture is referred to as general constant flagged adder (GCFA). We propose an Optimized Constant Generation (OCG) algorithm and a Hardware Optimization Algorithm (HOA) to achieve hardware-efficient constant flagged adder. These two algorithms are designed to lower the computational complexity. The OCG algorithm accepts the constant to be added and converts it into an optimized constant. This optimized constant then forms the input to the HOA where the hardware modifications are performed. Unlike the proposed work, the existing flagged adder structures do not provide a general methodology to obtain the optimized constant and hardware for all the constants, resulting from the presence of architectural customization for all constants and word lengths. Exhaustive hardware analyses have been carried out to prove the efficacy of the proposed architecture against the existing designs. Structural Verilog code is synthesized for each to obtain the area, delay and power. Synthesis results show up to 35.85% and 49.24% reductions in area–delay and power–delay products, respectively. The improved speed and lower hardware requirements make the proposed methodology a suitable choice for constant addition. [ABSTRACT FROM AUTHOR]

Power-electronics-based systems have penetrated into several critical sectors, such as the industry, power generation, energy transmission and distribution, and transportation. In this context, the system's control, often implemented in real-time processing units, has to meet stringent requirements in terms of safety and repeatability. Given the growing complexity of the implemented algorithms, floating-point arithmetic is being increasingly adopted for high-performance systems. This paper proposes to assess the numerical stability of the control algorithms by means of an interval analysis. The case study of an electric drive is considered, given the wide adoption of such systems and the importance they hold for the safety of the applications. In particular, two different control strategies—the resonant control and the vector space decomposition—are examined, and a sensitivity analysis based on the proposed technique highlights the different characteristics of the two with respect to numerical stability. The proposed method shows how the resonant control is more robust to variations of the controller gain coefficients with respect to the numerical stability, which could make it the preferred choice for mission-critical electric drive control. [ABSTRACT FROM AUTHOR]

In recent years, interest in approximate computing has been increasing significantly in many disciplines in the context of saving energy and computation cost by trading off on the quality of numerical simulation. The hardware acceleration based on the low-precision floating-point arithmetic is anticipated by the upcoming generation of microprocessors and code compilers and has already proven to be beneficial for weather and climate modelling and neural network training. The present work illustrates the application of low-precision arithmetic for the nuclear reactor core uncertainty analysis. We studied the performance of an elementary transient reactor core model for the arbitrary precision of the floating-point multiplication in a direct linear system solver. Using this model, we calculated the reactor core transients initiated by the control rod ejection taking into account the uncertainty of the model input parameters. Then, we evaluated the round-off errors of the model outputs for different precision levels. The comparison of the round-off errors and the model uncertainty showed the model could be run using a 15-bit floating-point number precision with an acceptable degradation of the result's accuracy. This precision corresponds to a gain of about 6× in the bit complexity of the linear system solution algorithm, which can be actualized in terms of reduced energy costs on low-precision hardware. [ABSTRACT FROM AUTHOR]

The use of floating-point units (FPU) in digital signal processing has increased due to the range and the high precision numbers that can be represented. These units are required in image processing, digital filters with infinite impulse response (IIR), finite impulse response (FIR), and digital controllers, to obtain accurate results and avoid unstable responses, however, to implement them, some processors have built-in units, this implies a technological dependency of the manufacturers when prototypes are developed. To avoid such dependency, this article presents the design of modules for the most used operations in digital signal processing: multiplication and addition/subtraction. To be able to implement these operations in any Field Programmable Gate Array (FPGA), the steps and considerations to be aware of are presented, such as exceptions, rounding, and normalization of operands. Results are verified using the MODELSIM® test bench and the error rate was determined using MATLAB®. [ABSTRACT FROM AUTHOR]

Fast 3D data analysis and steering of a tomographic experiment by changing environmental conditions or acquisition parameters require fast, close to realtime, 3D reconstruction of large data volumes. Here a performance-optimized TomocuPy package is presented as a GPU alternative to the commonly used central processing unit (CPU) based TomoPy package for tomographic reconstruction. TomocuPy utilizes modern hardware capabilities to organize a 3D asynchronous reconstruction involving parallel read/write operations with storage drives, CPU-GPU data transfers, and GPU computations. In the asynchronous reconstruction, all the operations are timely overlapped to almost fully hide all data management time. Since most cameras work with less than 16-bit digital output, the memory usage and processing speed are furthermore optimized by using 16-bit floating-point arithmetic. As a result, 3D reconstruction with TomocuPy became 20-30 times faster than its multi-threaded CPU equivalent. Full reconstruction (including read/write operations and methods initialization) of a 20483 tomographic volume takes less than 7 s on a single Nvidia Tesla A100 and PCIe 4.0 NVMe SSD, and scales almost linearly increasing the data size. To simplify operation at synchrotron beamlines, TomocuPy provides an easy-to-use command-line interface. Efficacy of the package was demonstrated during a tomographic experiment on gas-hydrate formation in porous samples, where a steering option was implemented as a lens-changing mechanism for zooming to regions of interest. [ABSTRACT FROM AUTHOR]

Specialized arithmetic units allow fast and efficient computation of lesser used mathematical functions. The overall impact of those units would be negligible in a general purpose processor, as added circuitry makes chips more complex despite most software would seldom make use of it. On the opposite side, custom computing machines are built for a specific task, and they can always benefit from specialized units if they are available. In this work, floating point architectures are proposed for computing the cube on Intel and Xilinx FPGAs. Those implementations reduce the cost and latency compared to using simple floating point multiplications and squarers. [ABSTRACT FROM AUTHOR]

Floating-point numbers represent only a subset of real numbers. As such, floating-point arithmetic introduces approximations that can compound and have a significant impact on numerical simulations. We introduce encapsulated error, a new way to estimate the numerical error of an application and provide a reference implementation, the Shaman library. Our method uses dedicated arithmetic over a type that encapsulates both the result the user would have had with the original computation and an approximation of its numerical error. We thus can measure the number of significant digits of any result or intermediate result in a simulation. We show that this approach, although simple, gives results competitive with state-of-the-art methods. It has a smaller overhead, and it is compatible with parallelism, making it suitable for the study of large-scale applications. [ABSTRACT FROM AUTHOR]

Boolean operations are among the most used paradigms to create and edit digital shapes. Despite being conceptually simple, the computation of mesh Booleans is notoriously challenging. Main issues come from numerical approximations that make the detection and processing of intersection points inconsistent and unreliable, exposing implementations based on floating point arithmetic to many kinds of degeneracy and failure. Numerical methods based on rational numbers or exact geometric predicates have the needed robustness guarantees, that are achieved at the cost of increased computation times that, as of today, has always restricted the use of robust mesh Booleans to offline applications. We introduce an algorithm for Boolean operations with robustness guarantees that is capable of operating at interactive frame rates on meshes with up to 200K triangles. We evaluate our tool thoroughly, considering not only interactive applications but also batch processing of large collections of meshes, processing of huge meshes containing millions of elements and variadic Booleans of hundreds of shapes altogether. In all these experiments, we consistently outperform prior robust floating point methods by at least one order of magnitude. [ABSTRACT FROM AUTHOR]

Machine-learning accelerators rely on floating-point matrix and vector multiplication kernels. To reduce their cost, customized many-term fused architectures are preferred, which improve the latency, power, and area of the designs. In this work, we design a parameterized fused many-term floating-point dot product architecture that is ready for high-level synthesis. In this way, we can exploit the efficiency offered by a well-structured fused dot-product architecture and the freedom offered by high-level synthesis in tuning the design's pipeline to the selected floating-point format and architectural constraints. When compared with optimized dot-product units implemented directly in RTL, the proposed design offers lower-latency implementations under the same clock frequency with marginal area savings. This result holds for a variety of floating-point formats, including standard and reduced-precision representations. [ABSTRACT FROM AUTHOR]

Convolutional neural networks (CNNs) have become a ubiquitous algorithm with growing applications in mobile and edge settings. We describe a compute-in-memory (CIM) technique called POD-RACING using Racetrack memory (RM) to accelerate CNNs for edge systems. Using transverse read, a technique that can determine the number of "1"s in multiple adjacent domains, POD-RACING can efficiently implement multioperand bulk-bitwise and addition computations, and two-operand multiplication. We discuss how POD-RACING can implement both variable precision integer and floating point arithmetic using digital CIM. This allows both CNN inference and on-device training without expensive data movement to the cloud. Based on these functions we demonstrate the implementation of several CNNs with backpropagation using RM CIM and compare these to the state-of-the-art implementations of CNN inference and training. During training, POD-RACING improves efficiency by 2×, energy consumption by $\geq$≥27%, and increases throughput by $\geq$≥18% versus a state-of-the-art field-programmable gate array accelerator. [ABSTRACT FROM AUTHOR]

Low bitwidth integer arithmetic has been widely adopted in hardware implementations of deep neural network inference applications. However, despite the promised energy-efficiency improvements demanding edge applications, the use of low bitwidth integer arithmetic for neural network training remains limited. Unlike inference, training demands high dynamic range and numerical accuracy for high quality results, making the use of low-bitwidth integer arithmetic particularly challenging. To address this challenge, we present a novel neural network training framework called NITI that exclusively utilizes low bitwidth integer arithmetic. NITI stores all parameters and accumulates intermediate values as 8-bit integers while using no more than 5 bits for gradients. To provide the necessary dynamic range during the training process, a per-layer block scaling exponentiation scheme is utilized. By deeply integrating with the rounding procedures and integer entropy loss calculation, the proposed scaling scheme incurs only minimal overhead in terms of storage and additional computation. Furthermore, a hardware-efficient pseudo-stochastic rounding scheme that eliminates the need for external random number generation is proposed to facilitate conversion from wider intermediate arithmetic results to lower precision for storage. Since NITI operates only with standard 8-bit integer arithmetic and storage, it is possible to accelerate it using existing low bitwidth operators originally developed for inference in commodity accelerators. To demonstrate this, an open-source software implementation of end-to-end training, using native 8-bit integer operations in modern GPUs is presented. In addition, experiments have been conducted on an FPGA-based training accelerator to evaluate the hardware advantage of NITI. When compared with an equivalent training setup implemented with floating point storage and arithmetic, NITI has no accuracy degradation on the MNIST and CIFAR10 datasets. On ImageNet, NITI achieves similar accuracy as state-of-the-art integer training frameworks without relying on full-precision floating-point first and last layers. [ABSTRACT FROM AUTHOR]

The microcomputer architecture named BZK.SAU.FPGA, which was developed in 2014, was used to increase efficiency in the teaching of the Computer Architecture and Organization course, which is one of the basic courses of the Department of Computer Engineering. In the last version released in 2018, the architecture has been started to be used in many engineering disciplines with its modular structure and a basic operating system. However, this architecture uses fixed‐point numbers in arithmetic operations. Although this situation contributes to its use as an educational tool at the beginner level for new learners, the fact that it cannot operate with floating point numbers is one of the biggest shortcomings of the educational tool. Floating point numbers are used extensively in applications such as mathematical analysis, signal processing, image processing, and so on. Therefore, in this study, the FPA unit for the computation of addition, subtraction, multiplication, and division operations is integrated into this architecture. For FPA unit implementation, an assembly‐level program has been embedded in the architecture using an IEEE‐754 half‐precision binary format (FP16) with the aim of presenting the fundamental of the floating‐point computation. The FPA unit proposed to observe the behavior of floating point numbers in arithmetic operations and increase awareness of these issues was used as an auxiliary tool in the computer architecture course. A pre‐ and postsurvey study was conducted to see the learning outcomes of students using this tool on floating point numbers. We found a significant association between pre‐ and postsurvey, indicating that students' knowledge about the behavior of floating point numbers increased (p <.001). [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Implementing chaos based ciphers usually involves 32-bit floating-point arithmetics that is hardware resources costly. The limitation of the computational precision is hardware imposed and transforms chaotic orbits into limit cycles with short periods, hence alters their randomness. In cryptographic applications, short period dynamics and weak randomness result in security issues. In order to address this concern, we propose an 8-bit precision cipher that can be implemented with low-end microprocessors running 8-bit integer arithmetics. The cipher includes a quantized pseudo-random number generator (QPRNG) based on a 16-dimensional quantized Arnold's cat map (QACM). We used entropy measure, statistical, sensitivity and key space analyses to evaluate its security level under limited computational precision. Simulation results attest that it is as highly secure as those involving real-number arithmetics, even for only 8-bit precision. We also showed that the period of the proposed QACM can be chosen such that Tx > 1027, which is very large as compared to existing QACM. Such a large period implies a high randomness of the derived QPRNG that is confirmed by statistical NIST tests. Contrary to existing ciphers that include other chaotic systems than the QACM for strengthening the security level, ours is exclusively based on the QACM and is fast, despite the included high-dimensional QACM. [ABSTRACT FROM AUTHOR]

Copyright of Erzincan University Journal of Science & Technology is the property of Erzincan Binali Yildirim Universitesi and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Approximate computing can significantly reduce the energy consumption of computing systems. Mixed-precision hardware architectures and precision-tuning tools for software provide the ability to introduce approximations, but when applied separately, they do not give complete control over the accuracy-energy trade-off. The co-optimization of approximations in hardware and software is a complex task, but it promises considerable benefits. We present a methodology for the fast design-time selection of mixed-precision hardware-software combinations that minimize the energy consumption and the area of the target FPGA-based softcore CPUs with configurable support for floating-point and fixed-point arithmetic. Our approach can evaluate configurations more than 2000 times faster than the alternative approach of using gate-level simulation. On benchmarks from the PolyBench suite the identified hardware-software configurations showed improvement of the energy-to-solution metric ranging from 20% to 95%. [ABSTRACT FROM AUTHOR]

Low precision arithmetic, in particular half precision (16‐bit) floating point arithmetic, is now available in commercial hardware. Using lower precision can offer significant savings in computation and communication costs with proportional savings in energy. Motivated by this, there has been a renewed interest in mixed precision iterative refinement schemes for solving linear systems Ax=b, and new variants of GMRES‐based iterative refinement have been developed. Each particular variant with a given combination of precisions leads to different condition number‐based constraints for convergence of the backward and forward errors, and each has different performance costs. The constraints for convergence given in the literature are, as an artifact of the analyses, often overly strict in practice, and thus could lead a user to select a more expensive variant when a less expensive one would have sufficed. In this work, we develop a multistage mixed precision iterative refinement solver which aims to combine existing mixed precision approaches to balance performance and accuracy and improve usability. For a user‐specified initial combination of precisions, the algorithm begins with the least expensive approach and convergence is monitored via inexpensive computations with quantities produced during the iteration. If slow convergence or divergence is detected using particular stopping criteria, the algorithm switches to use a more expensive, but more reliable variant. A novel aspect of our approach is that, unlike existing implementations, our algorithm first attempts to use "stronger" GMRES‐based solvers for the solution update before resorting to increasing the precision(s). In some scenarios, this can avoid the need to refactorize the matrix in higher precision. We perform extensive numerical experiments on a variety of random dense problems and problems from real applications which confirm the benefits of the multistage approach. [ABSTRACT FROM AUTHOR]

We show to what extent the accuracy of the inner products computed in the GMRES iterative solver can be reduced as the iterations proceed without affecting the convergence rate or final accuracy achieved by the iterates. We bound the loss of orthogonality in GMRES with inexact inner products. We use this result to bound the ratio of the residual norm in inexact GMRES to the residual norm in exact GMRES and give a condition under which this ratio remains close to 1. We illustrate our results with examples in variable floating-point arithmetic. [ABSTRACT FROM AUTHOR]

Drawing a floating-point number uniformly at random from an interval [a, b) is usually performed by a location-scale transformation of some floating-point number drawn uniformly from [0, 1). Due to the weak properties of floating-point arithmetic, such a transformation cannot ensure respect of the bounds, uniformity or spatial equidistributivity. We investigate and quantify precisely these shortcomings while reviewing the actual implementations of the method in major programming languages and libraries, and we propose a simple algorithm to avoid these shortcomings without compromising performances. [ABSTRACT FROM AUTHOR]

In this paper, a two-sided, parallel Kogbetliantz-type algorithm for the hyperbolic singular value decomposition (HSVD) of real and complex square matrices is developed, with a single assumption that the input matrix, of order n, admits such a decomposition into the product of a unitary, a non-negative diagonal, and a J-unitary matrix, where J is a given diagonal matrix of positive and negative signs. When J = ±I, the proposed algorithm computes the ordinary SVD. The paper's most important contribution—a derivation of formulas for the HSVD of 2 × 2 matrices—is presented first, followed by the details of their implementation in floating-point arithmetic. Next, the effects of the hyperbolic transformations on the columns of the iteration matrix are discussed. These effects then guide a redesign of the dynamic pivot ordering, being already a well-established pivot strategy for the ordinary Kogbetliantz algorithm, for the general, n × n HSVD. A heuristic but sound convergence criterion is then proposed, which contributes to high accuracy demonstrated in the numerical testing results. Such a J-Kogbetliantz algorithm as presented here is intrinsically slow, but is nevertheless usable for matrices of small orders. [ABSTRACT FROM AUTHOR]

Motivated by the unexpected failure of the triangle intersection component of the Projection Algorithm for Nonmatching Grids (PANG), this article provides a robust version with proof of backward stability. The new triangle intersection algorithm ensures consistency and parsimony across three types of calculations. The set of intersections produced by the algorithm, called representations, is shown to match the set of geometric intersections, called models. The article concludes with a comparison between the old and new intersection algorithms for PANG using an example found to reliably generate failures in the former. [ABSTRACT FROM AUTHOR]

This paper concerns test matrices for numerical linear algebra using an error-free transformation of floating-point arithmetic. For specified eigenvalues given by a user, we propose methods of generating a matrix whose eigenvalues are exactly known based on, for example, Schur or Jordan normal form and a block diagonal form. It is also possible to produce a real matrix with specified complex eigenvalues. Such test matrices with exactly known eigenvalues are useful for numerical algorithms in checking the accuracy of computed results. In particular, exact errors of eigenvalues can be monitored. To generate test matrices, we first propose an error-free transformation for the product of three matrices YSX. We approximate S by S ′ to compute Y S ′ X without a rounding error. Next, the error-free transformation is applied to the generation of test matrices with exactly known eigenvalues. Note that the exactly known eigenvalues of the constructed matrix may differ from the anticipated given eigenvalues. Finally, numerical examples are introduced in checking the accuracy of numerical computations for symmetric and unsymmetric eigenvalue problems. [ABSTRACT FROM AUTHOR]

Prior recent work, devoted to the study of polynomial Krylov techniques for the approximation of the action of the matrix exponential etAv, is extended to the case of associated φ-functions (which occur within the class of exponential integrators). In particular, a posteriori error bounds and estimates, based on the notion of the defect (residual) of the Krylov approximation are considered. Computable error bounds and estimates are discussed and analyzed. This includes a new error bound which favorably compares to existing error bounds in specific cases. The accuracy of various error bounds is characterized in relation to corresponding Ritz values of A. Ritz values yield properties of the spectrum of A (specific properties are known a priori, e.g., for Hermitian or skew-Hermitian matrices) in relation to the actual starting vector v and can be computed. This gives theoretical results together with criteria to quantify the achieved accuracy on the fly. For other existing error estimates, the reliability and performance are studied by similar techniques. Effects of finite precision (floating point arithmetic) are also taken into account. [ABSTRACT FROM AUTHOR]

Recent applications in low-power (1-20 mW) near-sensor computing require the adoption of floating-point arithmetic to reconcile high precision results with a wide dynamic range. In this article, we propose a low-power multi-core computing cluster that leverages the fined-grained tunable principles of transprecision computing to provide support to near-sensor applications at a minimum power budget. Our solution – based on the open-source RISC-V architecture – combines parallelization and sub-word vectorization with a dedicated interconnect design capable of sharing floating-point units (FPUs) among the cores. On top of this architecture, we provide a full-fledged software stack support, including a parallel low-level runtime, a compilation toolchain, and a high-level programming model, with the aim to support the development of end-to-end applications. We performed an exhaustive exploration of the design space of the transprecision cluster on a cycle-accurate FPGA emulator, varying the number of cores and FPUs to maximize performance. Orthogonally, we performed a vertical exploration to identify the most efficient solutions in terms of non-functional requirements (operating frequency, power, and area). We conducted an experimental assessment on a set of benchmarks representative of the near-sensor processing domain, complementing the timing results with a post place-&-route analysis of the power consumption. A comparison with the state-of-the-art shows that our solution outperforms the competitors in energy efficiency, reaching a peak of 97 Gflop/s/W on single-precision scalars and 162 Gflop/s/W on half-precision vectors. Finally, a real-life use case demonstrates the effectiveness of our approach in fulfilling accuracy constraints. [ABSTRACT FROM AUTHOR]

Transprecision computing targets energy-efficiency with multiple floating-point modules with different precisions to suit application requirements. Variable-precision architectures aim at making a more efficient hardware resource utilization, but they often rely on the IEEE-754 standard, without low-precision arithmetic support. Alternatively, the Posit format is particularly well-suited for low-precision arithmetic. However, for higher precisions, hardware requirements become prohibitive. Accordingly, this brief proposes a new unified Posit/IEEE-754 Vector Multiply-Accumulate (VMAC) unit, comprising a vectorized variable-precision datapath with shared support for the Posit and IEEE-754 formats. A 28nm ASIC implementation resulted in 50% less area and $2.9\times $ less power consumption than typical transprecision setups. [ABSTRACT FROM AUTHOR]

Block low-rank (BLR) matrices possess a blockwise low-rank property that can be exploited to reduce the complexity of numerical linear algebra algorithms. The impact of these low-rank approximations on the numerical stability of the algorithms in floating-point arithmetic has not previously been analysed. We present rounding error analysis for the solution of a linear system by LU factorization of BLR matrices. Assuming that a stable pivoting scheme is used, we prove backward stability: the relative backward error is bounded by a modest constant times |$\varepsilon $|⁠ , where the low-rank threshold |$\varepsilon $| is the parameter controlling the accuracy of the blockwise low-rank approximations. In addition to this key result, our analysis offers three new insights into the numerical behaviour of BLR algorithms. First, we compare the use of a global or local low-rank threshold and find that a global one should be preferred. Second, we show that performing intermediate recompressions during the factorization can significantly reduce its cost without compromising numerical stability. Third, we consider different BLR factorization variants and determine the update–compress–factor variant to be the best. Tests on a wide range of matrices from various real-life applications show that the predictions from the analysis are realized in practice. [ABSTRACT FROM AUTHOR]

We propose a novel clock skew compensation algorithm based on Bresenham’s line drawing algorithm. The proposed algorithm can avoid the effect of limited floating-point precision (e.g., 32-bit single precision) on clock skew compensation and thereby provide high-precision time synchronization even with resource-constrained sensor nodes in wireless sensor networks. [ABSTRACT FROM AUTHOR]

The overall network effectiveness in any real time application is defined by the amount of precision used in computing and the capacity to sustain low cost hardware. Within this context optimisation method for floating point computing is starting to emerge gradually due to the enhanced precision level. Particularly with regard to FFT floating point arithmetic model calculation, hardware sophistication is forced to minimise the uncertainty penalty gap between fixed points – FFT floating point prototype. Hardware fusion systems are designed primarily for increasing the use rate of hardware throughout FPU arithmetic calculations. The proposed system to compute mantissa is actually achieved using which hardware counts are reduced in a complex multiplication process and afterwards the signed digit recoding can be reconfigured by a digital integer. Eventually, the technique of radix factorisation is integrated to minimise complex arithmetic associated with phases of FFT. The results show that the algorithm proposed shows decreased field, elevated frequency of operation and an increased level of accuracy. Ultimately, it is contrasted with efficient FPGA implementation that uses the capital and robustness of the proposed fused CSD FP models. [ABSTRACT FROM AUTHOR]

Leading zero count (LZC) is a fundamental building block in floating-point arithmetic and data sketches. These applications are increasingly being implemented on field-programmable gate arrays (FPGAs), however, existing architectures for LZC target application-specific integrated circuits and to the best of our knowledge specific LZC implementations tailored to FPGA structures have not been presented. In this letter, the implementation of LZC on Xilinx FPGA is considered and it is shown that by carefully adapting the LZC design to the FPGA structure, more efficient implementations can be obtained. In more detail, LZC designs for different bit widths are presented and evaluated. The results show that significant reductions in the FPGA resources needed are obtained that reach 33% lookup tables (LUTs) saving for 32-bit vectors and 20% LUTs saving for 64-bit vectors. [ABSTRACT FROM AUTHOR]

The rising concerns about global warming have motivated the international community to take remedial actions to lower greenhouse gas emissions. The transportation sector is believed to be one of the largest air polluters. The quantity of greenhouse gas emissions is directly linked to the fuel consumption of vehicles. Eco-driving is an emergent driving style that aims at improving gas mileage. Real-time fuel estimation is a critical feature of eco-driving and eco-routing. There are numerous approaches to fuel estimation. The first approach uses instantaneous values of speed and acceleration. This can be accomplished using either GPS data or direct reading through the OBDII interface. The second approach uses the average value of the speed and acceleration that can be measured using historical data or through web mapping. The former cannot be used for route planning. The latter can be used for eco-routing. This paper elaborates on a highly pipelined VLSI architecture for the fuel estimation algorithm. Several high-level transformation techniques have been exercised to reduce the complexity of the algorithm. Three competing architectures have been implemented on FPGA and compared. The first one uses a binary search algorithm, the second architecture employs a direct address table, and the last one uses approximation techniques. The complexity of the algorithm is further reduced by combining both approximated computing and precalculation. This approach helped reduce the floating-point operations by 30% compared with the state-of-the-art implementation. [ABSTRACT FROM AUTHOR]