Search

In this article, a semi-analytical model for germanium absorber-based SOI-tunnel field-effect phototransistor at 1550 nm has been proposed. The model works efficiently for a wide range of intensities i.e. 10−2 to 102 µW/µm2 under the application of a very low gate voltage of 0.54 V. Exhaustive simulations using numerical ATLAS 2D device simulation tool with LUMNINOUS optical module have been carried out to propose the merit of tunnel field-effect transistors (TFETs) over metal oxide semiconductor field effect transistors (MOSFETs) for optical applications. The proposed TFET design provides a way to assist the ultrasensitive optical interconnects at a very low gate bias of 0.54 V with a maximum sensitivity of 1.5 × 107, responsivity of 270 mA/W, and detectivity of 3.5 × 1012 Jones at low power density of 0.01 µW/µm2. The TFET performance has further been improved by introducing a heavily doped pocket in between source and channel, which serves as a potential alternative for photodetector applications. The proposed pocket-doped TFET design offers significant improvements in device optical response with optimized sensitivity of 4.1 × 107, a responsivity of 772 mA/W, and a detectivity of 9.9 × 1012 Jones at an optical intensity of 0.01 µW/µm2, gate bias of 0.45 V, and drain voltage of 0.6 V. Transient analysis has been carried out to optimize the response time of the phototransistor for both Ge-gated conventional TFET and pocket-doped architecture and the fall time of ∼0.22 ms has been achieved. [ABSTRACT FROM AUTHOR]

This investigation examines the performance of AlGaN/GaN MISHEMTs having single-gate and dual-gate with different biasing combinations to explore the linearity in terms of gmpeak, gate voltage swing (GVS) and higher-order coefficients for intermodulation distortion for low-noise amplifiers (LNAs). In addition, the influence of distinct gate biasing configurations of DG-MISHEMT on current collapse (CC) (in response to OFF-state stress in drain) has been studied using TCAD simulations. It has been observed that drop in drain current value after the gate–drain voltages return to quiescent voltages (VGSQ, VDSQ) reduces for DG-MISHEMT (when both the gates are shorted together) to 9.1% as compared with 19.4% for SG-MISHEMT. Besides, the CC phenomena for DG-MISHEMTs (for shorted gates) exhibit a slight increase from 9% to 11.8% when workfunction increases from 4.1 eV to 5.2 eV for gate G2. Further, linearity in terms of GVS is observed to be doubled for AlGaN/GaN DG-MISHEMTs with both the gates connected together as compared with device with screen gate G2 shorted to source. Additionally, radio frequency performance has been studied in terms of cut-off frequencies fT and fmax and minimum noise-figure NFmin for AlGaN/GaN SG-MISHEMT and DG-MISHEMTs for different gate to gate distance i.e., LGG =100 and 200 nm. It is observed that NFmin is minimum for AlGaN/GaN DG-MISHEMT (with gate G1 floating and gate G2 is biased and LGG =100 nm) i.e., 1.13 dB with corresponding power gain of 18.7 dB at 50 GHz. [ABSTRACT FROM AUTHOR]

This paper systematically studies the reliability of non-uniformly doped Double Gate Junctionless transistor using ATLAS TCAD simulation. The reliability analysis is mainly based on the understanding of Band-To-Band-Tunneling (BTBT) current, lattice temperature, drain conductance and gate leakage current. Presented results show that higher source/drain work-function is beneficial in reducing tunneling current (1 × 10−9 A to 4 × 10−11 A @ Vgs = −1 V) but eventually it will also degrade electrostatic current significantly (∼3 order). Source/Drain length has also been varied during optimization and it has been observed that, shorter source drain extension region degrades the device reliability (i.e. higher magnitude of tunneling current (7 × 10−9 A @ Vgs =−1 V for LS = LD = 5 nm)). Different doping profile considered for performance assessment are: uniform, step (i.e. low–low–high and high–high–low etc.) and different configurations of gaussian doping profile. Minimum variation in tunneling current with negative gate bias, i.e. ∼ 1 order has been seen from the device having uniform doping 1019 cm−3 but at the cost of significantly high off-state current (2 × 10−9 A @ Vgs = 0 V) and tunneling current (2 × 10−8 A @ Vgs = −1 V). Thus, instead of using uniform doping, step type profile (i.e. Case A) is the better choice which results in lower tunneling current (1 × 10−9 A @ Vgs = −1 V), moderate lattice temperature (326) and better Ion/Ioff ratio (243 × 108). Device lattice temperature has also been controlled by using step A doping profile even at the higher operating temperatures due to lower Self Heating Effect. [ABSTRACT FROM AUTHOR]

Dopingless tunnel field effect transistor (DL-TFET) exhibits a great potential for lowering the sub-threshold current and hence increases the ION/IOFF ratio because of its electrostatically doped source and drain. An analytical model for double gate dopingless tunnel field transistor (DG-DL TFET) is developed, for the first time, by calculating the source and drain work-function-induced doping and using it for solving the 2D Poisson's equation in various regions. Electric potentials, energy band diagrams, electric field, corresponding drain current characteristics, and trans-conductance are obtained through the developed model and are validated by performing extensive device simulation for different gate and drain bias voltages. An excellent match between modeled and simulated results proves the efficacy of the developed model. The ION current obtained in Si-based dopingless TFET is 0.16 µA/µm, IOFF has reduced to 0.296 fA/µm and ION/IOFF obtained from the proposed device structure is 5.4 × 108, and the sub-threshold swing is 50.77 mV/decade. The DG-DL TFET is analyzed for resistive load inverter characteristics and has been further investigated for realizing digital logic functions by controlling the gates of the device independently. The realization of NAND gate requires one "p-type DG-DL TFET", whereas OR gate requires one "n-type DG-DL TFET". The implementations of single bias-controlled logics are useful as they render energy-efficient operations and simultaneously increase the packaging density. [ABSTRACT FROM AUTHOR]

An analytical surface potential model and 3-D ATLAS device simulations are used to investigate the impact of gate misalignment on the performance of dual-material double-gate (DMDG) silicon-on-insulator (SOI) n-MOSFET (metal-oxide-semiconductor field-effect transistor). Analytical and simulation results are consistent, which validates the proposed model for the DMDG SOI n-MOSFET.