348 results on '"Huo, Zongliang"'
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102. A Quantitative Approach to Characterize Total Ionizing Dose Effect of Periphery Device for 65 nm Flash Memory
103. PSM control technique for primary‐side regulating fly‐back converters
104. Investigation of Cycling-Induced Dummy Cell Disturbance in 3D NAND Flash Memory
105. Unification of three multiphonon trap-assisted tunneling mechanisms.
106. Performance-improved nonvolatile memory with aluminum nanocrystals embedded in Al2O3 for high temperature applications.
107. Word line interference based data recovery technique for 3D NAND Flash
108. A fast read retry method for 3D NAND flash memories using novel valley search algorithm
109. A Novel Read Scheme for Read Disturbance Suppression in 3D NAND Flash Memory
110. A 1.2 mV ripple, 4.5 V charge pump using controllable pumping current technology
111. Dynamic LLR scheme based on EM algorithm for LDPC decoding in NAND flash memory
112. A high efficiency all-PMOS charge pump for 3D NAND flash memory
113. Performance Enhancement of Metal Floating Gate Memory by Using a Bandgap Engineered High-k Tunneling Barrier
114. Investigation of tunneling layer and inter-gate-dielectric engineered TaN floating gate memory
115. A novel adaptive CMOS low-dropout regulator with 3A sink/source capability
116. A high efficiency all-PMOS charge pump for 3D NAND flash memory
117. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory
118. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory
119. Gate Bias Dependence of Complex Random Telegraph Noise Behavior in 65-nm NOR Flash Memory
120. A write buffer design based on stable and area-saving embedded SRAM for flash applications
121. Low-temperature post-deposition annealing investigation for 3D charge trap flash memory by Kelvin probe force microscopy
122. A page buffer design based on stable and area-saving embedded SRAM for flash applications
123. Program charge effect on random telegraph noise behavior in multi-level floating gate flash memory
124. Total ionizing dose effect investigated by in-situ measurements for a 65nm flash technology
125. Investigation of charge loss mechanisms IN 3D TANOS cylindrical junction-less charge trapping memory
126. An simple approach to evaluate TID response in High Voltage MOSFET for 65nm flash technology
127. Memory Switching: Direct Observation of Conversion Between Threshold Switching and Memory Switching Induced by Conductive Filament Morphology (Adv. Funct. Mater. 36/2014)
128. Investigation of charge loss characteristics of HfO2annealed in N2or O2ambient
129. Direct Observation of Conversion Between Threshold Switching and Memory Switching Induced by Conductive Filament Morphology
130. Thermally assisted magnetic switching of a single perpendicularly magnetized layer induced by an in-plane current
131. Metal Floating Gate Memory Device With SiO2/HfO2 Dual-Layer as Engineered Tunneling Barrier
132. A Study of P/E Cycling Impaction on Drain Disturb for 65nm NOR Flash Memories by Low Frequency Noise Analyze
133. Gate induced resistive switching in 1T1R structure with improved uniformity and better data retention
134. Low temperature atomic layer deposited HfO2film for high performance charge trapping flash memory application
135. Effect of Pre-annealing to Blocking Oxide on the Performance of Dual Trapping-layer Engineered Charge Trapping Memory
136. Comparison between N 2 and O 2 anneals on the integrity of an Al 2 O 3 /Si 3 N 4 /SiO 2 /Si memory gate stack
137. Enhanced DNA Sequencing Performance Through Edge-Hydrogenation of Graphene Electrodes
138. DNA sequencing with nanopore-embedded bilayer-graphene nanoelectrodes
139. Effect of Damage in Source and Drain on the Endurance of a 65-nm-Node NOR Flash Memory
140. Isolated nanographene crystals for nano-floating gate in charge trapping memory
141. Effects of Interfacial Fluorination on Performance Enhancement of High-k-Based Charge Trap Flash Memory
142. Visualization on charge distribution behavior in thickness-scalable HfO2 trapping layer by in-situ electron holography and Kelvin Probe Force Microscopy technology
143. Bipolar one diode–one resistor integration for high-density resistive memory applications
144. Cycling-Induced Peak-Like Interface State Generation in Si-Nanocrystal Memory Devices
145. Comparison of tunneling current assisted by neutral and positive traps with finite ranged core-potential
146. A novel 2 T P-channel nano-crystal memory for low power/high speed embedded NVM applications
147. Improved performance of non-volatile memory with Au-Al2O3 core-shell nanocrystals embedded in HfO2 matrix
148. Effects of high-temperature O2 annealing on Al2O3 blocking layer and Al2O3/Si3N4 interface for MANOS structures
149. Effect of bandgap engineering on the performance and reliability of a high-k based nanoscale charge trap flash memory
150. Effect of high temperature annealing on the performance of MANOS charge trapping memory
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