461 results on '"Kuroda, Tadahiro"'
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102. Architecture design of versatile recognition processor for sensornet applications
103. BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS
104. A 6Gb/s rotatable non-contact connector with high-speed/I2C/CAN/SPI interface bridge IC
105. A 400-mV 2.4-GHz frequency-shift keying transmitter using a capacitor switch across a transformer for a wide tuning range voltage-controlled oscillator
106. System integration in a package for cloud and edge
107. An image sensor/processor 3D stacked module featuring ThruChip interfaces
108. Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface
109. An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips
110. Basic study of non-contact connector for high-speed space cable transmission: Space fibre, short paper
111. Low-energy algorithm for self-controlled Wireless Sensor Nodes
112. Deep learning application trial to lung cancer diagnosis for medical sensor systems
113. Hydrophilic Bonding of SiO2/SiO2 and Cu/Cu using Sequential Plasma Activation.
114. A 1 Tb/s/mm2 inductive-coupling side-by-side chip link
115. Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces
116. A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver
117. A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver
118. Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces
119. Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO
120. Analytical thruchip inductive coupling channel design optimization
121. [Paper] 3D Stacked Imager featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer
122. Hydrophilic Bonding of SiO2/SiO2and Cu/Cu using Sequential Plasma Activation
123. 3D integration using inductive coupling and coupled resonator (Invited)
124. Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers
125. Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation
126. Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer
127. Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory
128. 10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver
129. An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS
130. 24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%
131. Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface
132. A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel
133. Transponder Array System with Universal On-Sheet Reference Scheme for Wireless Mobile Sensor Networks without Battery or Oscillator
134. Relay Transmission Thruchip Interface with Low-Skew 3D Clock Distribution Network
135. Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration
136. Circuit and device interactions for 3D integration using inductive coupling
137. Low-Power Digital Circuit Design
138. Low Power CMOS VLSI Design
139. Body Biasing
140. A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package
141. A 300 mV sub-threshold region 2.4 GHz voltage-controlled oscillator and frequency divider with transformer technique for ultralow power RF applications
142. 30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%
143. F2: 3D stacking technologies for image sensors and memories
144. An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique
145. Low-latency wireless 3D NoCs via randomized shortcut chips
146. Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage
147. FPGA-Based Design for Motion Vector Estimation Exploiting High-Speed Imaging and Its Application to Motion Classification with Neural Networks
148. A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler
149. Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions
150. A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface
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