101. GraphSAR
- Author
-
Yu Wang, John Wawrzynek, Tianhao Huang, Huazhong Yang, and Guohao Dai
- Subjects
010302 applied physics ,High energy ,Speedup ,Computer science ,Computation ,Energy reduction ,02 engineering and technology ,Parallel computing ,01 natural sciences ,Graph ,020202 computer hardware & architecture ,Long latency ,Resistive random-access memory ,0103 physical sciences ,Memory architecture ,0202 electrical engineering, electronic engineering, information engineering - Abstract
Large-scale graph processing has drawn great attention in recent years. The emerging metal-oxide resistive random access memory (ReRAM) and ReRAM crossbars have shown huge potential in accelerating graph processing. However, the sparse feature of natural graphs hinders the performance of graph processing on ReRAMs. Previous work of graph processing on ReRAMs stored and computed edges separately, leading to high energy consumption and long latency of transferring data. In this paper, we present GraphSAR, a sparsity-aware processing-in-memory large-scale graph processing accelerator on ReRAMs. Computations over edges are performed in the memory, eliminating overheads of transferring edges. Moreover, graphs are divided considering the sparsity. Subgraphs with low densities are further divided into smaller ones to minimize the waste of memory space. According to our extensive experimental results, GraphSAR achieves 4.43x energy reduction and 1.85x speedup (8.19x lower energy-delay product, EDP) against previous graph processing architecture on ReRAMs (GraphR [1]).
- Published
- 2019
- Full Text
- View/download PDF