Search

This paper presents the design and post-layout characteristics of a differential capacitance based inertial accelerometer This includes a MEMS based mechanical sensing element and a CMOS charge amplifier, which is the first stage of a readout circuit. The mechanical sensor is designed according to the SOIMUMPs fabrication process technology, and the readout circuit targeted AMS 0.35um technology. Post layout simulations indicated a +/-5G dynamic range, a maximum bandwidth of 1.58 kHz, non-linearity of 0.077% and a resolution of 10.5 uG/Hz^0.5. The readout circuit charge amplifier is fully differential and incorporated in a switched capacitor (SC) topology with CDS.

With the ever more pressing issue arising from the phenomenon known as the death or slowdown of Moore’s Law and the Dennard Scaling, compute performance has not been increasing at the rate the industry had been accustomed to over the decades [7]. This has prompted a shift from mostly homogeneous compute architectures to increasingly heterogeneous ones [1]. As these systems become increasingly complex, manual tuning and management of these heterogeneous resources becomes unfeasible. In this paper, we propose a runtime mechanism for automatic reconfigurable resource management that will enable a hypothetical flow for combined hardware and software compilation.

Decision trees are often preferred when implementing Machine Learning in embedded systems for their simplicity and scalability. Hoeffding Trees are a type of Decision Trees that take advantage of the Hoeffding Bound to allow them to learn patterns in data without having to continuously store the data samples for future reprocessing. This makes them especially suitable for deployment on embedded devices. In this work we highlight the features of an HLS implementation of the Hoeffding Tree. The implementation parameters include the feature size of the samples (D), the number of output classes (K), and the maximum number of nodes to which the tree is allowed to grow (Nd). We target a Xilinx MPSoC ZCU102, and evaluate: the design's resource requirements and clock frequency for different numbers of classes and feature size, the execution time on several synthetic datasets of varying sample sizes (N), number of output classes and the execution time and accuracy for two datasets from UCI. For a problem size of D3, K5, and N40000, a single decision tree operating at 103MHz is capable of 8.3x faster inference than the 1.2GHz ARM Cortex-A53 core. Compared to a reference implementation of the Hoeffding tree, we achieve comparable classification accuracy for the UCI datasets.

This paper presents results of a study of the performance of several base classifiers for recognition of handwritten characters of the modern Latin alphabet. Base classification performance is further enhanced by utilizing Viterbi error correction by determining the Viterbi sequence. Hidden Markov Models (HMMs) models exploit relationships between letters within a word to determine the most likely sequence of characters. Four base classifiers are studied along with eight feature sets extracted from the handwritten dataset. The best classification performance after correction was 89.8%, and the average was 68.1%