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A wideband cellular RF receiver for multi-band carrier aggregation employing a current-efficient wideband low noise amplifier and a frequency-band switchable transformer is demonstrated in a 14nm FinFET CMOS technology. The proposed wideband low-noise amplifier can support multiple-channel RF signals for intra-band carrier aggregation with high performance and low DC current consumption. Moreover, the frequency-band switchable transformer is used to support a size-efficient receiver up to 5 carrier components carrier aggregation. The receiver operates at frequencies between 0.6 to 2.7 GHz. The receiver has conversion gain more than 62 dB and noise figure less than 5 dB at all carrier aggregation combinations.

A novel receiver architecture based on frequency translation is proposed in this paper. The receiver treats a mono-lithically integrated time-varying transmission line (TVTL) as a capacitive mixer with minimum insertion loss and noise penalty, placing it in the first stage before a fixed, narrow bandpass filter. By varying the LO/carrier frequency of the TVTL mixer, the complete received frequency band is shifted so that the desired band can be selected with a fixed bandpass filter, without suffering signal-to-noise ratio (SNR) degradation that usually occurs in a conventional heterodyne receiver with a mixer at its first stage. Measured results of both the TVTL MMIC and the testbed of the frequency translational receiver validate the proposed concept and confirm its potential for applications in software defined radios.

This paper presents a 65 nm CMOS 25–30 GHz hybrid beamforming receiver with eight antenna inputs and two baseband output streams. The receiver uses the Cartesian-Combining architecture, which is introduced for two baseband streams. Each antenna signal is complex-weighted independently and combined with weighted signals from other antennas prior to downconversion. Each RF-domain complex weight is realized using a pair of 5-bit digitally controlled VGA's. The receiver achieves 34 dB conversion gain, 7.3 dB minimum noise figure, and 5 GHz of RF bandwidth while consuming only 27.5 mW power per antenna element (340 mW for the entire receiver). Two-element Cartesian-combining achieves a peak-to-null ratio of 20 dB. Use of mostly active phase shifting and combining approach made the design ultra-compact with 3.86 mm2 core area for entire 8-element 2-stream receiver.

A concurrent, tunable, tri-band, single chain radio receiver for 5G radio access networks is evaluated. The three concurrent bands are independently tunable over a frequency range from 600 MHz to 2.7 GHz. A hardware-in-the-loop test-bed provides a system level evaluation of the proposed receiver using direct RF digitization. The test-bed emulates a 5G heterogeneous network supporting three wideband, simultaneous connections. By measuring the receiver EVM, we demonstrate sufficient isolation between concurrent bands achieving 60 MHz of aggregated bandwidth as well as strong resilience to adjacent blockers.

Digital Beamforming (DB) in satellite communication (SATCOM) has drawn significant attention in recent years. DB design is flexible and adaptive among frequencies, bandwidths, and interferences. In this work, we design a cognitive radio testbed for SATCOM for digital beamforming design and implementation. The testbed is capable of simultaneously capturing signals from multiple antennas. Considering the conditions of jamming or interference, the design implements spectrum detection and compressive sensing for channel condition monitoring in a real time. Using the analyzed jammer and interference information, the incoming signal can be moved into a different frequency where the channel is vacant or at least meets acceptable conditions. The beamforming design is also adaptive to the frequency where each beam is weighted differently for a given channel condition. In addition, the satellite antenna array is used to determine the signal direction of arrival (DoA), The DB is capable of forming the beam in the direction that avoids interference and jamming. Moreover, the detection of the jamming signal direction can help localize the jammer. In the testbed design, a Universal Software Radio Peripheral (USRP) is used as a radio frequency (RF) front end component and GNU radio connecting to computer as signal processing back end. The system architecture includes the transponder receiver. And a USRP ×310 with twinRx receiver is capable of obtaining multiple copies of the signal captured by multiple receiving antennas.

This paper proposes an instantaneous frequency measurement (IFM) receiver structure for electronic support measure (ESM) systems. The performance of instantaneous frequency (IF) measurement improves as the IFM receiver delay increases. However, it is observed that the increasing delay introduces ambiguity to the IF measurement In order to resolve the ambiguity, an algorithm which uses the IFM receiver blocks of different delays in parallel is proposed. The IF measurement performance of the proposed IFM receiver is analyzed for different modulation types, pulse widths and signal to noise ratios.

The design of a 1–8 Gb/s optical wireless communication (OWC) dual-mode receiver is presented in this paper. The transimpedance amplifier (TIA) based reconfigurable receiver implements a high-sensitivity (HSS) mode to enable 1Gb/s OWC link over long distance, while a high speed (HSD) mode to enable up to 8Gb/s OWC link over short distance. In the HSS mode, the receiver is designed for high gain and low noise. In the HSD mode, the receiver is optimized for wide bandwidth. The receiver is designed in TSMC 65 nm CMOS technology. Post layout simulation results show that the receiver achieves maximum bandwidth of 5 GHz with 88 dB transimpedance gain in HSD mode. The receiver also achieves 0.7 GHz bandwidth with 125 dB transimpedance gain in HSS mode. The total input referred current noise is 60 nArms and 1.2 μΑ rms at 1 Gb/s and 8 Gb/s respectively. The overall receiver dissipates 34mW at 1.2 V supply voltage.

An effective and non-destructive receiver characterization method is proposed in this paper. This method can extract unknown third party device bandwidth information. It enables accurate end to end signal integrity study from transmitter to receiver.

This paper presents a MICS/ISM band receiver for ultra-low-power applications with a passive RF front-end. A shunt passive mixer along with low input capacitance amplifiers is introduced to decrease the large load capacitor and minimize power consumption of the Local Oscillator (LO) buffers without significant noise figure (NF) degradation. Measurement results show that the receiver consumes 89 μW from 1 V supply voltage with a NF of 7.5 dB and a voltage gain of 47.6 dB. S11

This paper presents a 1024-QAM OFDM signal capable WLAN receiver in 65 nm CMOS technology. Thermal noise-based IQ frequency-independent mismatch correction and IQ frequency-dependent mismatch correction with baseband loopback are proposed for the self-calibration in the receiver. By using proposed calibration method, neither received external signal nor RF loopback are necessary and the residual IQ mismatch of TXBB can be removed. The measured image rejection ratio of the self-calibration is −56.3 dB. The receiver achieves the extremely low EVM of −37.1 dB even with wide channel bandwidth of 80 MHz and has the ability to receive the 1024-QAM signal. The result indicates that the receiver is extendable for the 802.11ax compliant receiver that supports a higher density modulation scheme of MIMO.

Achieving wireless power transfer through airborne acoustic/ultrasonic waves has been previously shown to be a feasible alternative when the charging distance is above several times the transducer size. In order to further increase the receiver efficiency, constructing the receiver out of an array of transducer elements to increase the receiver effective area is desirable. In this work, a study on the power combining through series or parallel interconnections of the receiver elements is done to understand the benefits of both cases and the conditions required to maximize receiver efficiency, with measurements and modeling results presented. With a seven element receiver array, a factor of 4.25 increase in receiver efficiency was achieved compared to only using the receiver center transducer.

Cognitive radio (CR) is the key technology that provides to use frequency spectrum effectively. Spectrum sensing, a critical function of CR, detects spectrum holes. Energy based detection (ED) is the most preferred spectrum sensing technique by researchers because it only requires the energy of received signals. The sensing performance of the ED is mainly based on the wireless communication channel. The channel environment is continuously varying in time. It is therefore difficult to detect primary user's signal with a fixed threshold when the energy of received signal is affected by disturbances such as fading, shadowing, noise and interference. In this study, ET sensing performance based on adaptive threshold value in cognitive radio with MIMO technology has been investigated in terms of the number of antennas at the receiver and the transmitter side, the number of multipath, the speed of mobile receiver and modulation type parameters. The simulation results show that the adaptive threshold value provides better detection performance than the fixed threshold value especially at low SNRs.

We present a low power superheterodyne receiver architecture for wirelessly powered backscatter tags and sensors. This receiver architecture eliminates the power hungry local oscillator (LO) from the receiver by leveraging an external continuous wave (CW) carrier as both power source and LO source. The superheterodyne intermediate frequency (IF) is obtained from the output of a custom designed passive two-port mixer which simultaneously serves as an energy harvester. We have validated the proposed architecture at 2.4 GHz in benchtop proof-of-concept testing by successfully receiving and decoding Bluetooth Low Energy (BLE) advertising packets, which use GFSK modulation at 1 Mbps.

This work presents a 980μW direct-conversion BLE receiver at a 1V supply, employing current-reuse and subthreshold techniques. The receiver has a measured noise figure of 5.2dB, integrated from 10kHz to 1MHz, that corresponds to a sensitivity of −95.8dBm. At a receiver gain of 47dB, an HP3 of −19.7dBm has been measured. The LO integrated phase noise at 2.4GHz is 0.83° with LO spot phase noise of −119.9dBc/Hz at 3MHz frequency offset. The PLL is compacted inside the VCO inductor and has LC-VCO with a tuning range of 4.55GHz to 5.15GHz. Multiple μW-level feedback control loops are used in the design to make it robust over PVT variation. The prototype is implemented in a 40nm LP CMOS process occupying a silicon area of 0.7mm2. To the best of our knowledge, the proposed receiver achieves the highest reported figure of merit among the BLE receivers published in the literature.

Radio receiver, as an extensively feasible modern technology, has been widely applied in all fields of military and civil. It is mainly to demodulate all kinds of required signals with strong interference and noise. Based on intermediate frequency (IF) software radio receiver test platform, the data transmission approach combining direct memory access (DMA) and multichannel buffered serial port (McBSP) was studied and the parallel operation of data transmission and data processing was realized. The method proposed for signal transmission and processing shows strong universality and can be used in other relevant fields.

A 433 MHz ?104 dBm OOK/ASK receiver with offset-peak-detecting demodulation technique has been proposed and implemented in 0.18-µm CMOS process in this paper. The offset-peak-detecting technique enhances the receiver robustness under the existence of interferences and thus improves the sensitivity. This technique also guarantees a prompt setting process of the data slicer. A passive-mixer based front-end with low noise figure and high conversion gain is employed in the receiver to reduce the noise figure. The LO signal is generated by a 433 MHz SAW oscillator. An active balun is used to convert the single-ended LO signal to differential signal which is necessary for the performance of the mixer. The receiver achieves a sensitivity of ?104 dBm and a dynamic range of 95 dB at the data rate of 20 kbps. The receiver consumes a quiescent current of 4 mA under the supply voltage from 2.1 to 3.3 V.

This paper presents a process-variation tolerant, continuously channel-adaptive wireless front-end architecture and related adaptation algorithms to allow a radio-frequency transceiver to function with minimum power at all channel conditions and manufacturing process corner. Current wireless transceiver front-ends are designed for worst case channel conditions and a limited degree of post manufacture tuning is performed to compensate for process variations. It is shown how the proposed architecture can result in significant power savings over current practice without compromising system-level bit-error rate (while keeping the end-user experience unaffected). In contrast to traditional wireless circuits with limited tunability, such a zero-margin design is achieved by close loop adaptation of the wireless front-end circuits to ensure that they only consume the minimum power and deliver just enough performance (and not any more) for any channel condition. The adaptation methodology is applied to a WLAN receiver design and hardware measurement data for an adaptive receiver is presented showing a > 3 × power improvement under best case channel conditions.

In the paper a cost-effective input block of the SDR receiver for 0.9 2.4GHz frequency band built of capacitive- tuned selective amplifier and broadband Vivaldi antenna is presented. The applied selective amplifier consists of three identical sections of tunable filters and two stages of monolithic broadband amplifiers. The single filter section proposed by the authors, due to its ability to absorb parasitic inductances of varicap diodes, simplifies usage of encapsulated varicap diodes in design of tunable in broad band selective filters dedicated to input stages of the receivers. Moreover, proposed filter section has small variation of in-band insertion loss in comparison to varicap-tuned filters built of coupled transmission lines which are commonly applied in input blocks of the microwave receivers. The described selective amplifier could be easily integrated on a single substrate with the Vivaldi antenna which is a cost effective way of fabrication of the tunable in broad band input block of a receiver that has desired gain, selectivity and directivity of the antenna. Keywords—software-defined radio, radio receiver, broadband antenna, tuned filter

In a digital communication system, the analog signal that the receiver receives with its radio frequency front end is converted into digital format by using the analog-to-digital converter A/D converter, ADC. Quantisation takes place during the conversion from continuous amplitude signal to discrete amplitude signal, leading inevitably to losses in information which are dependent on the number of bits that is used to represent each sample. Although employing a higher bit resolution reduces the quantisation error, a higher power dissipation of the ADC is incurred at the same time. This trade-off is essential to the energy efficiency of the receiver, which is commonly measured by the number of information bits conveyed per consumed Joule of energy. We investigate, in this work, the adaptation of ADC resolutions of a multi-antenna receiver based on instantaneous channel knowledge, with the goal of maximising receiver energy efficiency. The formulated optimisation is a combinatorial problem, and we propose several algorithms which yield near-optimal solutions. Results from numerical simulations are presented and analysed, which provide guidelines to operation and deployment of the system. Copyright © 2014 John Wiley & Sons, Ltd.

In this paper, we describe a new digital receiver developed for a 1.3-GHz range imaging atmospheric radar. The digital receiver comprises a general-purpose software-defined radio receiver referred to as the Universal Software Radio Peripheral 2 (USRP2) and a commercial personal computer (PC). The receiver is designed to collect received signals at an intermediate frequency (IF) of 130 MHz with a sample rate of 10 MS s−1. The USRP2 digitizes IF received signals, produces IQ time series, and then transfers the IQ time series to the PC through Gigabit Ethernet. The PC receives the IQ time series, performs range sampling, carries out filtering in the range direction, decodes the phase-modulated received signals, integrates the received signals in time, and finally saves the processed data to the hard disk drive (HDD). Because only sequential data transfer from the USRP2 to the PC is available, the range sampling is triggered by transmitted pulses leaked to the receiver. For range imaging, the digital receiver performs real-time signal processing for each of the time series collected at different frequencies. Further, the receiver is able to decode phase-modulated oversampled signals. Because the program code for real-time signal processing is written in a popular programming language (C++) and widely used libraries, the signal processing is easy to implement, reconfigure, and reuse. From radar experiments using a 1 - μ s subpulse width and 1-MHz frequency span (i.e., 2-MHz frequency bandwidth), we demonstrate that range imaging in combination with oversampling, which was implemented for the first time by the digital receiver, is able to resolve the fine-scale structure of turbulence with a vertical scale as small as 100 m or finer.

The millimeter-wave transceiver front-end as a subsystem of high-frequency component is an important part of the radar, navigation, electronic warfare and communication systems. The millimeter receiver front-end developed herein, using the second harmonic mixer, reduces the frequency of the local oscillator. Using the bottom surface outlet ladder microstrip - waveguide structure, it strengthens the structure. Test results show that the developed front-end receiver has gain of 25dB and the transmit band is 35.5-36GHz.

With the rapid development of wireless communications, there are more and more ​​stringent requirements on the wireless receiver, such as low power consumption, high reliability, low price, as well as smaller size. The design of RF receiver is the key to achieve this goal. According to the actual needs of the project, a double conversion IF receiver is designed. At first, the high frequency signal is changed to a higher IF, and the second output is a zero-IF signal. Experimental results show that the receiver has 100dB gain and a flat bandwidth.

An ultra-low-energy Binary Frequency Shift Keying (BFSK) receiver is proposed. It features improved in-band interference tolerance by chirping the transmission frequency. To reduce the receiver power consumption, a novel three-phase passive mixer along with a three stage digitally controlled ring oscillator is proposed, while still allowing quadrature detection. A mixer-first direct conversion receiver architecture moves the required gain to lowest frequency and lowest bandwidth to reduce power consumption. A low power flip-flop based BFSK demodulator is proposed that reduces the baseband power further. The receiver is designed and fabricated in a 65 nm complementary metal-oxide-semiconductor process. It consumes 219 μW from 1.2 V power supply, while having a sensitivity of -70 dBm for a bit error rate of 0.1% at 2.4 GHz. Except the off-chip 64 MHz clock generation, the total receiver requires 27 pJ/bit. Using a chirped clock spreading of 360 MHz and chirp repetition rate of 1 MHz, it can tolerate up to -8 dB signal to interference ratio for all interferer frequencies. This is 13.5 dB better than previously reported in literature and 12 dB better than ideal noncoherent BFSK receiver interference robustness.

Recently, the concept of software radar has been proposed. The wide application of the digital technology has become a trend. With the development of modern radar system, the system requires higher and higher performance to the radar receiver. The technology of digital receiver has become an effective implementation method for high-accuracy and wide-band radar receiving systems. However, most of the digital receiver can only receive one wide-band signal with one center frequency. A multi-frequency digital receiver which can receive several center frequencies of signal simultaneously [1] is discussed in this paper. We also describe the theory and the design about digital receiver, introduce digital downconversion (DDC), FIR and decimation, digital beam forming and channel calibration. Based on the research, a realization of multi-frequency digital receiver based on FPGA is put forward. The analysis and simulation is made and the result shows the design of great performance.

This paper presents the analysis, design, and measurements of a 2.5-GHz receiver front-end in a 40-nm CMOS technology. The front-end utilizes RLC-resonator quality factor (Q) boosting and four-phase N-path filtering to improve the blocker filtering capabilities of the low-noise amplifier (LNA). Systematic analysis is performed in order to obtain a thorough design approach. Particular attention is paid to the passive mixer switches in the RLC case, for which we show that minimum switch resistance does not provide best noise figure (NF), nor best relative blocker attenuation. Moreover, the N-path filter extends the stable operating region of a Q-boosted LNA, and adding a noisy Q-boosting circuit can actually improve the receiver NF in practical realizations. The experimental CMOS front-end is flip-chip packaged, and a parasitic-aware input matching method for the electrostatic-discharge-protected LNA is proposed, analyzed, and verified. In nominal operation, the programmable front-end achieves a measured gain of 39 dB, an NF of 3.5 dB, and an out-of-band input-referred third order intercept point of > 0 dBm, while consuming 48 mA from a 1.1-V supply.

A 2.4-GHz current-reused receiver front end is presented in this brief. Instead of using the traditional stack-on current-reusing scheme that compresses the voltage headroom, the proposed front end employs a lateral current-shunt branch to share most of the dc bias current of the transconductance transistors in an LNA and a mixer. To prevent the signal interaction between the two modules, an LC tank is inserted into the current-reusing path to cut off the radio-frequency signal path between the LNA and the mixer. The IF signal blocking is realized by inserting a cascode transistor that provides large impedance for the IF signal from the mixer. Theory analysis and simulation results indicate that the current-reusing structure improves the noise performance and only a small impact on the voltage gain. A prototype of the proposed front end is designed and fabricated in the 130-nm CMOS process. Measurement results indicate that the front end achieved a conversion gain of 25 dB, a double-sideband noise figure of 3.5 dB, and a third-order input intercept point (IIP3) of -13 dBm at an input frequency of 2.4 GHz. The dc consumption of the front end is 3 mA under a supply voltage of 1.2 V.

In order to achieve 600 meters radio frequency communication and 2-10 meters serial cable communication between remote controller and parking heater, the paper designed the hardware of remote controller and vehicle receivers. Select CC1100 as radio frequency chip, select PIC16F914, ATmega16L as remote control and receiver SPI control chip, select CE8301, LM117 as remote control and receiver power supply module. Finally, the circuit diagram of the receiver and remoter are designed.

A software-defined radio receiver is presented, operating from 400 MHz to 6 GHz. The split front-end architecture has a low-band RF path (0.4-3 GHz) using 8-phase passive mixers and a high-band RF path (3-6 GHz) using 4-phase passive mixers. DC-offset, IIP 2, and harmonic recombination for harmonic rejection may be calibrated to achieve true wideband specifications. A 0.5-50 MHz tunable baseband bandwidth implies compliance with LTE and future standards. Despite having a 0.9 V supply, the receiver architecture ensures high out-of-band linearity. The 0.6 mm 2 , 28 nm CMOS receiver achieves down to 1.8 dB NF, >+3 dBm out-of-band IIP3, >70 dB calibrated HR3/5 and >+80 dBm calibrated IIP2. It tolerates 0 dBm blockers at 80 MHz offset with a blocker NF of 10 dB for a power consumption of 20-40 mW.

This paper presents a zero-IF CMOS RF receiver, which supports three channel bandwidths of 5/10/40MHz for LTE-Advanced systems. The receiver operates at IMT-band of 2,500 to 2,690MHz. The simulated noise figure of the overall receiver is 1.6 dB at 7MHz (7.5 dB at 7.5 kHz). The receiver is composed of two parts: an RF front-end and a baseband circuit. In the RF front-end, a RF input signal is amplified by a low noise amplifier and Gm with configurable gain steps (41/35/29/23 dB) with optimized noise and linearity performances for a wide dynamic range. The proposed baseband circuit provides a -1 dB cutoff frequency of up to 40MHz using a proposed wideband OP-amp, which has a phase margin of 77° and an unit-gain bandwidth of 2.04 GHz. The proposed zero-IF CMOS RF receiver has been implemented in 0.13-μm CMOS technology and consumes 116 (for high gain mode)/106 (for low gain mode) mA from a 1.2 V supply voltage. The measurement of a fabricated chip for a 10-MHz 3G LTE input signal with 16-QAM shows more than 8.3 dB of minimum signal-to-noise ratio, while receiving the input channel power from -88 to -12 dBm.

We propose a new receiver architecture for multi-user massive MIMO system that uses one radio frequency (RF) chain per user. We show that the proposed receiver architecture can provide virtually the same performance as the conventional receiver architecture which requires one RF chain per antenna. The basic idea is to perform the necessary signal processing in the RF domain and then down convert the processed information to the baseband to detect the intended user data. Since the number of antennas in multi-user massive MIMO receiver is much larger than the number of users, the proposed architecture can significantly reduce the hardware complexity, size, and power consumption over the conventional architecture.

In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave (mmW) band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier (LNA) with inter-stage peaking technique, a single-balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.11ad standard for next generation high speed Wi-Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.5dBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.

For the development of highly integrated, flexible and low-cost cognitive radio (CR) devices, simple transceiver architectures, like direct-conversion receiver, are expected to be deployed and provide viable radio frequency (RF) spectrum sensing solutions for practical implementation. Yet, this can be very challenging task especially if spectrum sensing and down-conversion are conducted over multiple RF channels simultaneously for improved efficiency in channel scans. Then, the so-called dirty RF problem that degrades link performance of traditional transmission systems starts to be influential from spectrum sensing perspective as well. The unavoidable RF impairments, e.g., oscillator phase noise in direct-conversion receiver, could generate crosstalk between multiple channels that are down-converted simultaneously, and thus considerably limit the spectrum sensing capabilities. Most of the existing spectrum sensing studies in literature assume an ideal RF receiver and have not considered such practical RF hardware problem. In this article, we study the impact of oscillator phase noise on energy detection (ED) based spectrum sensing in multi-channel direct-conversion receiver scenario. With complex Gaussian primary user (PU) signal models, we first derive the detection and false alarm probabilities in closed-form expression. The analytical results, verified through extensive simulations, show that the wideband multi-channel sensing receiver is very sensitive to the neighboring channel crosstalk induced by oscillator phase noise. More specifically, it is shown that the false alarm probability of multi-channel energy detection increases significantly, compared to the ideal RF receiver case. The exact performance degradation depends on the power of neighboring channels as well as statistical characteristics of the phase noise in the deployed receiver. In order to prevent such performance degradation in spectrum identification, an enhanced energy detection technique is proposed. The proposed technique calculates the leakage power from neighboring channels for each channel and improves the sample energy statistics by subtracting this leakage power from the raw values. An analytical expression is derived for the leakage power which is shown to be a function of power spectral levels of neighboring channels and 3-dB bandwidth of phase noise process. Practical schemes for estimating these two quantities are discussed. Extensive computer simulations show that the proposed enhanced detection yields false alarm rates that are very close to those of an ideal RF receiver and hence clearly outperforms classical energy detection.

Impulse radio is a low-complexity ultra-wideband system which is suitable for highly dispersive multipath channel. In this paper, we propose a random correlation-based receiver for impulse radio communications. The proposed receiver correlates the received pilot symbols with the randomly generated base functions according to channel statistics and forms the detection template by combining several base functions which have larger correlation coefficients with the pilot symbols. The proposed receiver demodulates the received signal by employing a symbol rate sampling. Computer simulation results have shown that the proposed receiver outperforms the conventional correlator-based receiver, compressive sensing correlator-based receiver, weighted energy detector and autocorrelation receiver.

RF front-end is an important part of the communication system. It realizes the functions such as low noise amplifier application, filtering and mixing, completes the conversion between the IF signal and the RF signal, and ensures effective communication system flexibility and versatility. In the paper, according to the superheterodyne structure, a receiver RF front-end has been designed. The total gain of the link circuit is more than 100 dB, with 50 dB AGC range, the center frequency is 750 MHz with 100MHz bandwidth, local oscillator (LO) signal with frequency 935MHz is generated by PLL and the stability is-82dBc/Hz@1KHz.

A software-defined radio (SDR) wireless receiver leveraging discrete-time (DT) RF signal processing is introduced. The proposed DT signal processor, which applies switched capacitor techniques to radio frequencies, achieves harmonic rejection, image rejection, and frequency translation simultaneously. A frequency tunable high-Q 2nd-order bandpass input impedance is synthesized by the DT RF signal processor, which enhances the front-end interference rejection and frequency selectivity. A proof-of-concept SDR receiver prototype, including a 65 nm LP CMOS chip and a custom designed board, is presented. The highly programmable chip allows independent control of individual block parameters and bias operating points for optimum performance under various signal scenarios. The 0.5-to-3 GHz SDR receiver achieves out-of-band IIP3 > 11 dBm, IIP2 > 46 dBm, uncalibrated 3rd and 5th order harmonic rejection exceeding 46 dB and 51 dB, respectively, and can handle up to -5 dBm blockers with less than 5 dB degradation in signal-to-noise ratio (SNR) when the blocker offset frequency is 10 times the signal bandwidth irrespective of the center frequency.

The main research content of this article is to design a direct sequence spread spectrum communication system based on software radio technology. In this paper, design of spread spectrum receiver system directly to intermediate frequency sampling signal processing, after internal processing directly output transmission baseband signal information.

Power line communications (PLC) has been drawing considerable interest in recent years due to the growing interest in smart grid implementation. Specifically, network control and grid applications are allocated the frequency band of 0-500 kHz, commonly referred to as the narrowband PLC channel. This frequency band is characterized by strong periodic noise which results in low signal to noise ratio (SNR). In this work we propose a receiver which uses frequency shift filtering to exploit the cyclostationary properties of both the narrowband power line noise, as well as the information signal, digitally modulated using orthogonal frequency division multiplexing. An adaptive implementation for the proposed receiver is presented as well. The proposed receiver is compared to existing receivers via analysis and simulation. The results show that the receiver proposed in this work obtains a substantial performance gain over previously proposed receivers, without requiring any coordination with the transmitter., Accepted to the ieee transactions on communications

A receiver architecture suitable for coexistence applications is presented. The receiver features an auxiliary path to deflect blockers away from the main receiver without disturbing the desired received signal. The sub-2-dB noise-figure (NF) receiver addresses the coexistence blocking issues without compromising the performance, achieving comparable NF and blocker tolerance to the state-of-the-art. Implemented in 40 nm CMOS, the entire receiver including the VCO and synthesizer drains 10 mA of battery current.

An efficient of the inter carrier interference (ICI) cancellation in the adaptive receiver using orthogonal frequency division multiplexing system by two path conjugate transmission. At the receiver side the phase rotated conjugate cancellation (PRCC) concept is used and only one of the phase rotation is employed on the transmit path and two of the phase rotation is employed on the two of the receiver path .The main objective is to maximize the carrier-to-interference ratio and signal to noise ratio to achieve a high spectral efficiency using the fast least mean square algorithm to improve the bit error rate performance. The carrier frequency offset occurs in the mobile environment due to Doppler effects. Here the OFDM is used because it is highly sensitive to the carrier frequency offset.

This paper presents the concept, design and analysis for a visible light communications receiver utilising the angular and spatial diversity in order to achieve full mobility and protection from signal blocking in a typical home/office environment. The proposed receiver uses seven sub-receivers, each dedicated to an independent viewing angle and direction. Employing selection combining, the receiver with the strongest signal is used for the communications channel. Full performance evaluation and numerical analysis of the proposed system have been performed in MATLAB and compared to that of a single receiver. The received power, impulse response, corresponding signal-to-noise ratios and root-mean-square delay spread are also investigated. Copyright © 2014 John Wiley & Sons, Ltd.

Summarization: Scatter radio achieves communication by reflection and requires low-cost and low-power RF front-ends. However, its use in wireless sensor networks (WSNs) is limited, since commercial scatter radio (e.g. RFID) offers short ranges of a few tens of meters. This work redesigns scatter radio systems and maximizes range through non-classic bistatic architectures: the carrier emitter is detached from the reader. It is shown that conventional radio receivers may show a potential 3dB performance loss, since they do not exploit the correct signal model for scatter radio links. Receivers for on-off-keying (OOK) and frequency-shift keying (FSK) that overcome the frequency offset between the carrier emitter and the reader are presented. Additionally, non-coherent designs are also offered. This work emphasizes that sensor tag design should accompany receiver design. Impact of important parameters such as the antenna structural mode are presented through bit error rate (BER) results. Experimental measurements corroborate the long-range ability of bistatic radio; ranges of up to 130 meters with 20 milliwatts of carrier power are experimentally demonstrated, with commodity software radio and no directional antennas. Therefore, bistatic scatter radio may be viewed as a key enabling technology for large-scale, low-cost and low-power WSNs. Παρουσιάστηκε στο: IEEE Transactions on Communications

We demonstrate analytically a novel scheme to obtain polarization-independent operation in low-cost coherent OOK receivers, suitable for access networks. We move from a well-known phase-diversity receiver, exploiting a 3 × 3 coupler, three photodiodes, and basic analogue processing. If that receiver is modified to inject the local oscillator (or the signal) into two inputs with proper polarization states, we show, by both mathematical derivation and numerical simulations, that the resulting electrical signal can be polarization-independent; this is attained only if the frequency-detuning between the signal carrier and the local oscillator is high enough, so that intrinsic second order distortions can be spectrally isolated and suppressed by the low-pass filtering of the receiver.

This paper presents an ultra-low-power radio receiver implemented only with CMOS logic gates used as basic building blocks and proves its operation. The self-timed duty-cycled system is self-synchronized with the input radio signal, runs a noise-robust baseband detection and does not require any reference besides power supply. Based on S-OOK modulation, the 350-450 MHz digital radio RX occupies an area of 0.07 mm 2 in a 130 nm RFCMOS technology and achieves a 0.1% sensitivity of -63 dBm at 95 kbps, 380 MHz center frequency and 40 μW active power consumption at 1.1 V power supply. At 1.0 V it achieves -62 dBm sensitivity and 33 μW active power at ~ 0.1% error rate. The compact receiver, whose architecture is parametric and technology scalable, suits energy harvested and miniaturized biomedical applications. The paper also presents the potential advantages of asynchronous logic pulse radio and introduces an ad-hoc VHDL model demonstrating RTL-/gate-level accurate error-rate predictions capabilities based on digital simulation only, i.e., without requiring electrical-level co-simulation.

This paper presents an interference rejection full-band UWB receiver and fast hopping carrier generator for 3.1---10.6 GHz. This receiver enables 11 bands of operation by embedding a tunable notch filter to eliminate interferers in a 5 GHz wireless local area network. The carrier generator can cover 3.1---10.6 GHz within less than 9.5 ns. The receiver, based on the proposed multi-band OFDM standard, consists of a zero-IF receive chain and required system noise figure, the receiver linearity specifications of which are discussed in this paper. It consists of a single-ended low-noise amplifier (LNA), a down-conversion mixer, a low-pass filter (LPF), and a programmable gain amplifier with an IO buffer. The LNA employs a common-gate topology of the 1st stage with dual-resonant loads, a cascade amplifier of the 2nd stage for mid-band resonance, and a tunable notch filter. The down-conversion mixer adopts a single-balanced architecture with LO cancellation. The LPF is implemented based on an active RC topology, and implements a four-stage programmable gain amplifier. The receiver dissipates 49.3 mA from a 1.8 V power supply. The average voltage conversion gain of the receiver IC is 73.5 dB, and the system noise figure is 8.4 dB. Input P1dB increases from ?36.8 dBm at 4 GHz to ?30.5 dBm at 10.3 GHz. The attenuation is 8.5 dB, which is achieved in the interference rejection band at 5.2 GHz. It occupies an area of 0.98 × 3.3 mm2 including the bond pads.

In this paper, we proposed the 1-channel monopulse receiver which has the new configuration and described the operation procedures. Also, we compared and analyzed the proposal receiver and the general 3-channel monopulse receiver. As a result, it is apparent that the monopulse ratio of the proposal receiver is equal to that of the 3-channel monopulse receiver. The proposal receiver achieve the simple receiver configuration and the simple tracking procedures, as contrasted with the 3-channel monopulse receiver. Also, the proposal receiver has advantages in terms of size, weight, cost and power. Because the proposal monopulse receiver require 1-channel receiver and need not the signal processor in comparison with 3-channel monopulse receiver which require 3-channel receiver and need the signal processor.

An on/off keying receiver has been designed in 90 nm CMOS for low-power event-driven applications. Thanks to the synchronized-switching technique and power-efficient RF gain stages, this receiver achieves -86 dBm sensitivity (10 -3 bit error rate) at 10 kbps while consuming 123 µW from a 1 V supply. The receiver is highly scalable in data rates from 1 kbps at 64 µW to 100 kbps at 146 µW power consumption. The center frequency of the receiver can be also programmed from 780 to 950 MHz, covering different sub-GHz bands worldwide. The receiver is fully integrated, although an external SAW filter can be added for better selectivity.