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In the Intensive and Intermediate Care Units of healthcare centres, many sensors are connected to patients to measure high frequency physiological data. In order to analyse the state of a patient, the medical staff requires both appropriately presented and easily accessed information. As most medical devices do not support the extraction of digital data in known formats, medical staff need to fill out forms manually. The traditional methodology is prone to human errors due to the large volume of information, with variable origins and complexity. The automatic and real-time detection of changes in parameters, based on known medical rules, will make possible to avoid these errors and, in addition, to detect deterioration early. In this article, we propose and discuss a high-level system architecture, an embedded system that extracts the electrocardiogram signal from an analog output of a medical monitor, and a real-time Big Data infrastructure that integrate Free Software products. We believe that the experimental results, obtained with a simple prototype of the system, demonstrate the viability of the techniques and technologies used, leaving solid foundations for the construction of a reliable system for medical use, able to scale and support an increasing number of patients and captured data., En las unidades de cuidados intensivos e intermedios de centros de salud, muchos sensores están conectados a los pacientes para medir datos fisiológicos de alta frecuencia. Para analizar el estado de un paciente, el personal médico requiere información presentada de manera apropiada y de fácil acceso. Como la mayoría del equipamiento médico no admite la extracción de datos digitales en formatos conocidos, el personal médico completa formularios manualmente. Esta metodología es propensa a errores humanos debido al gran volumen de información, con orígenes y complejidad variable. La detección automática y en tiempo real de cambios en los parámetros, basados en reglas médicas conocidas, permitirá evitar estos errores y, además, detectar el deterioro de forma temprana. En este artículo, proponemos una arquitectura de alto nivel del sistema, un sistema embebido que extrae la señal del electrocardiograma de una salida analógica de un monitor médico, y una infraestructura Big Data de tiempo real que integra productos Software Libre. Creemos que los resultados experimentales, obtenidos con un prototipo, demuestran la viabilidad de las técnicas y tecnologías utilizadas, dejando sólidas bases para la construcción de un sistema confiable para uso médico, y capaz de escalar para soportar un número creciente de pacientes y datos capturados., Facultad de Informática

Robotic systems are generally used for grasping, carrying, holding, and many similar operations, typically in industrial applications. One of the most important components of robotic systems is robot grippers for the aforementioned operations, which are not only mission-critical but also represent a significant operational cost due to the time and expense associated with replacement. Grasping operations require sensitive and dexterous manipulation ability. As a consequence, tactile materials and sensors are an essential element in effective robot grippers; however, to date, little effort has been invested in the optimization of these systems. This study has set out to develop inexpensive, easily replaced pads, testing two different chemical compositions that are used to produce a tactile material for robot grippers, with the objective of generating cost, time, and environmental savings. Each tactile material produced has its specific individual dimension and weight. First, each of the materials under construction was tested under different constant pressures, and its characteristics were analyzed. Second, each tactile material was mounted on a two-fingered robot gripper and its characteristics. Material characteristics were tested and analyzed as regards their ability to grasp different sizes and types of objects using the two-fingered robot gripper. Based on the analysis of the results the most sensitive and cost-effective material for industrial type multi-fingered grippers was identified.

The Industrial Revolution 4.0 began with the breakthrough technological advances in 5G, and artificial intelligence has innovatively transformed the manufacturing industry from digitalization and automation to the new era of smart factories. A smart factory can do not only more than just produce products in a digital and automatic system, but also is able to optimize the production on its own by integrating production with process management, service distribution, and customized product requirement. A big challenge to the smart factory is to ensure that its network security can counteract with any cyber attacks such as botnet and Distributed Denial of Service, They are recognized to cause serious interruption in production, and consequently economic losses for company producers. Among many security solutions, botnet detection using honeypot has shown to be effective in some investigation studies. It is a method of detecting botnet attackers by intentionally creating a resource within the network with the purpose of closely monitoring and acquiring botnet attacking behaviors. For the first time, a proposed model of botnet detection was experimented by combing honeypot with machine learning to classify botnet attacks. A mimicking smart factory environment was created on IoT device hardware configuration. Experimental results showed that the model performance gave a high accuracy of above 96%, with very fast time taken of just 0.1 ms and false positive rate at 0.24127 using random forest algorithm with Weka machine learning program. Hence, the honeypot combined machine learning model in this study was proved to be highly feasible to apply in the security network of smart factory to detect botnet attacks.

When real-time systems are modeled as timed automata, different time scales may lead to substantial fragmentation of the symbolic state space. Exact acceleration solves the fragmentation problem without changing system reachability. The relatively mature technology of exact acceleration has been used with an appended cycle or a parking cycle, which can be applied to the calculation of a single acceleratable cycle model. Using these two technologies to develop a complex real-time model requires additional states and consumes a large amount of time cost, thereby influencing acceleration efficiency. In this paper, a complex real-time exact acceleration method based on an overlapping cycle is proposed, which is an application scenario extension of the parking-cycle technique. By comprehensively analyzing the accelerating impacts of multiple acceleratable cycles, it is only necessary to add a single overlapping period with a fixed length without relying on the windows of acceleratable cycles. Experimental results show that the proposed timed automaton model is simple and effectively decreases the time costs of exact acceleration. For the complex real-time system model, the method based on an overlapping cycle can accelerate the large scale and concurrent states which cannot be solved by the original exact acceleration theory.

Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm capable of high accuracy rates for a different range of applications. When arranged in a cascade structure, SVMs can efficiently handle problems where the majority of data belongs to one of the two classes, such as image object classification, and hence can provide speedups over monolithic (single) SVM classifiers. However, the SVM classification process is still computationally demanding due to the number of support vectors. Consequently, in this paper we propose a hardware architecture optimized for cascaded SVM processing to boost performance and hardware efficiency, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings. The architecture was evaluated for the application of object detection on $$800\times 600$$ resolution images on a Spartan 6 Industrial Video Processing FPGA platform achieving over 30 frames-per-second. Moreover, by utilizing the proposed hardware reduction method we were able to reduce the utilization of FPGA custom-logic resources by $$\sim $$ 30%, and simultaneously observed $$\sim $$ 20% peak power reduction compared to a baseline implementation.

The design of a fuzzy control system for a germination chamber for hydroponic crops is presented. The system measures humidity and temperature inside the chamber and, by means of a Sugeno type fuzzy controller embedded in an Arduino board, it generates control signals that are sent to a forced ventilation system and to the artificial lighting control system. Experiences were carried out with a germination chamber using this fuzzy control system. Lettuce seeds were sowed in the fuzzy control chamber and on a conventional culture tray, with the former yielding better growth results., Facultad de Informática

Owing to growing complexity and scale, safetycritical real-time systems are generally designed using the concept of mixed-criticality, wherein applications with different criticality or importance levels are hosted on the same hardware platform. To guarantee non-interference between these applications, the hardware resources, in particular the processor, are statically partitioned among them. To overcome the inefficiencies in resource utilization of such a static scheme, the concept of mixedcriticality real-time scheduling has emerged as a promising solution. Although there are several studies on such scheduling strategies for uniprocessor platforms, the problem of efficient scheduling for the multiprocessor case has largely remained open. In this work, we design a fluid-model based mixed-criticality scheduling algorithm for multiprocessors, in which multiple tasks are allowed to execute on the same processor simultaneously. We derive an exact schedulability test for this algorithm, and also present an optimal strategy for assigning the fractional execution rates to tasks. Since fluid-model based scheduling is not implementable on real hardware, we also present a transformation algorithm from fluid-schedule to a non-fluid one. We also show through experimental evaluation that the designed algorithms outperform existing scheduling algorithms in terms of their ability to schedule a variety of task systems. MOE (Min. of Education, S’pore) Accepted version

An autonomous fault-tolerant system (AFTS) is one that can reconfigure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate in order to maintain the original functionality. This capability makes an AFTS especially suitable for use in harsh environments, where traditional electronics technology is susceptible to failure. This article describes the contributions of the Reliable Reconfigurable Real-Time Operating System (R3TOS) for building an AFTS using currently available Xilinx partially-reconfigurable field-programmable gate arrays. Namely, this article discusses what R3TOS offers for developing durable, dependable, and real-time embedded systems to be used in rugged environments. In this context, the article presents an R3TOS-based inverter controller of a real-world railway traction system that is proven to recover from most of the errors injected without requiring any human intervention.

In most areas of machine learning, it is assumed that data quality is fairly consistent between training and inference. Unfortunately, in real systems, data are plagued by noise, loss, and various other quality reducing factors. While a number of deep learning algorithms solve end-stage problems of prediction and classification, very few aim to solve the intermediate problems of data pre-processing, cleaning, and restoration. Long Short-Term Memory (LSTM) networks have previously been proposed as a solution for data restoration, but they suffer from a major bottleneck: a large number of sequential operations. We propose using attention mechanisms to entirely replace the recurrent components of these data-restoration networks. We demonstrate that such an approach leads to reduced model sizes by as many as two orders of magnitude, a 2-fold to 4-fold reduction in training times, and 95% accuracy for automotive data restoration. We also show in a case study that this approach improves the performance of downstream algorithms reliant on clean data.

International audience; As the speed metric of Massively Parallel Multi-Processors System-on-Chip (MP2SoC) systems has increased over time, another metric has become more important: power consumption. Finding a tradeoff between power consumption and performance early in the design flow of MP2SoC systems in order to satisfy time-to-market is the design challenge of Electronic Design Automation (EDA) tools. This paper presents a Design Space Exploration (DSE) framework, named Energy-Aware Rapid Design of MP2SoC (EWARDS), aiming at exploring the performance and power capabilities of modern homogenous MP2SoC systems at design time using Model-Driven Engineering (MDE) techniques. The proposed framework extends the Modeling and Analysis of Real-Time and Embedded systems (MARTE)profile with power aspects of MP2SoC systems providing a high-level design entry. In addition, EWARDS integrates an energy-aware scheduler that strives to balance performance and energy savings by combining clustering scheduling algorithm with off-line Dynamic Voltage and Frequency Scaling (DVFS) power management techniques. © 2016 IEEE.

International audience; The profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) defines a framework forannotating non-functional properties of embedded systems. Inparticular, the SAM (Schedulability Analysis Model) sub-profileoffers stereotypes for annotating UML models with the neededinformation which will be extracted to fulfill a scheduling phase. However, SAM does not allow designers to specify data to beused in the context of adaptive systems development. In thisposition paper, we present the related works around thedevelopment of adaptive real-time and embedded systems anddiscuss why we seek to improve the meta-models of MARTE.

Cascade support vector machines (SVMs) are optimized to efficiently handle problems, where the majority of the data belong to one of the two classes, such as image object classification, and hence can provide speedups over monolithic (single) SVM classifiers. However, SVM classification is a computationally demanding task and existing hardware architectures for SVMs only consider monolithic classifiers. This paper proposes the acceleration of cascade SVMs through a hybrid processing hardware architecture optimized for the cascade SVM classification flow, accompanied by a method to reduce the required hardware resources for its implementation, and a method to improve the classification speed utilizing cascade information to further discard data samples. The proposed SVM cascade architecture is implemented on a Spartan-6 field-programmable gate array (FPGA) platform and evaluated for object detection on 800 × 600 (Super Video Graphics Array) resolution images. The proposed architecture, boosted by a neural network that processes cascade information, achieves a real-time processing rate of 40 frames/s for the benchmark face detection application. Furthermore, the hardware-reduction method results in the utilization of 25% less FPGA custom-logic resources and 20% peak power reduction compared with a baseline implementation.

This study proposes the use of abstract software models in order to meet the diversity of embedded platforms. A UML 2.0 Profile for Modeling Application and Platform of Embedded Software (called PROAPES) is proposed. Such profile is intended to generically describe the services provided by a system platform that makes use of an RTOS. In addition, this study presents a Model Transformation (MT) based on the PROAPES profile, named MT-PROAPES. In this way, MT-PROAPES uses a Platform Model (PM), created on the basis of the proposed profile (PROAPES), and performs a transformation named Platform Independent Model (PIM)-behavior into Platform Specific Model (PSM)-behavior. Thus, the generation of reusable model transformations that are adaptable to different platform models is possible, Facultad de Informática

Atento a que de acuerdo a la bibliografía se observa que si bien hay una mayor sistematización del proceso de desarrollo de software para sistemas embebidos, los principales problemas actuales son la falta de profesionales de este ámbito con formación específica en ingeniería de software y la falta de técnicas o metodologías especificas para el desarrollo de este tipo de software. Es por ello que se propone identificar y clasificar patrones de uso común en el desarrollo de sistemas embebidos; a fin de generar un catálogo de patrones de aplicación en sistemas embebidos como forma de contribuir a la formación en técnicas de ingeniería de software para los profesionales que se dedican al desarrollo de software de sistemas embebidos., Facultad de Informática

International audience; With the growing complexity of Real-Time Embedded Systems (RTES), there is a huge interest in using modeling languages such as the Unified Modeling Language (UML), and other Model-Driven Engineering (MDE) techniques targeting RTES system design. These approaches provide language abstractions for system design, allowing to focus on their relevant properties. Unfortunately, such approaches still suffer from several shortcomings including the lack of well-defined semantics. Therefore, it remains difficult to connect the MDE specification tools and the design tools that are based on formal grounds and well-defined semantics to perform analysis, validation or system synthesis for RTES. This paper presents a top-down RTES design flow aiming to reduce the gap between MDE and formal design approaches. We present the connection between a framework dedicated to the enrichment of modeling languages such as UML with formal semantics, a framework based on formal models of computation supporting validation by simulation, and a system synthesis tool targeting a flexible platform with well-defined execution services. Our purpose is to cover several system design phases from specification, simulation down to implementation on a platform. As a case study, a JPEG Encoder application was realized following the different design steps of the tool-chain.

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IP integration, which is one of the most important SoC design steps, requires taking into account communication and timing constraints. In that context, design and reuse can be improved using IP cores described at a high abstraction level. In this paper, we present an IP design approach that relies on three main phases: (1) constraint modeling, (2) IP constraint analysis steps for feasibility checking, and (3) synthesis. We propose a set of techniques dedicated to the digital signal processing domain that lead to an optimized IP core integration. Based on a generic architecture of components, the method we propose provides automatic generation of IP cores designed under integration constraints. We show the effectiveness of our approach with a DCT core design case study.

Instruction memoization is a promising technique to reduce the power consumption and increase the performance of future low-end/mobile multimedia systems. Power and performance efficiency can be improved by reusing instances of an already executed operation. Unfortunately, this technique may not always be worth the effort due to the power consumption and area impact of the tables required to leverage an adequate level of reuse. In this paper, we introduce and evaluate a novel way of understanding multimedia floating-point operations based on the fuzzy computation paradigm: performance and power consumption can be improved at the cost of small precision losses in computation. By exploiting this implicit characteristic of multimedia applications, we propose a new technique called tolerant memoization. This technique expands the capabilities of classic memoization by associating entries with similar inputs to the same output. We evaluate this new technique by measuring the effect of tolerant memoization for floating-point operations in a low-power multimedia processor and discuss the trade-offs between performance and quality of the media outputs. We report energy improvements of 12 percent for a set of key multimedia applications with small LUT of 6 Kbytes, compared to 3 percent obtained using previously proposed techniques.

Simulink is a powerful tool for Embedded Systems, playing a key role in dynamic systems modeling. However, far too little attention has been paid to quality of Simulink models. In addition, no research has been found linking the relationship between model complexity and its impact in the comprehension quality of Simulink models. The aim of this paper is to define a set of metrics to support the characterization of Simulink models and to investigate their relationship with the model comprehension property. For this study, we performed a controlled experiment using two versions of a robotic Simulink model — one of them was constructed through the ad hoc development approach and the other one through the re-engineered development approach. The results of the experiment show that the re-engineered model is more comprehensible than the ad hoc model. In summary, the set of metrics collected from each version of the Simulink model suggests an inverse relationship with the model comprehension, i.e., the lower the metrics, the greater the model comprehension., Facultad de Informática

A simulation-based approach to measuring the faultresilience of real-time systems is presented. Simulation is used to favor generality, comparability and make it possible to study the system taking into consideration its overall behavior instead of dealing only with worst-case scenarios. Tasks can be analyzed individually, which may be useful when they have different levels of criticality. The simulation procedure is efficient since only randomly generated parts of the schedule are simulated. We show that results collected from simulation can then be statistically analyzed for different scheduling models so that one can infer the overall fault resilience for the system., Facultad de Informática

Includes bibliographical references. Number of sources in the bibliography: 187 Thesis (Ph. D.) -- University of Cyprus, Faculty of Engineering, Department of Electrical and Computer Engineering, June 2014. The University of Cyprus Library holds the printed form of the thesis. Η ανίχνευση αντικειμένων είναι μια βασική και απαραίτητη λειτουργίας για ενσωματωμένα συστήματα όρασης, καθώς τους δίνει τη δυνατότητα να αλληλεπιδρούν με πιο έξυπνο τρόπο με το περιβάλλον τους και γίνεται όλο και πιο αναγκαία για ένα ευρύ φάσμα εφαρμογών που σχετίζονται με την επεξεργασία εικόνων, ρομποτική, συστήματα ασφαλείας και βίο-πληροφορική. Υφιστάμενα συστήματα που βασίζονται μόνο σε υλοποίηση σε λογισμικό παρέχουν την απαιτούμενη απόδοση μόνο για εικόνες μικρών διαστάσεων και κάτω από ιδανικές συνθήκες. Συνεπώς, υπάρχει ανάγκη για ανάπτυξη αρχιτεκτονικών σε υλικό που μπορούν να χρησιμοποιηθούν σε διάφορες εφαρμογές για εύρεση διαφορετικών αντικειμένων, σε εικόνες διαφόρων μεγεθών. Η διατριβή ασχολείται με μια βασική πρόκληση στις μέρες μας που σχετίζεται με το σχεδιασμό και την υλοποίηση αρχιτεκτονικών υλικού για την ανίχνευση αντικείμενων σε εικόνες, που να έχουν χαμηλή κατανάλωση ενέργειας και να λειτουργούν σε πραγματικό χρόνο, αξιοποιώντας τη χρήση αναδιατασσόμενου υλικού. Συγκεκριμένα, προτείνονται αρχιτεκτονικές για δύο αλγόριθμους, των αλγόριθμο Viola-Jones και τις διανυσματικές μηχανές υποστήριξης, με στόχο την ανίχνευση αντικειμένων σε πραγματικό χρόνο, διατηρώντας παράλληλα μια καλή ακρίβεια. Επιπλέον ένας ακόμη στόχος αυτής της διατριβής είναι η ανάπτυξη γενικών και επεκτάσιμων αρχιτεκτονικών υλικού, που να επιτρέπουν τη χρήση τους σε ένα ευρύ φάσμα εφαρμογών και διαφορετικές πλατφόρμες. Επιπλέον, ευφυείς μηχανισμοί ενσωματωθεί μαζί με τις προτεινόμενες αρχιτεκτονικές υλικού με σκοπό την περαιτέρω βελτίωση της απόδοσης. Επιπλέον, η διατριβή προτείνει μια μεθοδολογία για την περαιτέρω βελτίωση της απόδοσης των αλγορίθμων ανίχνευσης αντικειμένου με τη χρησιμοποίηση ακμών εικόνας, και τρισδιάστατων δεδομένων ώστε να επιτυχή την μείωση του αριθμού των παραθύρων που δημιουργούνται για μια εικόνα ώστε να αυξηθεί η συνολική απόδοση του συστήματος ανίχνευσης. Οι προτεινόμενες αρχιτεκτονικές αξιολογήθηκαν πειραματικά σε πλατφόρμες αναδιατασσόμενου υλικού και είναι ικανές να παρέχουν επεξεργαστικές επιδόσεις που ξεπερνούν τις 30 εικόνες ανά δευτερόλεπτο, επιτρέποντας να χρησιμοποιηθούν σε εφαρμογές ανίχνευσης αντικειμένων πραγματικού χρόνου. Object detection is a necessary task for embedded vision systems as it enables them to interact more intelligently with their host environment, and increases their responsiveness and awareness with regards to their surroundings. The typical object detection process involves extracting information of an image/video frame at various scales and classifying it using a machine learning pattern recognition algorithm to determine the presence of objects of interest. Object detection is a tedious process that needs to be performed within real-time constraints. Hence, this thesis addresses a key challenge nowadays related to the design and implementation of a hardware architecture for visual object detection in order to operate under low power requirements and facilitate real-time performance, both important constraints in embedded applications, while exploiting the use of reconfigurable hardware (FPGAs). In particular, two popular algorithms are implemented, the Viola-Jones and Support Vector Machines with the overall aim in increasing the performance of real-time object detection while maintaining the accuracy. Another goal of the thesis is to develop novel, generic and scalable architecture models in order to allow their usage in a wide range of applications and different hardware platforms. Furthermore, intelligent mechanisms are integrated along with the proposed hardware architecture in order to further improve performance or reduce computation overheads. In addition, and beyond the hardware implementation contributions, the thesis proposes a methodology to further improve the performance of object detection algorithms by utilizing edge image features, 3D depth data and classification in order to reduce the number of windows generated for an image and, hence, increase the overall performance of the detection problem. The proposed architectures are experimentally evaluated on Field Programmable Gate Arrays (FPGAs) computing platforms demonstrating real-time performance (over 30 frames-per second) that enables them to be used in real-time object detection applications, and maintain detection accuracy comparable to software implementations.

Conference of Symposium on Theory of Modeling and Simulation - DEVS Integrative M and S Symposium, DEVS 2013, Part of the 2013 Spring Simulation Multiconference, SpringSim 2013 ; Conference Date: 7 April 2013 Through 10 April 2013; Conference Code:96780; International audience; Model-based engineering is becoming a de facto paradigm for designing complex systems and software. By being executable, models are easier to understand, as well as systems they abstract. UML is the most natural choice for modeling. fUML is an executable subset of UML with precise operational semantics. From causal relations defined in a model, fUML semantics only constructs partial execution orders. When considering fUML in a simulation process, this limitation is possibly an issue for engineers to observe various execution schemes and to have a representative execution of a system model. Usually simulation frameworks control the execution of an application thanks to a dedicated entity. This latter is responsible for the construction of the execution order conforming to the semantics of a specific Model of Computation (MoC). Furthermore it can be used to reflect extra-functional aspects like time. In order to overcome these limitations, this paper proposes principles to use fUML as a simulation environment. We propose to extract the execution control policy from a fUML model and to delegate it to a specific simulation library defining MoCs as fUML models. This library is responsible for controlling the execution and simulating extra-functional aspects. This approach provides the required flexibility and openness needed to support various applications domains. The solution is evaluated on a simple, but representative example.

International audience; Energy harvesting is the capture of ambient energy, its conversion into a usable form, and its storage for immediate or future use. Interest in energy harvesting has increased over the last decade because of its environmental friendliness and its ability to power devices without electric wires. This term has been frequently applied in recent years in the context of small autonomous embedded devices such as wireless sensor nodes. In this paper, we address the scheduling problem for a single processor device that executes preemptable time critical tasks. Each one has a certain energy requirement and arrives at an unpredictable time. We ask the question whether the traditional task scheduling algorithm Earliest Deadline First (EDF) is convenient for energy harvesting environments. The paper shows that EDF has a zero competitive factor but nevertheless is optimal for online non-idling settings.

Model Driven Engineering (MDE) places models at the heart of the software engineering process. MDE helps managing the complexity of software systems and improving the quality of the development process. The Model Driven Architecture (MDA) initiative from the Object Management Group (OMG) defines a framework for building design flows in the context of MDE. MDA relies heavily on formalisms which are normalized by the OMG, such as UML for modeling, QVT for model transformations and so on. This work deals with the execution semantics of the UML language applied to embedded real-time applications. In this context, the OMG has a norm which defines an execution model for a subset of UML called fUML (foundational UML subset). This execution model gives a precise semantics to UML models, which can be used for analyzing models, generating code, or verifying transformations. The goal of this PhD thesis is to define and build an execution engine for UML models of embedded real-time systems, which takes into account the explicit hypothesis made by the designer about the execution semantics at a high level of abstraction, in order to be able to execute models as early as possible in the design flow of a system. To achieve this goal, we have extended the fUML execution model along three important axes with regard to embedded real-time systems: - Concurrency: fUML does not provide any mechanism for handling concurrent activities in its execution engine. We address this issue by introducing an explicit scheduler which allows us to control the execution of concurrent tasks. - Time: fUML does not provide any mean to handle time. By adding a clock to the model of execution, we can take into account the elapsed time as well as temporal constraints on the execution of activities. - Profiles: fUML does not take profiles into account, which makes it difficult to personalize the execution engine with new semantic variants. The execution engine we propose allows the use of UML models with profiles, and interprets these profiles as semantic extensions of the execution model. An implementation of these extensions has been realized as an Eclipse plug-in using the Papyrus UML modeling tool., L'Ingénierie Dirigée par les Modèles (IDM) place les modèles au cœur des processus de d'ingénierie logicielle et système. L'IDM permet de maitriser la complexité des logiciels et d'améliorer la rapidité et la qualité des processus de développement. Le Model Driven Architecture (MDA) est une initiative de l'Object Management Group (OMG) définissant un cadre conceptuel, méthodologique et technologique pour la mise-en-œuvre de flots de conception basés sur l'IDM. Le MDA s'appuie particulièrement sur une utilisation intensive des formalismes normalisés par l'OMG pour la mise-en-œuvre des flots IDM (UML pour la modélisation, QVT pour les transformations, etc.). Ce travail s'intéresse à la sémantique d'exécution du langage UML appliqué à l'exécution de modèles des applications temps réel embarquées. Dans ce contexte, l'OMG propose une norme qui définit un modèle d'exécution pour un sous-ensemble d'UML appelé fUML (foundational UML subset). Ce modèle d'exécution définit une sémantique précise non ambigüe facilitant la transformation de modèles, l'analyse, l'exécution de modèles et la génération de code. L'objectif de cette thèse est d'étudier et mettre-en-œuvre un moteur d'exécution de modèles UML pour les systèmes temps réel embarqués en explicitant les hypothèses portant sur la sémantique d'exécution des modèles à un niveau d'abstraction élevé afin de permettre l'exécution d'un modèle le plus tôt possible dans le flot de conception de l'application. Pour cela, nous avons étendu le modèle d'exécution défini dans fUML, en apportant une contribution sur trois aspects importants concernant les systèmes temps réel embarqués : * Gestion de la concurrence: fUML ne fournit aucun mécanisme pour gérer la concurrence dans son moteur d'exécution. Nous répondons à ce problème par l'introduction d'un ordonnanceur explicite permettant de contrôler les différentes exécutions parallèles, tout en fournissant la flexibilité nécessaire pour capturer et simuler différentes politiques d'ordonnancements. * Gestion du temps : fUML ne fixe aucune hypothèse sur la manière dont les informations sur le temps sont capturées ainsi que sur les mécanismes qui les traitent dans le moteur d'exécution. Pour cela, nous introduisons une horloge, en se basant sur le modèle de temps discret, afin de prendre en compte les contraintes temporelles dans les exécutions des modèles. * Gestion des profils : les profils ne sont pas pris en compte par ce standard, cela limite considérablement la personnalisation du moteur d'exécution pour prendre en charge de nouvelles variantes sémantiques. Pour répondre à ce problème, nous ajoutons les mécanismes nécessaires qui permettent l'application des profils et la capture des extensions sémantiques impliquées par l'utilisation d'un profil. Une implémentation de ces différentes extensions est réalisée sous forme d'un plugin Eclipse dans l'outil de modélisation Papyrus UML.

Ethernet Switches are widely used in real-time distributed systems as a solution to guarantee the real-time behavior in communication. In this solution there are still some limitations which are the important obstacles obtaining timeliness in the network. These limitations are the limited number of priority levels as well as the possibility of memory overruns with consequent messages. The mentioned limitations can be eliminated using a master/slave technique along with FTT paradigm. The FTT-SE protocol which is a technique based on the master/slave and FTT methods was proposed to overcome the mentioned limitations. However, the FTT-SE protocol has been investigated for a small network architecture with a single switch and master node. Extension of this solution to larger networks is still an open issue. Three different architectures were suggested to scale the FTT-SE to large scale network. In this thesis we propose a solution that extends the FTT-SEprotocol while keeping the real-time behavior of the network. In this solution, we divided the network into a set of sub-networks, each contains one switch, set of slave nodes and one master node that connected to the associated switch in the network. Moreover, the switches are connected together directly without gateways and form a tree topology network. The solution includes both synchronous and asynchronous traffic in the network. We also show that the timeliness of the traffic can still be enforced. Moreover, to validate the solution we have designed and implemented a simulator based on the Matlab/Simulink which is a tool to evaluate different network architecture using Simulink blocks. All transmission can be visualized by the ordinary Scope block in the Simulink. Moreover, the end-to-end delay for all messages is calculated after the simulation running to show the response time of the network. Furthermore, the response time analysis is done for both synchronous and asynchronous messages in this thesis according to the proposed solution. The results from simulation and the analysis are compared together to validate the investigations.

Le prime due tappe di 'Evaal', il concorso internazionale dedicato alle applicazioni più 'smart' per l'assistenza domestica automatizzata organizzato per il secondo anno consecutivo dal laboratorio 'Wireless network' (Wn Lab) dell'Istituto di scienze e tecnologie dell'informazione 'A. Faedo' (Isti) del Cnr di Pisa, si sono svolte a Madrid ('Localizzazione in ambiente domestico') e a Valencia ('Riconoscimento delle attività domestiche'). L'ultima fase, che ha visto la proclamazione e la premiazione dei vincitori, si è tenuta lo scorso settembre a Eindhoven.

Model Driven Engineering (MDE) places models at the heart of the software engineering process. MDE helps managing the complexity of software systems and improving the quality of the development process. The Model Driven Architecture (MDA) initiative from the Object Management Group (OMG) defines a framework for building design flows in the context of MDE. MDA relies heavily on formalisms which are normalized by the OMG, such as UML for modeling, QVT for model transformations and so on. This work deals with the execution semantics of the UML language applied to embedded real-time applications. In this context, the OMG has a norm which defines an execution model for a subset of UML called fUML (foundational UML subset). This execution model gives a precise semantics to UML models, which can be used for analyzing models, generating code, or verifying transformations. The goal of this PhD thesis is to define and build an execution engine for UML models of embedded real-time systems, which takes into account the explicit hypothesis made by the designer about the execution semantics at a high level of abstraction, in order to be able to execute models as early as possible in the design flow of a system. To achieve this goal, we have extended the fUML execution model along three important axes with regard to embedded real-time systems: - Concurrency: fUML does not provide any mechanism for handling concurrent activities in its execution engine. We address this issue by introducing an explicit scheduler which allows us to control the execution of concurrent tasks. - Time: fUML does not provide any mean to handle time. By adding a clock to the model of execution, we can take into account the elapsed time as well as temporal constraints on the execution of activities. - Profiles: fUML does not take profiles into account, which makes it difficult to personalize the execution engine with new semantic variants. The execution engine we propose allows the use of UML models with profiles, and interprets these profiles as semantic extensions of the execution model. An implementation of these extensions has been realized as an Eclipse plug-in using the Papyrus UML modeling tool., L'Ingénierie Dirigée par les Modèles (IDM) place les modèles au cœur des processus de d'ingénierie logicielle et système. L'IDM permet de maitriser la complexité des logiciels et d'améliorer la rapidité et la qualité des processus de développement. Le Model Driven Architecture (MDA) est une initiative de l'Object Management Group (OMG) définissant un cadre conceptuel, méthodologique et technologique pour la mise-en-œuvre de flots de conception basés sur l'IDM. Le MDA s'appuie particulièrement sur une utilisation intensive des formalismes normalisés par l'OMG pour la mise-en-œuvre des flots IDM (UML pour la modélisation, QVT pour les transformations, etc.). Ce travail s'intéresse à la sémantique d'exécution du langage UML appliqué à l'exécution de modèles des applications temps réel embarquées. Dans ce contexte, l'OMG propose une norme qui définit un modèle d'exécution pour un sous-ensemble d'UML appelé fUML (foundational UML subset). Ce modèle d'exécution définit une sémantique précise non ambigüe facilitant la transformation de modèles, l'analyse, l'exécution de modèles et la génération de code. L'objectif de cette thèse est d'étudier et mettre-en-œuvre un moteur d'exécution de modèles UML pour les systèmes temps réel embarqués en explicitant les hypothèses portant sur la sémantique d'exécution des modèles à un niveau d'abstraction élevé afin de permettre l'exécution d'un modèle le plus tôt possible dans le flot de conception de l'application. Pour cela, nous avons étendu le modèle d'exécution défini dans fUML, en apportant une contribution sur trois aspects importants concernant les systèmes temps réel embarqués : * Gestion de la concurrence: fUML ne fournit aucun mécanisme pour gérer la concurrence dans son moteur d'exécution. Nous répondons à ce problème par l'introduction d'un ordonnanceur explicite permettant de contrôler les différentes exécutions parallèles, tout en fournissant la flexibilité nécessaire pour capturer et simuler différentes politiques d'ordonnancements. * Gestion du temps : fUML ne fixe aucune hypothèse sur la manière dont les informations sur le temps sont capturées ainsi que sur les mécanismes qui les traitent dans le moteur d'exécution. Pour cela, nous introduisons une horloge, en se basant sur le modèle de temps discret, afin de prendre en compte les contraintes temporelles dans les exécutions des modèles. * Gestion des profils : les profils ne sont pas pris en compte par ce standard, cela limite considérablement la personnalisation du moteur d'exécution pour prendre en charge de nouvelles variantes sémantiques. Pour répondre à ce problème, nous ajoutons les mécanismes nécessaires qui permettent l'application des profils et la capture des extensions sémantiques impliquées par l'utilisation d'un profil. Une implémentation de ces différentes extensions est réalisée sous forme d'un plugin Eclipse dans l'outil de modélisation Papyrus UML.

Rapid evolution of real-time and embedded systems (RTES) is continuing at an increasing rate, and new method-ologies and design tools are needed to reduce design complexity while decreasing development costs and integrating aspects such as verification and validation. Model-Driven Engineering offers an interesting solution to the above mentioned challenges and is being widely used in various industrial and academic research projects. This paper presents the EU funded MADES project which aims to develop novel model-driven techniques to improve existing practices in development of RTES for avionics and surveillance embedded systems industries. MADES proposes a subset of existing UML profiles for embedded systems modeling: namely MARTE and SysML, and is developing new tools and technologies that support design, validation, simulation and eventual automatic code generation, while integrating aspects such as component re-use. In this paper, we first introduce the MADES language, which enables rapid system design and specification that can be then taken by underlying MADES tools for goals such as simulation or code generation. Finally, we illustrate the various concepts present in the MADES language by means of a car collision avoidance system case study.

La maggior parte dei dispositivi embedded dev'essere oggi in grado di offrire funzioni quali, ad esempio, configurazione, diagnosi ed aggiornamento remoto dei programmi applicativi mediante una rete di comunicazione. L'avere a disposizione software open source per le pile protocollari TCP/IP e UDP/IP ha reso questo compito relativamente agevole, anche per applicazioni a basso costo. Le caratteristiche di queste pile protocollari per quanto concerne l'esecuzione in tempo reale sono invece ancora poco note, anche perché le applicazioni già citate non necessitano di queste informazioni per funzionare. Questo contributo analizza le prestazioni in tempo reale di una pila protocollare open source e mostra che esse sono accettabili per molte applicazioni industriali, a patto di realizzare un corretto adattamento verso il sistema operativo e l'interfaccia di rete.

The adoption of open-source operating systems for the execution of real-time applications is gaining popularity, even in the networked control systems domain, due to cost and flexibility reasons. However, as opposed to their commercial counterparts, the actual performance level to be expected from them is still little known and may often depend on the kind of real-time extension being used, its configuration, and the overall software load of the system, including best-effort components. In this paper, an open-source EtherCAT master supported by a popular real-time extension for Linux, the RT Patch, is thoroughly evaluated with long-term measurements, which build confidence on the suitability of the proposed approach for real-world applications. Special attention is devoted to the unexpected, adverse effect that some best-effort components, for instance, graphics applications, may have on the overall real-time characteristics of the system. For reference, the proposed approach is also compared with RTAI, a more traditional and well-known real-time extension for Linux already in use for demanding applications.

System-on-Chip (SoC) can be considered as a particular case of embedded systems and has rapidly became a de-facto solution for implement- ing these complex systems. However, due to the continuous exponential rise in SoC's design complexity, there is a critical need to find new seamless method- ologies and tools to handle the SoC co-design aspects. This paper addresses this issue and proposes a novel SoC co-design methodology based on Model Driven Engineering (MDE) and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by OMG (Object Management Group), in order to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs; and allow to implement the notion of Partial Dy- namic Reconfiguration supported by current FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in UML (Unified Modeling Language); and afterwards, transform these high level mod- els into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis.

Contenido: Arquitecturas de computadoras Sistemas embebidos Arquitecturas orientadas a servicios (SOA) Redes de comunicaciones Redes heterogéneas Redes de Avanzada Redes inalámbricas Redes móviles Redes activas Administración y monitoreo de redes y servicios Calidad de Servicio (QoS, SLAs) Seguridad informática y autenticación, privacidad Infraestructura para firma digital y certificados digitales Análisis y detección de vulnerabilidades Sistemas operativos Sistemas P2P Middleware Infraestructura para grid Servicios de integración (Web Services o .Net), Red de Universidades con Carreras en Informática (RedUNCI)