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The aggressive scaling of MOS devices is quickly reaching the fundamental limits of SiO/sub 2/ as the gate dielectric. Replacement of SiO/sub 2/ with a high dielectric constant material allows an increase in the physical oxide thickness, while maintaining a low equivalent oxide thickness (EOT) and low direct tunnelling current. The high-k gate dielectric of choice will most likely be a deposited film, which makes the replacement of SiO/sub 2/, a thermally grown layer, even more challenging. Atomic layer CVD (ALCVD/sup TM/) is a well-controlled surface saturating process using gas-solid interactions to deposit thin films. The technique results in covalent bonding between the gaseous precursors and the surface bonding sites. ALCVD/sup TM/ provides highly uniform layers and the possibility to deposit many materials, including mixed oxide layers and nano-laminates. Some of the challenges facing high-k materials include achieving a high quality Si/high-k interface, film stability and solving reliability and integration issues. In this paper, we use MOS capacitors to investigate these challenges for Al/sub 2/O/sub 3/-TiN and Al/sub 2/O/sub 3/-ZrO/sub 2/-TiN gate stacks.

Low-frequency noise has been used to study the impact of an Al2O3 work-function-engineering cap layer on the gate oxide quality of SiO2/HfO2 DRAM peripheral n- and pMOSFETs. It is shown that from the 1/f-like spectra a border trap density profile can be extracted, which depends on whether the cap is deposited below or above the HfO2 layer. In general, the presence of Al in the high-κ material leads to a higher trap density, with a maximum concentration close to or at the SiO2/HfO2 interface, where a dipole layer is expected to form. When removing the cap layer from the SiO2 interfacial layer, excess generation-recombination-like noise is introduced for the n-channel devices, indicating the presence of dry-etching damage at the SiO2/HfO2 interface.

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In this work, we employ the substrate hot electron injection technique as a characterization tool to examine the defect creation mechanisms in high-k HfSiON gate stacks, taking advantage of the independent control over oxide field, electron fluence, and injected electron energy which the technique allows. We show that defect creation and oxide breakdown are dependent on the energy of the injected electrons and not on the oxide field. Furthermore, we show that the energy of the injected electrons governs whether the majority of the defects are created at the Si∕SiO2 interface or in the bulk of the material. Results show that at operating conditions, the primary threat to device reliability from hot carrier damage is the introduction of a permanent 3D positive bias temperature instability component introduced by increased interface trap generation, even for carriers with energy slightly above that of field accelerated electrons. We also discuss the feasibility of using substrate hot electron injection as a ...