249 results on '"Tsui, Bing-Yue"'
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102. High-Performance Poly-Si Nanowire Thin-Film Transistors Using the $\hbox{HfO}_{2}$ Gate Dielectric
103. Extreme ultra-violate exposure induced damages on non-volatile memories
104. A process for high yield and high performance carbon nanotube field effect transistors
105. Multi-gate non-volatile memories with nanowires as charge storage material
106. Thermal Stability of Nickel Silicide and Shallow Junction Electrical Characteristics with Carbon Ion Implantation
107. A 30 nm gate-all-around poly-Si nano wire thin-film transistor
108. Improvement of the Thermal Stability of NiSi by Germanium Ion Implantation
109. Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate
110. Ta–Pt Alloys as Gate Materials for Metal–Oxide–Semiconductor Field Effect Transistor Application
111. Trigate TiN Nanocrystal Memory with High-k Blocking Dielectric and High Work Function Gate Electrode
112. Thermal Stability Improvement of NiSi on Gate by High Dosage Germanium Implantation
113. Method for Extracting Gate-Voltage-Dependent Source Injection Resistance of Modified Schottky Barrier (MSB) MOSFETs
114. Two-Dimensional Carrier Profiling by Kelvin-Probe Force Microscopy
115. Thermal Stability and Electrical Characteristics of Tungsten Nitride Gates in Metal–Oxide–Semiconductor Devices
116. Low Threshold Voltage CMOSFETs with NiSi Fully Silicided Gate and Modified Schottky Barrier Source/Drain Junction
117. The Impact of High-voltage Drift N-well and Shallow Trench Isolation Layouts on Electrical Characteristics of LDMOSFETs
118. Impact of \Vpass Interference on Charge-Trapping NAND Flash Memory Devices.
119. Process and Characteristics of Fully Silicided Source/Drain (FSD) Thin-Film Transistors
120. Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-k gate stack by low-frequency capacitance-voltage measurement
121. Investigation of NiSi Fully-Silicided Gate on SiO2 and HfO2 for Applications in Metal–Oxide–Semiconductor Field-Effect Transistors
122. Study on the interface thermal stability of metal-oxide-semiconductor structures by inelastic electron tunneling spectroscopy
123. Effect of Oxygen Absorption on Contact Resistance between Metal and Carbon Nano Tubes (CNTs)
124. Impact of Back Gate Bias on Hot-Carrier Effects of n-channel Tri-Gate FETs (TGFETs)
125. Schottky Barrier TFTs with Source/Drain Sub-Gates
126. An Excellent Cu Diffusion Barrier for Next Generation Multi-level Cu-interconnect
127. Investigation of Molybdenum Nitride Gate on SiO[sub 2] and HfO[sub 2] for MOSFET Application
128. Effects of Base Oxide Thickness and Silicon Composition on Charge Trapping in HfSiO/SiO2 High-k Gate Stacks
129. Electrical Characteristics of Thin HfO2 Gate Dielectrics Prepared Using Different Pre-Deposition Surface Treatments
130. Optimization of Back Side Cleaning Process to Eliminate Copper Contamination
131. Electrical Stability and Reliability of Ultralow Dielectric Constant Porous Carbon-Doped Oxide film for Copper Interconnect
132. A New Method to Correct Capacitance of High-leakage Ultra-thin Gate Dielectric
133. Threshold Voltage Instability in nMOSFETs with HfSiO/SiO2 High-k Gate Stacks
134. Analysis of NiSi Fully-silicided Gate on SiO2 and HfO2 for CMOS Application
135. High-Performance Modified-Schottky-Barrier S/D p-Channel FinFETs
136. 24.4: Planar Triode Structure Carbon Nanotubes Field Emission Display
137. Investigation of Cu/TaN Metal Gate for Metal-Oxide-Silicon Devices [Journal of The Electrochemical Society, 150, G22 (2003)]
138. Stability Investigation of Single-Wafer Process by Using a Spin Etcher
139. Via-Filling Capability of Copper Film by CVD
140. Novel Binary Alloy Gate Electrodes for Metal Gate MOS Devices
141. Dielectric and Barrier Properties of Spin-On Organic Aromatic Low Dielectric Constant Polymers FLARE and SiLK
142. Surface-Processing-Enhanced Copper Diffusion into Fluorosilicate Glass
143. Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D <sc>NAND</sc> Flash Memory Devices.
144. Six\rm Ge1\-{\rm x} Epitaxial Tunnel Layer Structure for P-Channel Tunnel FET Improvement.
145. Tilt angle effect on DC and AC performance of Halo PMOS
146. Dielectric degradation of Pt/SiO2/Si structures during thermal annealing
147. Contact resistivity of shallow junctions formed by implantation through Pt or PtSi
148. Integral contact process in submicron technology.
149. Formation of PtSi‐contactedp+nshallow junctions by BF+2implantation and low‐temperature furnace annealing
150. Formation and characterization of a PtSi contactedn+pshallow junction
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