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Mass via arrays (MVAs) are intersubstrate thermal management structures that utilize thermal meta-material design principles to target localized hot spots and extreme variation in the temperature profile of electronic systems. MVAs have shown promise for integration into electronic systems as passive thermal management techniques. Theoretical analysis has shown that, when properly designed, MVAs and MVA-like structures provide control over how the heat is transferred in an electronic substrate. While the theoretical confirmation of this behavior is promising, experimental results are important to prove and strengthen MVA design principles. In this work, MVAs are implemented using an industry-standard printed circuit board (PCB) fabrication technique with Rogers 4350B (RO4350) material. The design structures are first theoretically modeled using a multilayer RO4350 stack-up in which equivalent thermal properties are studied for a variety of MVA designs. Uncertainty metrics are integrated into this model, and an iterative, Monte Carlo process is used to simulate variability in MVA performance. Next, these theoretical structures are implemented in conventional PCBs. Sample devices are chosen at random, and the heat spreading characteristics of the devices are measured using a thermal imaging camera. The results of these measurements confirm the theoretical baseline that an MVA structure provides improved thermal management characteristics relative to conventional thermal via array (TVA) structures. [ABSTRACT FROM AUTHOR]

Erratum: Zhang, C. et al., The Effect of Substrate Biasing during DC Magnetron Sputtering on the Quality of VO 2 Thin Films and Their Insulator-Metal Transition Behavior. The authors would like to correct a typographical error in their paper [[1]]. Reference 1 Zhang C., Gunes O., Li Y., Cui X., Mohammadtaheri M., Wen S.-J., Wong R., Yang Q., Kasap S. The Effect of Substrate Biasing during DC Magnetron Sputtering on the Quality of VO2 Thin Films and Their Insulator-Metal Transition Behavior. [Extracted from the article]

The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method. [ABSTRACT FROM AUTHOR]

In this work, VO 2 thin films were deposited on Si wafers (onto (100) surface) by DC magnetron sputtering under different cathode bias voltages. The effects of substrate biasing on the structural and optical properties were investigated. The results show that the metal-insulator transition (MIT) temperature of VO 2 thin films can be increased up to 14 K by applying a cathode bias voltage, compared to deposition conditions without any bias. The decrease in the transition efficiency and increase in the transition temperature are attributed to the enlarged grain size, increased defects, and the residual stress in the VO 2 thin films induced by biasing. The optical transmittance measurements for different thickness films indicate an attenuation coefficient of 3.1 × 10 7 m -1 at 2000 nm or an extinction coefficient of 4.9 in the metal phase. The optical transmittance vs wavelength characteristics point to an indirect bandgap of 0.6 ± 0.5 eV and significant scattering in the bulk and/or at the interface.