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To prevent charge pump from degradation in its applications to power management IC (integrate circuit) like hot swap controller, the influence of the clock frequency and duty cycle on charge pump was analyzed. And a new oscillator structure featuring the immunity from changes of frequency and duty cycle, which is originated from the supply voltage fluctuation, was proposed. The new charge pump was applied to a hot swap controller IC to lift up the gate drive voltage of the external FET. Simulation results showed that by using it, the hot swap controller worked well while supply voltage swung from 3V to 10V. And all circuits were designed and realized in 1.5μm BCD (Bipolar-CMOS-DMOS) process.

To solve uneven distribution of currents and thermal stresses among the power modules in paralleled power systems such as parallel multiple independent power supplies or dc-to-dc modules, a load share controller IC (integrated circuit) was proposed. By using the automatic MSC (master-slave control) technique, the functions necessary to these systems such as even current and thermal stress distribution controlling were achieved. Some new functions including bus short fault protection and Enable function were added to the chip. Simulation results showed that the main expectation for the controller was realized and the current share error at full load was controlled within 1%. In addition, by introducing special start-up control logic, start-up timing of parallel system was obviously improved. The chip was designed in 1.5μm BCD (Bipolar-CMOS-DMOS) technology with an area of 3.6 mm2.

A hot swap controller was developed to ensure the safe insertion and removal of a circuit board from a live backplane. Multi protections of both board and backplane were proposed and realized in this design, which includes automatically starting current limiting or circuit breaking in the event of over current faults and driving an SCR crowbar to protect the loads in the event of over input voltage faults. In addition, the under-voltage detecting and output voltage monitoring is also available for its use. A lot of efforts were put into the design and optimization of its control strategy since the performance of the circuit depends it strongly. The simulation results are well consistent with the expectations. This IC could be realized in BCD technology (Bipolar-CMOS-DMOS technology).

An analog implementation of a novel fixed-frequency quasi-sliding-mode controller for single-inductor dual-output (SIDO) buck converter in pseudo-continuous conduction mode (PCCM) with a self-adaptive free- wheeling current level (SFCL) is presented. Both small and large signal variations around the operation point are considered to achieve better transient response so as to reduce the cross-regulation of this SIDO buck converter. Moreover, an internal integral loop is added to suppress the steady-state regulation error introduced by conventional PWM-based sliding mode controllers. Instead of keeping it as a constant value, the free-wheeling current level varies according to the load condition to maintain high power efficiency and less cross-regulation at the same time. To verify the feasibility of the proposed controller, an SIDO buck converter with two regulated output voltages, 1.8 V and 3.3 V, is designed and fabricated in HEJIAN 0.35 m CMOS process. Simulation and experiment results show that the transient time of this SIDO buck converter drops to 10 s while the cross-regulation is reduced to 0.057 mV/mA, when its first load changes from 50 to 100 mA.

This paper presents a high dimming ratio light emitting diode (LED) drive controller chip with digital mode dimming (DMD). The chip is composed of a boost power converter and a dimming control block. A novel constant on time (COT) control strategy is proposed for boost converter to achieve high dimming ratio. In addition, a fast enough load transient response of the converter power stage ensures its high dimming ratio. The COT control circuit operates mainly based on two current-capacitor timers and a finite state machine (FSM). The LED drive controller chip is designed and fabricated in 1.5 μm bipolar CMOS-DMOS (BCD) process with a die area of 1.31 × 1.43 mm2. Experimental results show that the proposed LED drive system works well. And, as expected, the minimum LED dimming on time of 1.0 μs and the corresponding dimming ratio of 1000:1 at 1 kHz dimming frequency are successfully achieved.