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Static random access memory (SRAM) is a sort of RAM where information is not permanently stored and does not require routine updating. To reduce leakage power without sacrificing performance, a variety of approaches have been applied to SRAM cells. In this study, we suggest a new 16T SRAM design that can function in active, park, standby, or hold modes. A fully static mode of operation for SRAM is made possible by the 16T SRAM structure, which also enhances write margin (WM) and removes charging conflict between devices during read and write operations. The key objectives of the suggested architecture are to retain logic state in park mode while maintaining stability and reducing standby time in active mode, as well as to reduce leakage current in standby mode. This is done by removing feedback from the back-to-back inverters during write operations via the data-dependent supply block. This makes it possible for the suggested bitcell to considerably increase the WM. A novel SRAM cell with 16 transistors is created with subthreshold operation and enhanced data stability. By using an equalized bit line technique to avoid leakage due to enhanced data pattern and RBL detection, the suggested single-ended SRAM cell with dynamic feedback control lowers the static noise margin for ultra-low power transfer. A sleep transistor is incorporated into the architecture to save power consumption when the system is in standby mode due to inefficient voltage transmission. Tanner EDA tool V.14.1 on 45-nm CMOS was used for design and simulation. The outcomes demonstrate a considerable decrease in no-load current and power loss. [ABSTRACT FROM AUTHOR]

This paper presents a novel reconfigurable SRAM CRP PUF that can achieve high reliability and randomness. In conventional reconfigurable SRAM CRP PUFs, imprecise timing control can produce a biased response output, which is typically attributed to mismatches in the connection of input control signals to the two inverter arrays in the layout floorplan. We propose a timing control scheme along with the addition of an adjunct NMOS transistor to address this issue. This eliminates the connection mismatches for the challenge and word-line inputs to the two inverter arrays. Furthermore, we employ symmetric layout techniques to achieve the randomness of response output. The symmetric arrangement of the two inverter arrays maximizes the inherent random output characteristics derived from process variation. The pre-charge input signal is symmetrically connected to each array to prevent delay mismatches. A 16 × 9-bit reconfigurable PUF array is fabricated by using a 180 nm CMOS process, with a PUF cell area of 1.2 × 10 4 F 2 /bit. The experimental results demonstrate an inter Hamming distance of 0.4949 across 40 chips and an intra Hamming distance of 0.0167 for a single chip in 5000 trials. The measured worst bit error rate (BER) is 4.86% at the nominal point (1.8 V, 25 °C). The proposed prototype exhibits good reliability and randomness, as well as a small silicon area when compared to the conventional SRAM CRP PUFs. [ABSTRACT FROM AUTHOR]

Electronic devices are persisting as the integral part in various medical devices. These devices require SRAMs (Static Random Access Memory) with power efficient capability to handle the data, as they occupy most of the die area. Especially, wearable devices are bringing new challenges in the design of an IC, where high stability and low static power dissipation are very much required. In this paper, two new Carbon Nanotube Field Effect Transistor (CNTFET) based 9T SRAM cell topologies are presented to improve the leakage power dissipation at standby mode while maintaining the stability of the cell. Differential bitlines with decoupled read port are used to assist the read disturbance and the subthreshold lowering as well as stack of transistors are employed to curtail the leakage power. The circuits are implemented at 900 mv in Cadence using CNTFET technology. The Architecture with a 4 × 4 array matrix of the proposed 9T cells is designed. These are found to be the better ones yielding good results compared to the existing designs. [ABSTRACT FROM AUTHOR]

In this study, a trajectory simulation is developed in order to estimate pre-apogee flight parameters of low altitude rockets. It is intended to evolve a mathematical model of trajectory of rocket and provide a perspective for design and performance analysis. The rocket's equations of motion of are integrated using the fourth-order Runge-Kutta method. First, the variation of altitude, velocity, acceleration, and pitch angle values of the rocket with time during flight are investigated. Secondly, the center of pressure and center of gravity are dynamically calculated to determine changes in the rocket's static margin during flight. This approach allows the simulation to provide information regarding the stability of the rocket. The accuracy of the numerical results is verified by comparing them to real flight data and an open source software. For this purpose, two rockets with design parameters and real flight data, previously launched to different altitudes, are used in the study. This research specifically focuses on orbital simulation and stability of unguided, low-altitude, subsonic sounding rockets and highlights the importance of modeling and simulation in the design and optimization of rockets. [ABSTRACT FROM AUTHOR]

This article presents a reconfigurable in-/near-memory advanced computing (InMAC) architecture based on 6T SRAM, with a storage capacity of 1 KB (128 × 64). The proposed architecture utilizes standard 65 nm CMOS technology and operates with a power supply of 1 V. Along with standard storage operations, the design performs various complex Boolean computing operations, such as binary to gray, gray to binary, 2's complement, and binary addition, with 8-bit precision. The architecture also implements other essential logic operations, such as NAND, NOR, XOR, and XNOR, in an area-efficient manner, without requiring complex circuitry. The design offers flexibility in the reconfiguration to meet specific bit precision and operation requirements. In-memory computing approaches improve the latency by 7 × and 4 × for logic implementation and Boolean computation, respectively, compared to conversions performed outside the macro. Additionally, the optimized full adder design outperforms the state-of-the-art design in terms of all parameters analyzed, with reductions of 40% in the number of transistors, 25.4% in latency, 55.2% in dynamic power, and 28.1% in static power. The proposed InMAC architecture can potentially use in-memory computing in various applications that require advanced computing with low latency. [ABSTRACT FROM AUTHOR]

In this paper, a schmitt trigger-based single-sided 7T stable SRAM is proposed for ultra-low energy and near-threshold operation, which supports a bit interleaving scheme. The proposed ST-7T SRAM design improves the WSNM (Write Static Noise Margin) and RSNM (Read Static Noise Margin) and consumes less energy. Moreover, obtain high read strength by utilizing a single-sided ST (schmitt trigger) inverter. Furthermore, write ability is also enhanced by applying an ST inverter write assist scheme (Negative VWWL technique), which can limit the tripping voltage of the ST inverter circuit. The PST-7T (Proposed ST-7T) circuit minimizes the read power by 49.96%, write power by 39.27%, and leakage power by 39.17% compared to conventional-6T SRAM. The RSNM and WSNM of the proposed SRAM circuit are enhanced by 66.28% and 18.97% compared to conventional-6T SRAM. The write energy and read energy utilization are also lowered by 14.87% and 14.19% compared to the SE7T SRAM cell. [ABSTRACT FROM AUTHOR]

Static random-access memory (SRAM), a pivotal component in integrated circuits, finds extensive applications and remains a focal point in the global research on single-event effects (SEEs). Prolonged exposure to irradiation, particularly the displacement damage effect (DD) induced by high-energy protons, poses a substantial threat to the performance of electronic devices. Additionally, the impact of proton displacement damage effects on the performance of a six-transistor SRAM with an asymmetric structure is not well understood. In this paper, we conducted an analysis of the impact and regularities of DD on the upset cross-sections of SRAM and simulated the single-event upset (SEU) characteristics of SRAM using the Monte Carlo method. The research findings reveal an overall increasing trend in upset cross-sections with the augmentation of proton energy. Notably, the effect of proton irradiation on the SEU cross-section is related to the storage state of SRAM. Due to the asymmetry in the distribution of sensitive regions during the storage of "0" and "1", the impact of DD in the two initial states is not uniform. These findings can be used to identify the causes of SEU in memory devices. [ABSTRACT FROM AUTHOR]

This paper presents an error resilience evaluation of the intra prediction step in Versatile Video Coding decoders when approximate storage is employed in the Reference Line Buffer (RLB). We present an error injection framework to simulate the use of approximate storage in the RLB buffer with commonly used bit error rate (BER) values from literature for static random-access memory and dynamic random-access memory technologies. We perform an error resilience evaluation based on peak signal-to-noise ratio and structural similarity for twelve video sequences, considering different decoding settings, with four quantization parameters, two encoding configurations, and seven BERs. We also present a few examples, showing how approximately decoded sequences can look and performing a subjective visual quality analysis. Our analysis characterizes how the impacts of approximation are dependent on video content and configurations. The results show that approximate storage can be used in some of the evaluated scenarios with very low degradation on the final visual quality of the decoded video sequences. [ABSTRACT FROM AUTHOR]

Due to the dramatic increase of resource-constrained Internet of Things devices, robust and lightweight security primitives are emerging to protect such devices from malicious attacks. Static Random Access Memory (SRAM) Physical Unclonable Function (PUF) is a promising candidate, typically used for secure key generation. An SRAM PUF exploits manufacturing process variations to generate device-specific responses based on the random start-up values (SUVs), after the device is powered up. However, a Complementary Metal-Oxide-Semiconductor aging mechanism, Bias Temperature Instability (BTI), might be exploited to change the original SUVs of an SRAM PUF. Based on this fact, we propose a physical cloning process using BTI to modify SRAM SUVs and create physical counterfeits. The produced counterfeit is reliable and can act as the target PUF to generate error-free keys, so it is potentially able to be implemented in malicious attacks. To prevent this physical cloning attack, we propose a scheme without any modifications on the present SRAM PUF circuit, which is to pre-charge a PUF before it is powered up, so that its response can be affected by those transistors that cannot be precisely aged in the cloning process. Our simulation results indicate the presented cloning process can produce a counterfeit with 98.64% similarity to a conventional SRAM PUF in reasonable time, but the similarity is largely reduced to 51% by introducing the pre-charge scheme as prevention. Finally, we show security and reliability metrics of SRAM PUFs are not affected by the extra pre-charge phase. [ABSTRACT FROM AUTHOR]

Non-linear distortion of signals is a serious problem in computing-in-memory SRAM (CIM-SRAM) circuits in current mode. This problem greatly limits the performance of calculations and directly affects the computing power of the CIM-SRAM. In this study, the causes of non-linearity and inconsistency were investigated. Based on detailed analyses, we proposed a high-precision, fully dynamic range IV (HFIV) conversion circuit. The HFIV circuit was added to each bit line (BL) for voltage clamping and proportionally mirroring the read current. We applied the structure to numerous prior studies and evaluated them using the 55 nm complementary metal-oxide semiconductor process. The results showed the proposed HFIV circuit could increase the CIM-SRAM's calculation linearity to 99.92% (8~32 SRAM bit-cells) and 99.8% (32~64 SRAM bit-cells) with a 1.2 V supply. [ABSTRACT FROM AUTHOR]

This paper proposes a method of definition of transistor dimensions for an 8-transistor (8T) cell of a resister file static memory RFSRAM (register file static random access memory) for development of low-power dual-port register files and dual-port SRAM (static random access memory) for power consumption decrease. This method can also be used for 6-transistor (6T) cells of single-port static RAM. The method is based on the analysis of so-called butterfly curves (BC) and the search for such values of transistor dimensions and their threshold voltage dispersion, providing for a given critical minimum supply voltage and the existence of one intersection and one contact of the BC. We compare the obtained characteristics of silicon memory samples and their critical voltage with the simulation results in the reading and writing modes dependent on the supply voltage. Experimental samples of memory cells manufactured at the TSMC factory using 180 nm have technology passed testing at 0.75–1.8 V. [ABSTRACT FROM AUTHOR]

The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly eliminate data remanence and maximise physical mismatch. Moreover, a two-phase power gating module is devised to provide controllable power on/off cycles for the chosen PUF clusters in order to facilitate fast statistical measurements and curb the in-rush current. The architecture and hardware implementation of the power-gated PUF are developed to accommodate fast multiple evaluations of PUF Responses. The fast speed enables a new data processing method, which coordinates Dark-bit masking and Multiple Temporal Majority Voting (TMV) in different Process, Voltage and Temperature (PVT) corners or during field usage, hence greatly reducing the Bit Error Rate (BER) and the hardware penalty for error correction. The designs are based on the UMC 65 nm technology and aim to tape out an Application-Specific Integrated Circuit (ASIC) chip. Post-layout Monte Carlo (MC) simulations are performed with Cadence, and the extracted PUF Responses are processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion in PUF Responses, which comprise the novelty of this approach. [ABSTRACT FROM AUTHOR]

Memristive devices, which are materials systems with two or three electrodes separated by an insulating or semiconducting material, are becoming increasingly important in various applications. They are already being used as non-volatile electronic memory and are expected to have a market size of up to 5.6 billion USD by 2026. Recent research has shown that memristors have potential for applications in brain-inspired neuromorphic engineering, cryptography, and 5G/6G telecommunications. The versatility of memristors lies in the materials used, as different materials have different electrical characteristics and figures-of-merit. Intense research is necessary to optimize the properties of memristors and discover new functionalities, such as mechanical, optical, and thermal properties. This special issue of Advanced Functional Materials contains 20 articles written by leading scientists in the field, covering various aspects of materials for memristors and proposing innovative applications. The articles discuss the use of different materials, including 2D materials like MoS2, hexagonal boron nitride (hBN), and graphene oxide, as well as materials with dipoles like ferroelectric and piezoelectric materials, nanowire electronics, and phase change memory and organic memory. [Extracted from the article]

Many researchers are actively working on developing a fast-performing static random-access memory (SRAM) cell with low-power consumption and high stability. This study also introduces one such new and all-round excellent SRAM cell. In this paper, an SRAM cell with eleven transistors (11T) developed using carbon nanotube field effect transistor (CNTFET) is introduced. This new 11T CNTFET SRAM cell is another variant of the Schmitt-trigger (ST)-based SRAM cell. This new SRAM cell structure is achieved by incorporating a single-ended write mode, a feed-back cutting technique and a single-ended read approach into a Schmitt-trigger (ST)-based SRAM cell. The WSNM of the proposed 11T CNTFET SRAM cell is increased by using single-ended writing scheme and feed-back cutting method in the cell. The single ended read approach of 11T CNTFET SRAM cell increases the RSNM as the storage nodes are not disturbed. The write power, hold power, read power, WSNM, HSNM, RSNM, write delay and read delay of this 11T CNTFET SRAM cell are 2.1538e-10 W, 1.7077e-09 W, 1.4524e-08 W, 423.61 mV, 402.20 mV, 425.56 mV, 1.2932e-10s and 5.5225e-12s, respectively. The parameters of the proposed cell are compared with 6T SRAM [M. Elangovan and K. Gunavathi, Stability analysis of 6T CNTFET SRAM cell for single and multiple CNTs, 2018 4th Int. Conf. Devices, Circuits Syst., Coimbatore, India, 16–17 March 2018, vol. 2, pp. 63–67], 8T SRAM [M. Elangovan, A novel Darlington based 8T CNTFET SRAM cell for low, J. Circuits Syst. Comput.30 (2021) 2150213], 12T SRAM [S. Pal, S. Bose, W. H. Ki and A. Islam, Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications, IEEE Trans. Electron Dev. 67 (2020) 80–89, doi:10.1109/TED.2019.2952397], 12T SRAM [N. Yadav, A. P. Shah and S. K. Vishvakarma, Stable, reliable, and bit-interleaving 12T SRAM for space applications: A device circuit co-design, IEEE Trans. Semicond. Manuf. 30 (2017) 276–284, doi:10.1109/TSM.2017.2718029], 12T SRA-M [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger-based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] and 12T SRAM [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] cells to understand the performance of the proposed SRAM cell. From the comparative study, it is observed that the proposed cell is more stable than the other cells considered for the comparison and consumes less power in all write, read and hold modes. Also, the read time of the introduced cell is much less than the others. This study also recorded the information on how the performance of an SRAM cell varies as the CNTFET parameters change. The simulation is done with the HSPICE simulation tool using the Stanford University 32 nm CNTFET model. [ABSTRACT FROM AUTHOR]

With the percentage of embedded SRAM increasing in SoC chips, low-power design such as the near-threshold SRAM technique are getting increasing attention to reduce the entire chip energy consumption. However, the descending operating voltage will lead to longer write latency and a higher failure rate. In this paper, we present a novel low Vth ultradynamic voltage scaling (UDVS) 9T subthreshold SRAM cell to improve the write ability of SRAM cells. The proposed Low Vth UDVS SRAM cell is demonstrated with a low threshold voltage speed-up transistor and an ultradynamic voltage scaling circuit implemented in 16 nm low-leakage CMOS technology. This wide supply range was made possible by a combination of circuits optimized for both subthreshold and abovethreshold regimes. This write assist technique can be operated selectively to provide write capability at very low voltage levels while avoiding excessive power overhead. The simulation findings reveal that with 16 nm technology, the write ability is improved by 33% over the normal case at 0.9 V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at VDD = 0.3 V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST2/PPN10T due to the read-decoupling technique. Furthermore, it improves writability by 1.42X/2.85X/1.35X/1.28X compared to 6T/DIRP10T/ST2/PPN10T owing to feedback-cutting scheme. The use of write bitline free structure make the proposed SRAM consumes at least 2.79X lower dynamic power. The static power is reduced in the proposed SRAM by at least 1.09X. The reduction is because of the stacking of the transistors, the long path from power VDD to ground, and eliminated leakage in read path. The proposed SRAM works reliably even when exposed to extreme process variations. The proposed bitcell occupies a 1.46X/1.19X higher area than that of 6T/8T. The proposed design improves most of the design metrics and can be an efficient candidate for portable applications with budgeted power. [ABSTRACT FROM AUTHOR]

The impact of 0.1–10 MeV neutron-induced single-event upsets (NSEUs) on terrestrial SER (soft error rate) prediction is analyzed for several broad spectrum neutron sources based on 0.1–200 MeV NSEU energetic-dependent cross-sectional data of a 40 nm SRAM. The results show that for test facilities with abundant <10 MeV neutrons, such as ISIS ChipIR, J-PARC BL10, CSNS Back-n, and CSNS BL09, the terrestrial SER is overestimated. The overestimation could reach 78%–287%. By reducing the cutoff energy (Emin) from 10 to 6 MeV, the overestimation can be decreased. However, the overestimation can still reach up to 164% in this case, significantly larger than the results reported by previous studies. By analyzing the contribution of neutrons in different energy bins to NSEUs, the discrepancy is proved to be attributed to the sensitivity of NSEUs to 0.1–1 MeV neutrons, along with the overpopulation of 0.1–1 MeV neutrons for certain test facilities, such as ISIS ChipIR and CSNS BL09. Therefore, it is necessary to take 0.1–1 MeV NSEU sensitivity into account when studying the prediction method using broad spectrum neutron sources. [ABSTRACT FROM AUTHOR]

Computing-in-Memory (CIM) is a novel computing architecture that enormously improves energy efficiency and reduces computing latency by avoiding frequent data movement between the computation and memory units. Currently, digital CIM is regarded as more suitable for high-precision operations represented in floating-point arithmetic, as it is not limited by the bit width of ADC/DAC in analog CIM. However, the development of DCIM still faces two problems: On the one hand, mainstream SRAM-based DCIM memory cells introduce large area overheads, which contain at least six transistors per cell. On the other hand, existing DCIM solutions can only support the computing precision up to FP32, failing to meet the demands of high-accuracy application scenarios. To overcome these problems, this work designs a novel SOT-MRAM-based digital CIM macro (MDCIM) with higher area/energy efficiency and achieves double-precision floating-point (FP64) computation with a modified fused multiply–accumulate (FMA) module. The proposed design is synthesized with a 55 nm CMOS technology node, achieving 0.62 mW power consumption, 26.9 GOPS/W, and 0.332 GOPS/mm2 energy efficiency at 150 MHz with 1.08 V supply. Circuit level simulation results show that the MDCIM can achieve higher area utilization compared to previous SRAM-based CIM designs. [ABSTRACT FROM AUTHOR]

This paper introduces an 8T single-ended SRAM cell to improve stability and decrease energy consumption. It cuts the pull-down path to the storage node written '1', enhancing the write ability. It uses an isolated read path to enhance the read stability with low power and energy consumption. At a supply voltage of 0.5 V, the read static noise margin, write margin, read energy, and write energy of the proposed cell are superior by 320%, 233%, 12%, and 26%, respectively, compared to the conventional 6T. We performed 5,000 Monte Carlo simulations in the 32 nm technology to evaluate read yields. The results show that our cell has 6.9x more yields than the conventional 6T SRAM cell. Therefore, the proposed cell can be a good option for high stability and low power/energy applications. [ABSTRACT FROM AUTHOR]

SRAM-based physically unclonable function (PUF) is an attractive security primitive for cryptographic protocol and security architecture because SRAM itself is one of the most widely used embedded memories. In terms of robustness, however, there is a weakness for SRAM PUF owing to a bit error; thus, a method must be explored to reduce this error. In this work, a novel hardware chip to characterize cell-to-cell entropy is demonstrated for robust SRAM based PUF by implementation of a screening test to filter out poor cells. We design a chip with a power controller, circuits for error correction coding, a SRAM array and central processing unit. Then it was fabricated by a foundry service. We also propose a procedure to suppress the bit error by use of a screening test, which is based on SRAM cells possessing their own entropy. Through the screening test, the bit error rate (BER) is reduced to below 10 - 6 , which is much smaller than the BER of 0.05 in previous reports, i.e., the robustness is notably improved. Moreover, this robustness was evaluated in terms of an error correction code (ECC) failure rate and temperature after the screening test. SRAM-based PUF with enhanced robustness can contribute to implementing a security protocol and architecture for chip authentication. [ABSTRACT FROM AUTHOR]

Soft errors are the primary concern in space and terrestrial integrated circuit applications. When a charged particle from space collides with a scaled memory circuit, a transient pulse is generated across the sensitive storage node, causing a bit flip throughout the storage nodes. This bit flip is stated as a soft error, which affects the semiconductor memory architecture's stability and reliability. This paper presents a 10 T SRAM (STS-10 T) cell that mitigates soft error challenges even at space temperature. To demonstrate the relative performance of the STS-10 T, existing radiation-hardened memory cells, such as the Quatro-10 T, PS10T, NS-10 T, RHBD-10 T, 10 T-SRAM, RHMD-10 T, QUCCE-10 T, and SIS-10 T, were evaluated. The read stability of the proposed STS-10 T memory cell is 2.6x/ 3x/ 1.5x/ 1.4x/ 1.25x/ 1.6x/ 2.03 × greater than that of the existing Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ RHMD-10 T/ QUCCE-10 T/ SIS-10 T memory cells, respectively. Moreover, 1.48x/ 1.17x/ 1.18x/ 1.4x/ 1.01x/ 1.27x/ 1.45x/ 1.43 × greater write ability than Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ 10 T-SRAM/ RHMD-10 T/ QUCCE-10 T/ SIS10T. In addition, when the supply voltage is at 1 V, the read and write access time, hold power, and critical charge is also improved. [ABSTRACT FROM AUTHOR]

Summary: As the scale of the integrated circuit increases, the distance between transistors decreases, a trend that reduces the critical charge of the sensitive nodes of the memory cell. Consequently, Static Random Access Memory cells in high radiation environments are very prone to soft errors. A novel radiation‐hardened memory cell, the Polarity Reinforcement Feature (PRF)‐18T, is proposed in this paper, which uses the polarity reinforcement feature to reduce the number of sensitive nodes in the memory cell and can entirely and effectively tolerate single event upset and double node upset. A comparison is made in this paper with DICE‐12T, Quatro‐10T, SEA‐14T, RHBD‐14T, NASA‐13T, and SCCS‐18T memory cells in a simulation environment with Semiconductor Manufacturing International Corporation 55 nm process, the supply voltage of 1.2 V, and temperature of 25°C. In comparison, the PRF‐18T proposed in this paper has the highest critical charge value, improving by more than 15× and 3.1× compared to the DICE‐12T and RHBD‐14T, respectively, and by more than 79% and 17.6% compared to the Quatro‐10T and SEA‐14T, respectively. In the high hold static noise margin comparison, the improvement over the SEA‐14T, DICE‐12T, RHBD‐14T, and Quatro‐10T is 26.7%, 3.8×, 1.5×, and 1.2×, respectively. In the write static noise margin comparison, the results were similar to the Quatro‐10T, DICE‐12T, and SEA‐14T, with a 68.5% improvement compared to the RHBD‐14T. Finally, the robustness of the proposed cell to process, voltage, and temperature variations is verified by temperature change experiments and 2000 Monte Carlo model simulations. [ABSTRACT FROM AUTHOR]

A decoupled inverter pair sense amplifier (DIPSA) is proposed for improved sensing in differential SRAM. The DIPSA is designed at 45-nm technology node with a decreased sensing delay of 31.44% and 28.44% over the conventional latch-type sense amplifier (CLSA) and current-latched SA with an NMOS footswitch (CSANF) at 1.1 V, respectively. The performance of DIPSA is validated using delay and power consumption comparison with prior SA designs across a set of supply voltages. Monte Carlo simulation for 3 σ deviation yields a reliable design with no read failures and mean delay of 488.81 ps across the 1k data points with a deviation of 54.87 ps. The threshold voltage variation contribution to process variation is considered for these calculations. The sizing of the decoupling transistors is discussed and its impact on the delay and power of DIPSA shown. The performance of existing voltage and current sense amplifiers is compared to DIPSA. [ABSTRACT FROM AUTHOR]

The October 2023 issue of the IETE Journal of Research contains 70 articles covering various topics in the fields of Communications, Electromagnetics, Optoelectronics, Computers and Computing, Control Engineering, Electronic Circuits, Devices and Components, Instrumentation and Measurement, Medical Electronics, and Power Electronics. The issue includes articles on topics such as the performance of hybrid FSO/RF systems, complexity reduction in UFMC systems, lossless compression of hyperspectral imagery, miniaturized substrate integrated waveguide filters for 5G applications, object tracking using thermal and visible imaging, MIMO diversity antennas for UWB applications, metamaterial-based SWB-MIMO antennas, and more. The issue also features articles on spintronic ripple carry adders, lattice-shifted twist-induced photonic crystal waveguides, software project effort estimation, neural machine translation, supply chain financial risk management, brain computer interfaces, reversible data hiding schemes, IoT-based airshed management, lemmatizers, content-based image retrieval, and named entity recognition. [Extracted from the article]

The current generation aims for Low power electronic gadgets like cell phones, PDAs, etc. This urged demand is met through adopting low power reduction techniques. These gadgets also demand the presence of cache memories, which are fabricated via Static Random Access Memory (SRAM) Cells. Now the challenge is in designing low leakage SRAM cells by adopting power reduction techniques. The proposed work of 7T based Volatile and Non-Volatile SRAM cell is carried through adopting efficient low power reduction technique referred to as Improved Self Controllable Voltage Level (I-SVL). Proposed 7T SRAM cell is based on Improved Self Controllable Voltage Level (I-SVL) technique which controls the supply voltage in Idle and Non Idle mode of SRAM cell. Also Upper-ISVL and Lower-ISVL supplies the Vdd and Vss as per the requirement there by controlling the leakage power. The proposed I-SVL based 7T Volatile and Non-Volatile is designed and simulated using Cadence Virtuoso spectre tool by using CMOS technology with gpdk 45nm. Proposed work carried is efficient in terms of sub threshold and total leakage currents in comparison with the earlier work. The obtained sub threshold and total leakage current of the proposed volatile 7T SRAM cell based on the I-SVL shows improvements in lower values with existing work by 15% and 32%. Also proposed Non-volatile based I-SVL 7T SRAM cell resulted in lesser sub threshold and total leakage current by an amount of 97% and 93% in comparison with the earlier work. The gate leakage current of proposed Non-volatile 7T SRAM cell resulted in 57% lower value in comparison with the earlier work. [ABSTRACT FROM AUTHOR]

In this study, we designed a 6T‐SRAM cell using 16‐nm CMOS process and analyzed the performance in terms of read‐speed latency. The temperature‐dependent Cu and multilayered graphene nanoribbon (MLGNR)‐based nano‐interconnect materials is used throughout the circuit (primarily bit/bit‐bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano‐interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading‐0 and reading‐1 operations. To execute the reading operation, the CMOS technology, that is, the16‐nm PTM‐HPC model, and the16‐nm interconnect technology, that is, ITRS‐13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high‐speed memories using different nano‐interconnect materials. [ABSTRACT FROM AUTHOR]

The technology advances from the micron level to the Nanometer level. This striking change in the technology with so many factors might influence the embedded device design and its performance. In the fast-growing technology, it is very difficult to find suitable algorithms to test embedded SRAM. It is noticed that while going to deep sub-nano technologies, the existing test methods may not fully satisfy the test results due to the increased number of faults and defects. Scale-down technologies have an impact on the parasitic effects, creating an additional source of faulty behavior, and making the existing test techniques less effective in detecting them. In this paper we propose a new method, taking the parasitic effect into the consideration, which gives the fault information along with its location. In the proposed method we have considered node-to-node open and short defects for different technologies (45 nm, 32 nm, and 7 nm). It is observed that the proposed test method gives 100% fault coverage which is independent of technology variation. [ABSTRACT FROM AUTHOR]

This paper presents the benefit of the near-threshold design of random-access memory (SRAM) design to reduce software errors during very low-power operations in nanosatellites. The near-threshold design is based on an optimization of the use of the Schmitt trigger structure for a 45 nm technology. The results of the soft error susceptibility of the optimized design are compared to a standard 6T SRAM cell. These two designs are modeled and validated by comparing the results with experimental measurements of both static noise margin (SNM) and single event upset (SEU). The optimized circuit reduces the multiple upsets occurrence from 95% down to 14%. Based on the use of simulation tools, the paper demonstrates that the near-threshold design of SRAM is an excellent candidate for the radiation point of view for agile nanosatellites. The results computed for the near-threshold SRAM device demonstrate an improvement of a factor of up to 25 of the soft error rate (SER) in a GEO orbit. [ABSTRACT FROM AUTHOR]

The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications. [ABSTRACT FROM AUTHOR]

SRAM cells in spacecraft or space stations are susceptible to single event upset (SEU) caused by high-energy particle impacts. Conventional 6 T SRAM cells are more prone to soft errors in this environment. In this paper, we propose a new highly stable soft-error immune SRAM cell with multi-node upset recovery (SIMR-18 T). This design is an improvement from the Quatro-10 T. The design not only tolerates all SEU and performs well in double node upset (DNU). This paper mainly compares with other structures in terms of read and write access time, static noise margin, and critical charge. The write access time of this cell (11.75 ps) is lower than all other cells. The static noise margin for write, about 1010.11 mV, is 151.87% of that of the QUATRO12T. • Compared with other designs, this structure has higher write and hold static noise margin (WSNM and HSNM). • This design not only tolerates all signal event upset (SEU) and performs well in double node upset (DNU). • This structure has a larger critical charge (Q c) of about 90fc. [ABSTRACT FROM AUTHOR]

This paper proposes a Reconfigurable In-Memory Advance Computing architecture using a novel 10 SRAM cell. In addition to basic logic operations, the proposed R-InMAC can also implement complex Boolean computing operations such as binary addition/subtraction, binary-to-gray, gray-to-binary conversion, 2's complement, less/greater than, and increment/decrement. Furthermore, content addressable memory (CAM) operation to search a binary string in a memory array is also proposed efficiently. It can search true and complementary data strings in a single cycle. The proposed R-InMAC architecture's reconfigurability allows it to be configured according to the needed operation and bit precision, making it ideal and energy-efficient. In addition, compared to the standard SRAM cells, the proposed 10T cell is suited for implementing the XNOR-based binary convolution operation required in Binary Neural Networks (BNNs) with improved latency of 58.89%. The optimized full adder of the proposed R-InMAC shows decrement in the area by 40%, static power by 28%, dynamic power by 55.2%, and latency by 25.3% as compared to conventional designs, making this work a promising candidate for modern edge AI compute in-memory systems. [ABSTRACT FROM AUTHOR]

Research on modeling and mechanisms of the brain remains the most urgent and challenging task. The customized embedded neuromorphic system is one of the most effective approaches for multi-scale simulations ranging from ion channel to network. This paper proposes BrainS, a scalable multi-core embedded neuromorphic system capable of accommodating massive and large-scale simulations. It is designed with rich external extension interfaces to support various types of input/output and communication requirements. The 3D mesh-based topology with an efficient memory access mechanism makes exploring the properties of neuronal networks possible. BrainS operates at 168 MHz and contains a model database ranging from ion channel to network scale within the Fundamental Computing Unit (FCU). At the ion channel scale, the Basic Community Unit (BCU) can perform real-time simulations of a Hodgkin–Huxley (HH) neuron with 16000 ion channels, using 125.54 KB of the SRAM. When the number of ion channels is within 64000, the HH neuron is simulated in real-time by 4 BCUs. At the network scale, the basal ganglia-thalamus (BG-TH) network consisting of 3200 Izhikevich neurons, providing a vital motor regulation function, is simulated in 4 BCUs with a power consumption of 364.8 mW. Overall, BrainS has an excellent performance in real-time and flexible configurability, providing an embedded application solution for multi-scale simulation. [ABSTRACT FROM AUTHOR]

It was shown in [1, 2] that the dependence of the fault tolerance of a static RAM cell on the energy of secondary particles resulting from the action of a neutron flux does not take into account another significant factor—the part of the transistor in which these secondary particles are generated. In order to determine the area of the memory cell in which the impact of secondary particles can lead to a failure, the probability of a failure depending on the location of the occurrence of the secondary particle is studied. A method for analyzing the accumulated charge is proposed for assessing the fault tolerance of a static random access memory cell depending on the place of occurrence of the secondary particle and the charge corresponding to the margin of static noise immunity. The analysis is carried out based on the results of the instrumental-technological simulation of a single MOS transistor, which is part of a static RAM cell, and the integration of the obtained values of the current responses from the regions of the transistor. [ABSTRACT FROM AUTHOR]

Due to the rapid technology scaling and increasing program/erase cycles, the raw bit error rate (RBER) in NAND flash memory keeps increasing rapidly. This dilemma seriously incurs reliability issues. The traditional error correction codes (ECCs) with stronger protection capability are usually equipped for all flash pages as a solution to maintain the mandatory yield and reliability levels. However, the growth of RBER is exponentially proportional to the number of induced P/E cycles and the distributions of errors are usually uneven. Therefore, the conventional uniform ECC protection based on the worst scenario of fault distributions might incur unnecessary hardware and latency overhead. Moreover, the overlong ECC check bits might be stored in two different flash pages. Therefore, two flash read/program operations are required for reading/programming a codeword. To cure these drawbacks, the ECC Caching (E3C) techniques are proposed in this paper. The main idea is to upgrade the ECC protection levels for flash pages when their correction slack is below the specified threshold. An ECC Cache containing the ECC CAM and the ECC SRAM is used for accessing and storing extra check bits, respectively. The corresponding repair flow and hardware architecture are also proposed. According to simulation results, we can enhance the reliability and yield of flash memories significantly with negligible hardware cost. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a highly stable and low‐cost 12T (HSLC12T) radiation hardened static‐random‐access‐memories (SRAM) cell is proposed in 55 nm CMOS technology. Based on polarity reversal design and read/write separation structure, the proposed HSLC12T cell can recover from any single event upsets (SEUs) induced at all its sensitive nodes and even single event double‐node‐upsets (SEDNUs) induced at its internal storage node pair Q‐QN, while also having the maximum read static noise margin (RSNM) and lower static hold power, as well as excellent write speed and write‐ability. Though the HSLC12T cell exhibits a larger read delay, it has the best overall performance of all other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed HSLC12T cell a better choice for aerospace applications. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuit for the 9T Schmitt trigger-based static random-access memory (SRAM) cell (9T-ST), significantly improving write performance for real-time memory applications. In deep sub-micron technology, increasing device parameter deviations significantly reduce SRAM cells' write-ability. The proposed RNBLCS write-assist driver for 9T-ST SRAM cell has 0.84×, 0.48×, 0.27× optimized write access delay and 1.05×, 1.08×, 1.19× improvement in write static noise margin (WSNM), 1.05×, 1.13×, and 1.39× improvement in write margin (WM), 0.96×, 0.89× and 0.72× minimum write trip-point (WTP) from transient-negative bit line (Tran-NBL), capacitive charge sharing (CCS), and conventional write circuits respectively. The proposed RNBLCS is functionally verified using a synopsys custom compiler with a 16 nm BSIM4 model card for bulk complementary metal-oxide semiconductor (CMOS). [ABSTRACT FROM AUTHOR]

In this paper, the single event effect of 6T-SRAM is simulated at circuit level and device level based on a 22 nm fully depleted silicon-on-insulator (FDSOI) process, and the effects of charge sharing and bipolar amplification are considered in device-level simulation. The results demonstrate that, under the combined influence of these two effects, the circuit's upset threshold and critical charge decreased by 15.4% and 23.5%, respectively. This indicates that the charge sharing effect exacerbates the single event effects. By analyzing the incident conditions of two different incident radius particles, it is concluded that the particles with a smaller incident radius have a worse impact on the SRAM circuit, and are more likely to cause the single event upset in the circuit, indicating that the ionization distribution generated by the incident particle affects the charge collection. [ABSTRACT FROM AUTHOR]

Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., <12b, show lower accuracy but higher power efficiency. An input precision of 8b achieves implementation requirements. The maximum performance reported is 7.49 TOPS at 330 MHz, while custom SRAM-based performance has shown a maximum of 5.6 GOPS at 100 MHz. The second part of this article analyzes the FinFET 6T-SRAM as one of the critical components in determining overall performance of an AI computing system. We have investigated the FinFET 6T-SRAM cell performance and limitations as dictated by the FinFET technology-specific parameters, such as sizing, threshold voltage (Vth), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values. [ABSTRACT FROM AUTHOR]

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Optical computing, based on the photonic CMOS technology, may substantially improve the analog or digital processing capabilities, and expand silicon photonics markets. There are two types of optical computing: photon-assisted optoelectronic computing and quantum optical computing. The former requires no change in existing circuit designs. The latter may require new features in logic designs, so is suitable for newly developed sections that are connected and fully compatible with existing sub-5nm ULSI circuits. In this paper, we will discuss how to implement the coherent micro-holographic effects, generated by photonic CMOSFETs, for optical computers. [ABSTRACT FROM AUTHOR]

With the development of modern computer storage technology, the spin-transfer torque magnetic random-access memory (STT-MRAM) has become one of the most promising candidates to replace the static random-access memory and dynamic random-access memory. However, its large power consumption and long relaxation time before the magnetic moments switch are important factors restricting its commercial application. In this work, gradient-current pulses are proposed to replace the conventional constant-current pulses in the injection method. A 70-nm classical CoFeB/MgO/CoFeB magnetic tunnel junction (MTJ) with perpendicular magnetic anisotropy was simulated and measured at pulse widths of 20, 30, and 40 ns using the proposed and conventional injection pulses. The comparison results show that adopting gradient pulses can significantly reduce the relaxation time and switching power consumption of the MTJ. A power consumption reduction of 8%–40% is obtained at different pulse amplitudes and widths. Our method paves an avenue for overcoming the issues affecting the STT-MRAM and could help to promote its commercial applications. [ABSTRACT FROM AUTHOR]

The Cu-CNT composite is obtained by depositing Cu around CNT bundles via electrodeposition, while coating the Cu-CNT with graphene layers via plasma enhanced chemical vapor deposition results in the Cu-carbon hybrid structure. Kumari I et al. i study the electro-thermal aspects and reliability of Cu-carbon hybrid interconnects.[41] In their analysis, the authors consider multiple different structures such as Cu-GNR hybrid, Cu-CNT composite, and Cu-carbon hybrid. Metals like Ru are a promising replacement for Cu due to their resistance to oxidation, high melting point, low bulk resistivity, and the ability to build barrier-less interconnect modules.[[29]] Yet, electron scatterings remain an obstacle even in the case of Ru. On the other hand, topological semimetals introduce completely new physics and are expected to have a size-insensitive resistivity or even a decrease in resistivity with decreasing line dimensions.[31] Both Weyl semimetals and multifold-fermion semimetals, which are sub-classes of topological semimetals, have been studied as alternative interconnect materials at advanced technology nodes. [Extracted from the article]

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell. [ABSTRACT FROM AUTHOR]

This article examines the development of a low power FINFET SRAM and applying different techniques to reduce leakage current. Due to scalability, the CMOS parameters are not providing reliable values at lower technology nodes. Researchers are looking for solutions to mitigate the negative consequences of MOSFET scaling, and FINFET has emerged as one of the best substitutes since it has better control over the gate and provide better performance parameters like it conserves less energy, eliminates short-channel effects, and reduces leakage current at sub-32 nm regime. Since the number of battery-powered portable devices has dramatically increased, electronic devices must be operated for longer time once the battery has charged. To achieve this the device should have less leakage current so that least amount of leakage power is possible which results in devices to operate for long periods of time. At first, a 6-T CMOS SRAM was designed, and all the parameters were calculated. Subsequently, DG-FINFET SRAM was developed, and all the parameters were calculated. The 6 T cell design based on FinFET consumes considerably less power than the 6 T SRAM designed by CMOS. Additionally, it features hold SNM and RSNM are better than the CMOS 6 T cell by 18% and 26% respectively. To reduce leakage current further in the FinFET SRAM many leakages current reduction techniques are applied and evaluated, which results MTCMOS technique reduced leakage current by 21.38%, SVL by 13.15%, AVL by 17.19% and proposed technique by 24.31%, which shows that the proposed technique has less leakage current than all the techniques discussed. [ABSTRACT FROM AUTHOR]

Summary: Static random‐access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect. [ABSTRACT FROM AUTHOR]

Radiation‐induced soft errors are becoming a key challenge in satellite‐based communication. The worst‐hit component of such devices is static random‐access memory bit‐cells, owing to their high density, large area, and low‐operating voltage. The unsuitability of conventional 6T SRAM for this purpose is ascertained by weak stability constraints, higher variability during process variations, and less tolerance capability in such a harsh environment. In this work, we have presented an improved, feedback charge‐boosted, and read decoupled 11 transistors based (FC11T) SRAM cell. Its performance is assessed by comparing it with other low power, high stability, and soft‐error‐immune SRAM cells, namely, Asymmetric 8T (AS8T), Quatro 10T, PPN based 10T (PP10T), and loop cutting 10T (LC10T) cells over various design metrics. The attained observations establish that the proposed FC11T shows 1.13×/1.38×/0.90×/1.04×/1.03× improvement in critical charge compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The read access time of proposed FC11T cell is reduced by 1.31×/1.17×/1.31×/1.41×/1.01× compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The proposed cell further strengthens read stability by 1.97×/0.98×/1.91×/1.24×/1× when equated to 6T/PP10T/AS8T/Quatro10T/LC10T cell. Improved Inter‐cell and Intra‐cell soft error ratios represent improved soft error mitigation capability of the proposed 11T cell over 0.5 to 1 V supply voltage and 27 to 125 C temperature variation range. In addition to this, the proposed 11T cell also shows improved read stability and writability. [ABSTRACT FROM AUTHOR]

This paper presents radiation hardened SRAM (namely LPDNUR and HSDNUR), both of which can self-recover from single-node and double-node upsets. LPDNUR uses a two-input C-element structure, which reduces the average power consumption because the stacked effect. Moreover, in order to reduce read access time (RAT) and write access time (WAT), the paper proposes HSDNUR, which uses a combination of NMOS and PMOS as the transistor for one-node data transmission, an approach that increases the current drive capability and reduces transmission delays. Compared to the state-of-the-art radiation-hardened SRAM design, such as QUCCE10T, QUCCE12T, We-Quatro, etc. The model results show that the average power consumption of LPDNUR is reduced by 24.59% on average, and the RAT and WAT of HSDNUR are reduced by an average of 35.71% and 24.14% respectively. • LPDNUR and HSDNUR fully achieve SNU and DNU recovery. • Average power of LPDNUR is 24.59% lower on average than other SRAM hardened since stack structure. • WAT and RAT of HSDNUR are 24.14% and 35.71% lower than other SRAM hardened on average by using TG. [ABSTRACT FROM AUTHOR]