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The cross-point architecture for memory arrays is widely considered as one of the most attractive solutions for storage and memory circuits thanks to simplicity, scalability, small cell size, and consequently high density and low cost. Cost-scalable vertical 3-D cross-point architectures, in particular, offer the opportunity to challenge Flash memory with comparable density and cost. To develop scalable cross-point arrays, however, select devices with sufficient ON–OFF ratio, current capability, and endurance must be available. This paper presents a select device technology based on volatile resistive switching with Cu and Ag top electrode and silicon oxide (SiO x ) switching materials. The select device displays ultrahigh resistance window and good current capability exceeding 2 MAcm−2. Retention study shows a stochastic voltage-dependent ON–OFF transition time in the ${10}~\mu \text{s}$ –1 ms range, which needs to be further optimized for fast memory operation in storage class memory arrays.

The semiconductor industry is currently challenged by the emergence of Internet of Things, Big data, and deep-learning techniques to enable object recognition and inference in portable computers. These revolutions demand new technologies for memory and computation going beyond the standard CMOS-based platform. In this scenario, resistive switching memory (RRAM) is extremely promising in the frame of storage technology, memory devices, and in-memory computing circuits, such as memristive logic or neuromorphic machines. To serve as enabling technology for these new fields, however, there is still a lack of industrial tools to predict the device behavior under certain operation schemes and to allow for optimization of the device properties based on materials and stack engineering. This work provides an overview of modeling approaches for RRAM simulation, at the level of technology computer aided design and high-level compact models for circuit simulations. Finite element method modeling, kinetic Monte Carlo models, and physics-based analytical models will be reviewed. The adaptation of modeling schemes to various RRAM concepts, such as filamentary switching and interface switching, will be discussed. Finally, application cases of compact modeling to simulate simple RRAM circuits for computing will be shown.

The understanding of the dynamic mechanism of volatile resistive switching memory devices is of paramount importance to further increase the switching speed. It is also of great value for future neuromorphic applications which use such devices in temporal domain. In this work, we investigate the switching speed and retention time of metallic filamentary volatile resistive switching devices. We find that the switching speed can be quantitatively described by the ionic mobility, while the retention time can be quantitatively described by the surface ionic diffusion following the gradient descent of surface atomic concentration. Further analysis reveals that the ionic mobility and surface diffusivity can be connected with Einstein relation. Finally, evidences supporting this relation and experimental data showing the competition of the ionic drift and diffusion are collected and shown.

The in-memory solution of linear systems with analog resistive switching memory in one computational step has been recently reported. In this work, we investigate the time complexity of solving linear systems with the circuit, based on the feedback theory of amplifiers. The result shows that the computing time is explicitly independent on the problem size N, rather it is dominated by the minimal eigenvalue of an associated matrix. By addressing the Toeplitz matrix and the Wishart matrix, we show that the computing time increases with log(N) or N1/2, respectively, thus indicating a significant speed-up of in-memory computing over classical digital computing for solving linear systems. For sparse positive-definite matrix that is targeted by a quantum computing algorithm, the in-memory computing circuit also shows a computing time superiority. These results support in-memory computing as a strong candidate for fast and energy-efficient accelerators of big data analytics and machine learning.

Neuromorphic computing has emerged as a promising approach for autonomous systems able to learn, adapt, and interact in real time with the environment. To build neuromorphic hardware, the recent development of novel material-based devices such as resistive switching memory (RRAM) has shown to be crucial since this class of devices offers the unique advantage to implement neuron and synaptic functions in silico by device physics, thus avoiding bulky circuits and very complex algorithms. In this work, we first explore volatile switching behaviour of RRAM devices, investigating their ability to capture short-term plasticity (STP) and short-term memory (STM) functionalities. Then, we characterise a volatile RRAM synapse, discussing its potential use in a spiking neural network for speech recognition applications.

In this paper we propose a new method of estimating Joule heating in a resistive switching SiO x based device through the use of a micro-thermal stage (MTS). We show an electro-thermal characterization of the device during set/reset operation using the MTS structure as a thermometer, we then attempt to reconstruct the complete heating profile of the device through numerical modeling in COMSOL, then we simulate the reset condition of the device.

Spin-transfer torque random access memory (STT-RAM) is gaining momentum as a promising technology for high density and embedded nonvolatile memory. To enable the design of STT-RAM circuits for memory and computing, there is a need for accurate compact models capable of predicting the stochastic behavior. Here, we present a detailed model accounting for the anomalous thermal regime of switching deviating from the thermal model below 200 ns. Anomalous switching is explained by the non-linear barrier lowering of the perpendicular magnetic anisotropy (PMA). The model is validated against write error rate (WER) data and applied to the design of random number generator (RNG) and stochastic computing primitives with STT-RAM.

In the era of big data, there is a strong urge for novel methodologies of computing large amount of unstructured data with short latency and low power. Toward this goal, in-memory computing has emerged as a paradigm shift to enable processing the data directly within or close to the memory, thus overcoming the memory wall typical of the von Neumann architecture [1]. Computation within resistive memory devices, such as resistive switching memory (RRAM) and phase change memory (PCM) has the additional advantage of physical computing, where data are processed via fundamental physical laws, such as the Ohm's law and the Kirchhoff's law, thus enabling a massive parallelism and the consequent acceleration of computational tasks, such as the matrix-vector multiplication (MVM). In this work, we will demonstrate an extreme speedup for solving matrix algebra problems, such as solution of linear systems or calculation of eigenvectors, via MVM in crosspoint arrays of resistive memory devices with feedback configuration [2].

This work presents an optimized model for resistance evolution in PCM cells with Ge-rich GeSbTe (GST) alloy as active material. Unlike conventional Ge 2 Sb 2 Te 5 , the low-resistance (set) state of Ge-rich GST shows a resistance drift to high resistance R, similar to the high resistance (reset) state, which could be a potential risk for data reliability. We develop a Monte Carlo (MC) model which predicts the time evolution of R at the statistical level of a memory array at various temperature T. The model is validated against variable temperature annealing, such as the soldering profile in embedded PCM, supporting the good reliability of Ge-rich GST at high T.

Spin-transfer torque random-access memory (STT-RAM) is gaining momentum as a promising technology for high-density and embedded nonvolatile memory. Owing to random thermal fluctuations, switching transitions generally display statistical variations from cycle to cycle. Stochastic variations are critical to the hindering of memory and computing applications of STT-RAM. To enable the design of STT-RAM circuits for memory and computing, there is a need for accurate compact models capable of predicting the stochastic behavior. Here, we present a detailed model accounting for the anomalous thermal regime of switching deviating from the Neel–Brown thermal model below 200 ns. Anomalous switching is explained by the nonlinear lowering of the energy barrier associated with the perpendicular magnetic anisotropy (PMA). The model is extensively verified against the write-error-rate (WER) data as a function of applied voltage and pulsewidth and experimental switching time-delay distributions.

Electrochemical metallization ReRAMs (ECM) - Experiments and modelling: General discussion

Producción Científica, Recently, artificial intelligence reached impressive milestones in many machine learning tasks such as the recognition of faces, objects, and speech. These achievements have been mostly demonstrated in software running on high-performance computers, such as the graphics processing unit (GPU) or the tensor processing unit (TPU). Novel hardware with in-memory processing is however more promising in view of the reduced latency and the improved energy efficiency. In this scenario, emerging memory technologies such as phase change memory (PCM) and resistive switching memory (RRAM), have been proposed for hardware accelerators of both learning and inference tasks. In this work, a multilevel 4kbit RRAM array is used to implement a 2-layer feedforward neural network trained with the MNIST dataset. The performance of the network in the inference mode is compared with recently proposed implementations using the same image dataset demonstrating the higher energy efficiency of our hardware, thanks to low current operation and an innovative multilevel programming scheme. These results support RRAM technology for in-memory hardware accelerators of machine learning., German Research Foundation (grant FOR2093)

Producción Científica, Training and recognition with neural networks generally require high throughput, high energy efficiency, and scalable circuits to enable artificial intelligence tasks to be operated at the edge, i.e., in battery-powered portable devices and other limited-energy environments. In this scenario, scalable resistive memories have been proposed as artificial synapses thanks to their scalability, reconfigurability, and high-energy efficiency, and thanks to the ability to perform analog computation by physical laws in hardware. In this work, we study the material, device, and architecture aspects of resistive switching memory (RRAM) devices for implementing a 2-layer neural network for pattern recognition. First, various RRAM processes are screened in view of the device window, analog storage, and reliability. Then, synaptic weights are stored with 5-level precision in a 4 kbit array of RRAM devices to classify the Modified National Institute of Standards and Technology (MNIST) dataset. Finally, classification performance of a 2-layer neural network is tested before and after an annealing experiment by using experimental values of conductance stored into the array, and a simulation-based analysis of inference accuracy for arrays of increasing size is presented. Our work supports material-based development of RRAM synapses for novel neural networks with high accuracy and low-power consumption., European Union’s Horizon 2020 research and innovation programme (Grant Agreement No. 648635), German Research Foundation (grant FOR2093)

Artificial neural networks (ANNs) can outperform the human ability of object recognition by supervised training of synaptic parameters with large datasets. Contrarily to the human brain, however, ANNs cannot continually learn, i.e. acquire new information without catastrophically forgetting previous knowledge. To solve this issue, we present a novel hybrid neural network based on CMOS logic and phase change memory (PCM) synapses, mixing a supervised convolutional neural network (CNN) with bio-inspired unsupervised learning and neuronal redundancy. We demonstrate high classification accuracy in MNIST and CIFAR10 datasets (98% and 85%, respectively) and energy-efficient continual learning of up to 30% of non-trained classes with 83% average accuracy.

Valence change ReRAMs (VCM) - Experiments and modelling: General discussion

Memristive devices, such as resistive switching memory (RRAM) and phase change memory (PCM), show variable resistance which can mimic the synaptic plasticity in the human brain. This fascinating analogy has provided the inspiration for many recent research advances, involving memristive devices and their use as artificial electronics synapses in neuromorphic circuits with learning capability. In particular, RRAM-based artificial synapses are extremely promising in terms of area efficiency, low power consumption, and flexibility of design which pave the way for spiking neural networks that perform and behave like the human brain. This chapter will review the state of the art about the design and development of memristive neural networks for unsupervised learning. First, the optimization of RRAM devices for synaptic applications will be discussed, and a novel RRAM device with improved resistance window and controllability of resistance will be introduced. Then, a hybrid CMOS/memristive synaptic circuit will be shown to carry out learning tasks via the spike-timing dependent plasticity (STDP), which is one of the learning rules in biological synapses. Finally, the neural networks based on RRAM synapses will be reviewed, covering both feed-forward networks and recurrent networks. In both cases, the network displays unsupervised learning of input patterns, which can be stored, recognized, or even reconstructed by the network, thus highlighting the wealth of potential promising applications for memristive networks with synaptic plasticity.

In our brain, information is exchanged among neurons in the form of spikes where both the space (which neuron fires) and time (when the neuron fires) contain relevant information. Every neuron is connected to other neurons by synapses, which are continuously created, updated, and stimulated to enable information processing and learning. Realizing the brain-like neuron/synapse network in silicon would enable artificial autonomous agents capable of learning, adaptation, and interaction with the environment. Toward this aim, the conventional microelectronic technology, which is based on complementary metal–oxide–semiconductor transistors and the von Neumann computing architecture, does not provide the desired energy efficiency and scaling potential. A generation of emerging memory devices, including resistive switching random access memory (RRAM) also known as the memristor, can offer a wealth of physics-enabled processing capabilities, including multiplication, integration, potentiation, depression, and time-decaying stimulation, which are suitable to recreate some of the fundamental phenomena of the human brain in silico. This work provides an overview about the status and the most recent updates on brain-inspired neuromorphic computing devices. After introducing the RRAM device technologies, we discuss the main computing functionalities of the human brain, including neuron integration and fire, dendritic filtering, and short- and long-term synaptic plasticity. For each of these processing functions, we discuss their proposed implementation in terms of materials, device structure, and brain-like characteristics. The rich device physics, the nano-scale integration, the tolerance to stochastic variations, and the ability to process information in situ make the emerging memory devices a promising technology for future brain-like hardware intelligence.

Current overshoot due to parasitic capacitance during set transition represents a major concern for controlling the resistance and current consumption in resistive switching memory (RRAM) arrays. In this letter, the impact of current overshoot on the low-resistance state (LRS) is evaluated by means of experiments on one-transistor/one-resistor structures of HfO2 RRAM. We develop a physics-based analytical model, able to calculate the LRS resistance and the corresponding reset current by a closed-form formula. The model allows predicting the current overshoot impact for any value of compliance current, set voltage, and parasitic capacitance.

In-memory computing (IMC) is gaining momentum for low-power acceleration of data intensive problems, particularly in the frame of artificial intelligence (AI). Analogue matrix-vector multiplication (MVM) in crosspoint arrays allows to dramatically improve energy efficiency in neural networks for inference and training [1]. Recently, it has been shown that a feedback configuration of MVM can accelerate the solution of generic linear matrix problems, such as linear systems, matrix inversion and eigenvector calculation, with a single computational step [2,3]. This is achieved by the high parallelism of MVM in the memory array, combined with the physical iteration executed naturally in the feedback loop. Eigenvector extraction allows to address general problems, such as PageRank of internet webpages, with complexity O(1), i.e., the time to solve a ranking problem remains fixed irrespective of the size of the coefficient matrix [4]. In this work, we address two specific problems of AI acceleration, namely regression and optimization. Linear regression can be viewed as one of the most basic problems of machine learning: given a sequence of points, one must predict the value of the next point in the sequence. This problem can be solved in just one computational step by using the closed-loop crosspoint array of Fig. 1, where the independent variables x_i are physically written within the two crosspoint arrays, while the dependent variables y_i are applied externally as input currents. The crosspoint arrays are connected within a closed-loop configuration by using operational amplifiers (OAs) in the rows and the columns of the arrays. The OA output yields the coefficients of the best fitting line along the sequence, i.e., the coefficients a and b in the line equation y= ax + b providing the least mean squares (LMS) regression of the sequence. This problem can be extended to any arbitrary dimension, i.e., not only data on x-y plane, but also data on x-y-z space and any hyperspace of n dimensions. The problem can also be extended to logistic regression, which enables classification in one computational step. In particular, the crosspoint regression circuit allows the training of a 2-layer perceptron in just one step, by assuming random weights in the first layer according to the extreme learning machine (ELM) approach. In-memory computing thus appears as a promising option for accelerating neural network training with complexity O(1). The continuous-time, analogue closed-loop approach can be extended to a discrete-time, digital recurrent neural network (RNN) for addressing optimization problems [5]. The RNN allows the efficient solution of constraint satisfaction problems (CSPs), such as Sudoku, by taking advantage of analogue MVM in the crosspoint array. In the RNN, stochastic iterations can allow the minimization of the cost function, hence the number of violated constraints, thus leading to the global minimum. Noise can be injected as spike jitter by phase change memory devices as integrate-and-fire neurons. The convergence to the solution can be efficiently accelerated by a 2-layer RNN, where the first layer is programmed to prevent the violation of constraints in the CSP. In-memory solution of CSPs can dramatically improve the energy efficiency and speed of data intensive optimization in transport, industry, and society in general. References [1] D. Ielmini and G. Pedretti, “Device and circuit architectures for in-memory computing,” Adv. Intell. Syst. 2000040 (2020). [2] Z. Sun, G. Pedretti, E. Ambrosi, A. Bricalli, W. Wang and D. Ielmini, “Solving matrix equations in one step with crosspoint resistive arrays,” PNAS 116 (10) 4123-4128 (2019). [3] Z. Sun, G. Pedretti, A. Bricalli, D. Ielmini, “One-step regression and classification with crosspoint resistive memory arrays,” Sci. Adv. 6:eaay2378 (2020). [4] Z. Sun, G. Pedretti, E. Ambrosi, A. Bricalli, and D. Ielmini, “In-memory eigenvector computation in time O(1),” Adv. Intell. Sys. (2020). [5] G. Pedretti, P. Mannocci, S. Hashemkhani, V. Milo, O. Melnic, E. Chicca, and D. Ielmini, “A spiking recurrent neural network with phase change memory neurons and synapses for the accelerated solution of constraint satisfaction problems,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits 6 (2019). Figure 1

Acting as artificial synapses, two‐terminal memristive devices are considered fundamental building blocks for the realization of artificial neural networks. Current memristive crossbar architectures demonstrate the implementation of neuromorphic computing paradigms, although they are unable to emulate typical features of biological neural networks such as high connectivity, adaptability through reconnection and rewiring, and long‐range spatio‐temporal correlation. Herein, self‐organizing memristive random nanowire (NW) networks with functional connectivity able to display homo‐ and heterosynaptic plasticity is reported thanks to the mutual electrochemical interaction among memristive NWs and NW junctions. In particular, it is shown that rewiring and reweighting effects observed in single NWs and single NW junctions, respectively, are responsible for structural plasticity of the network under electrical stimulation. Such biologically inspired systems allow a low‐cost realization of neural networks that can learn and adapt when subjected to multiple external stimuli, emulating the experience‐dependent synaptic plasticity that shape the connectivity and functionalities of the nervous system that can be exploited for hardware implementation of unconventional computing paradigms.

In-memory computing with crosspoint resistive memory arrays has gained enormous attention to accelerate the matrix-vector multiplication in the computation of data-centric applications. By combining a crosspoint array and feedback amplifiers, it is possible to compute matrix eigenvectors in one step without algorithmic iterations. In this work, time complexity of the eigenvector computation is investigated, based on the feedback analysis of the crosspoint circuit. The results show that the computing time of the circuit is determined by the mismatch degree of the eigenvalues implemented in the circuit, which controls the rising speed of output voltages. For a dataset of random matrices, the time for computing the dominant eigenvector in the circuit is constant for various matrix sizes, namely the time complexity is O(1). The O(1) time complexity is also supported by simulations of PageRank of real-world datasets. This work paves the way for fast, energy-efficient accelerators for eigenvector computation in a wide range of practical applications., Accepted by Adv. Intell. Syst

Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

Volatile resistive switching memory (RRAM) is raising strong interest as potential selector device in crosspoint memory and short-term synapse in neuromorphic computing. To enable the design and simulation of memory and computing circuits with volatile RRAM, compact models are essential. To fill this gap, we present here a novel physics-based analytical model for volatile RRAM based on a detailed study of the switching process by molecular dynamics (MD) and finite-difference method (FDM). The analytical model captures all essential phenomena of volatile RRAM, e.g., threshold/holding voltages, on-off ratio, and size-dependent retention. The model is validated by extensive comparison with data from Ag/SiO x ), RRAM. To support the circuit-level capability of the model, we show simulations of crosspoint arrays and neuromorphic time-correlated learning.

Brain-inspired computation can revolutionize information technology by introducing machines capable of recognizing patterns (images, speech, video) and interacting with the external world in a cognitive, humanlike way. Achieving this goal requires first to gain a detailed understanding of the brain operation, and second to identify a scalable microelectronic technology capable of reproducing some of the inherent functions of the human brain, such as the high synaptic connectivity (~10

Brain-inspired neural networks can process information with high efficiency, thus providing a powerful tool for pattern recognition and other artificial intelligent tasks. By adopting binary inputs/outputs, neural networks can be used to perform Boolean logic operations, thus potentially surpassing complementary metal-oxide-semiconductor logic in terms of area efficiency, execution time, and computing parallelism. Here, the concept of stateful neural networks consisting of resistive switches, which can perform all logic functions with the same network topology, is introduced. The neural network relies on physical computing according to Ohm's law, Kirchhoff 's law, and the ionic migration within an output switch serving as the highly nonlinear activation function. The input and output are nonvolatile resistance states of the devices, thus enabling stateful and cascadable logic operations. Applied voltages provide the synaptic weights, which enable the convenient reconfiguration of the same circuit to serve various logic functions. The neural network can solve all two-input logic operations with just one step, except for the exclusive-OR (XOR) needing two sequential steps. 1-bit full adder operation is shown to take place with just two steps and five resistive switches, thus highlighting the high efficiencies of space, time, and energy of logic computing with the stateful neural network.

Interest in resistance switching is currently growing apace. The promise of novel high-density, low-power, high-speed nonvolatile memory devices is appealing enough, but beyond that there are exciting future possibilities for applications in hardware acceleration for machine learning and artificial intelligence, and for neuromorphic computing. A very wide range of material systems exhibit resistance switching, a number of which-primarily transition metal oxides-are currently being investigated as complementary metal-oxide-semiconductor (CMOS)-compatible technologies. Here, the case is made for silicon oxide, perhaps the most CMOS-compatible dielectric, yet one that has had comparatively little attention as a resistance-switching material. Herein, a taxonomy of switching mechanisms in silicon oxide is presented, and the current state of the art in modeling, understanding fundamental switching mechanisms, and exciting device applications is summarized. In conclusion, silicon oxide is an excellent choice for resistance-switching technologies, offering a number of compelling advantages over competing material systems.

Modern computers are based on the von Neumann architecture in which computation and storage are physically separated: data are fetched from the memory unit, shuttled to the processing unit (where computation takes place) and then shuttled back to the memory unit to be stored. The rate at which data can be transferred between the processing unit and the memory unit represents a fundamental limitation of modern computers, known as the memory wall. In-memory computing is an approach that attempts to address this issue by designing systems that compute within the memory, thus eliminating the energy-intensive and time-consuming data movement that plagues current designs. Here we review the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, their resistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation. We examine the different digital, analogue, and stochastic computing schemes that have been proposed, and explore the microscopic physical mechanisms involved. Finally, we discuss the challenges in-memory computing faces, including the required scaling characteristics, in delivering next-generation computing. This Review Article examines the development of in-memory computing using resistive switching devices.

Hardware processors for neuromorphic computing are gaining significant interest as they offer the possibility of real in-memory computing, thus by-passing the limitations of speed and energy consumption of the von Neumann architecture. One of the major limitations of current neuromorphic technology is the lack of bio-realistic and scalable devices to improve the current design of artificial synapses and neurons. To overcome these limitations, the emerging technology of resistive switching memory has attracted wide interest as a nano-scaled synaptic element. This paper describes the implementation of a perceptron-like neuromorphic hardware capable of spike-timing dependent plasticity (STDP), and its operation under stochastic learning conditions. The learning algorithm of a single or multiple patterns, consisting of either static or dynamic visual input data, is described. The impact of noise is studied with respect to learning efficiency (false fire, true fire) and learning time. Finally, the impact of stochastic learning rule, such as the inversion of the time dependence of potentiation and depression in STDP, is considered. Overall, the work provides a proof of concept for unsupervised learning by STDP in memristive networks, providing insight into the dynamics of stochastic learning and supporting the understanding and design of neuromorphic networks with emerging memory devices.

The development of neuromorphic systems capable of mimicking the behavior of the human brain has recently received an increasing deal of interest. However, the building of such artificial systems has been hindered by the lack of commercial technologies with nanoscale integration of synaptic devices as well as the complexity of the biological neural architecture in terms of connectivity, parallelism, and plasticity behavior. In particular, there is a wide consensus on the relevance of recurrent connections in the human brain, and their key role for associative learning and pattern classification. Fundamental primitives of cognitive computing can therefore be demonstrated by means of Recurrent Neural Networks (RNNs). In this work, we design and simulate a Hopfield-type RNN with HfO2 RRAM devices capable of learning via spike-timing dependent plasticity (STDP). We first demonstrate learning and recall of a single attractor state in a 4-neuron RNN. Based on this result, we then simulate signal restoration of two orthogonal patterns in a 64-neuron RNN, thus supporting RRAM-based RNN with cognitive computing functionalities.

Emerging memory devices such as resistive switching memory (RRAM) and phase change memory (PCM) are gaining interest as future synapses for smart neuromorphic systems, capable of learning and inference similar to the human brain. Developing neuromorphic systems with emerging memory technologies requires accurate co-design of devices, synapses, and neural networks, aiming at the replication of the fundamental learning processes in the human brain, such as spike-timing dependent plasticity (STDP) and spike-rate dependent plasticity (SRDP). This work addresses the development of RRAM synapses for unsupervised learning via STDP. This learning scheme is implemented in a simple one-transistor/one-resistor (1T1R) structure capable of long term potentiation and depression with standard memory-grade RRAM devices. 1T1R synapses are implemented in a spiking neural network (SNN) with feedforward architecture, allowing for the hardware demonstration of unsupervised learning. Recurrent SNNs employing the same fundamental STDP rule are then addressed by simulation of associative learning, pattern reconstruction, and recall of spatiotemporal sequences.

Perpendicular spin-transfer torque (p-STT) magnetic memory is gaining increasing interest as a candidate for storage-class memory, embedded memory, and possible replacement of static/dynamic memory. All these applications require extended cycling endurance, which should be based on a solid understanding and accurate modeling of the endurance failure mechanisms in the p-STT device. This paper addresses cycling endurance of p-STT memory under pulsed electrical switching. We show that endurance is limited by the dielectric breakdown of the magnetic tunnel junction stack, and we model endurance lifetime by the physical mechanisms leading to dielectric breakdown. The model predicts STT endurance as a function of applied voltage, pulsewidth, pulse polarity, and delay time between applied pulses. The dependence of the endurance on sample area is finally discussed.

Resistive switching devices were used as technological synapses to learn about the spatial- and temporal-correlated neuron spikes., The human brain is a complex integrated spatiotemporal system, where space (which neuron fires) and time (when a neuron fires) both carry information to be processed by cognitive functions. To parallel the energy efficiency and computing functionality of the brain, methodologies operating over both the space and time domains are thus essential. Implementing spatiotemporal functions within nanoscale devices capable of synaptic plasticity would contribute a significant step toward constructing a large-scale neuromorphic system that emulates the computing and energy performances of the human brain. We present a neuromorphic approach to brain-like spatiotemporal computing using resistive switching synapses. To process the spatiotemporal spike pattern, time-coded spikes are reshaped into exponentially decaying signals that are fed to a McCulloch-Pitts neuron. Recognition of spike sequences is demonstrated after supervised training of a multiple-neuron network with resistive switching synapses. Finally, we show that, due to the sensitivity to precise spike timing, the spatiotemporal neural network is able to mimic the sound azimuth detection of the human brain.

The Collaborative Innovation Center of Suzhou Nano Science & Technology, the Jiangsu Key Laboratory for Carbon-Based Functional Materials & Devices, and the Priority Academic Program Development of Jiangsu Higher Education Institutions are also acknowledged. Stanford co-authors acknowledge support from the Non-volatile Memory Technology Research Initiative (NMTRI). An Chen from IBM is acknowledged for revision of section 5. Alok Ranjan from Singapore University of Technology and Design is acknowledged for useful discussion on section 3.5., Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, being electronic non-volatile memories those that have received most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. In this manuscript we describe the most recommendable methodologies for the fabrication, characterization and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology., This work has been supported by the Young 1000 Global Talent Recruitment Program of the Ministry of Education of China, the National Natural Science Foundation of China (grants no. 61502326, 41550110223, 11661131002), the Jiangsu Government (grant no. BK20150343), and the Ministry of Finance of China (grant no. SX21400213).

Resistive-switching memory (RRAM) based on metal oxide is currently considered as a possible candidate for future nonvolatile storage and storage-class memory. To explore possible applications of RRAM, the switching variability and the cycling endurance are key issues that must be carefully understood. To this purpose, we studied the switching variability and the endurance in pulsed regime for HfO x -based RRAM. We found that the resistance window, the set/reset variability, and the endurance are all controlled by the maximum voltage $V_{\rm stop}$ , which is applied during the negative-reset operation. We demonstrate that the endurance failure is triggered by a negative-set event, where the resistance suddenly decreases during the reset. Cycling endurance is studied as a function of time, compliance current and $V_{\rm stop}$ , allowing to develop an Arrhenius-law model, which is capable of predicting device lifetime under various conditions.

Scalable, low-power random number generator (RNG) blocks are essential for encryption in today's communication systems. To allow for true RNG, a system must display an inherently-random physical phenomenon, such as the timing of individual fluctuations in random telegraph noise or the random trapping/detrapping phenomena in dielectrics. In this work, a true RNG based on set variability in a resistive switching memory (RRAM) is demonstrated. The RNG relies on a single RRAM device, which is repeatedly programmed at a constant voltage close to the nominal set voltage. Due to the statistical variability of the set voltage, set transition takes place only in 50% of the applied pulses, thus resulting in a bimodal distribution of resistance. The bimodal distribution of analog resistance is finally converted into a 0/1 distribution of output voltage values through digital regeneration with a CMOS inverter.

To extend the scaling of digital integrated circuits, beyond-CMOS approaches based on advanced materials and novel switching concepts are strongly needed. Among these approaches, the resistive switching random access memory (RRAM) allows for fast and nonvolatile switching at scalable power consumption. This work presents functionally complete logic gates based on RRAM technology. Logic computation is obtained through conditional switching in RRAM circuits with serially connected switches. AND, implication, NOT, and bit transfer operations are demonstrated, each using a single clock pulse, while other functions (e.g., OR and XOR) are achieved in multiple steps. The results support RRAM logic for normally-off digital circuits with extremely high density.

Phase change memory (PCM) operation relies on a combination of electrical, thermal, and structural effects at the nanoscale [1, 2, 3, 4, 5]. Under an externally applied electric field, electrical current flows across the device and causes power dissipation and a consequent increase of local temperature, thus inducing crystallization or melting/amorphization, depending on temperature (hence on voltage and current). The corresponding change of the device resistance can then be sensed by application of a relatively low voltage. Electrical characteristics of the crystalline and amorphous phases thus play a fundamental role in the programming and read behavior of the PCM device. The electrical current-voltage characteristics of the PCM device, for instance, control the read current margin, the programming current, and the energy consumption during memory array operation. To design the driving circuits for generating the voltage pulses for memory program and read, or for selecting the correct select device to allow selection/unselection of memory bits within a cross-point array, the device characteristics are an essential piece of information. The same applies to sensing circuits aimed at reading the memory state. Finally, the dependence of voltage and currents on the device geometry (e.g., thickness of the active layer, diameter of the bottom electrode) plays a leading role in determining the scaling behavior of the PCM device for various technology nodes. Optimization of PCM device should include a careful consideration of the electrical behavior, in combination to structural properties (melting and crystallization point, activation energy of crystallization, etc.) and thermal characteristics (thermal conductivity, thermal boundary resistances, etc.).

Brain-inspired computation can revolutionize information technology by introducing machines capable of recognizing patterns (images, speech, video) and interacting with the external world in a cognitive, humanlike way. Achieving this goal requires first to gain a detailed understanding of the brain operation, and second to identify a scalable microelectronic technology capable of reproducing some of the inherent functions of the human brain, such as the high synaptic connectivity (~104) and the peculiar time-dependent synaptic plasticity. Here we demonstrate unsupervised learning and tracking in a spiking neural network with memristive synapses, where synaptic weights are updated via brain-inspired spike timing dependent plasticity (STDP). The synaptic conductance is updated by the local time-dependent superposition of pre- and post-synaptic spikes within a hybrid one-transistor/one-resistor (1T1R) memristive synapse. Only 2 synaptic states, namely the low resistance state (LRS) and the high resistance state (HRS), are sufficient to learn and recognize patterns. Unsupervised learning of a static pattern and tracking of a dynamic pattern of up to 4 × 4 pixels are demonstrated, paving the way for intelligent hardware technology with up-scaled memristive neural networks.

Brain-inspired computing is currently gaining momentum as a viable technology for artificial intelligence enabling recognition, language processing and online unsupervised learning. Brain-inspired circuit design is currently hindered by 2 fundamental limits: (i) understanding the event-driven spike processing in the human brain, and (ii) developing predictive models to design and optimize cognitive circuits. Here we present a comprehensive model for spiking neural networks based on spike-timing dependent plasticity (STDP) in resistive switching memory (RRAM) synapses. Both a Monte Carlo (MC) model and an analytical model are presented to describe experimental data from a state-of-the-art neuromorphic hardware. The model can predict the learning efficiency and time as a function of the input noise and pattern size, thus paving the way for model-based design of cognitive brain-like circuits.

Resistive switching memory based on electrochemical reaction are receiving a great interest as a future technology for nonvolatile storage class memories with fast programming and low power operation. To achieve scalable and reliable electrochemical memories, the switching and stability mechanisms must be carefully understood. This work shows that the switching characteristics of electrochemical memory devices display a strong asymmetric behavior, which is attributed to the mechanical stress around the conductive filament (CF) in the set state. CF instability after pulsed set is also evidenced and explained in terms of the compressive stress. Stress relaxation is shown to significantly stabilize ECM, thus providing new guidelines to improve memory stability at low set/reset power.

A key concern for resistive-switching random access memory (RRAM) is the read noise, due to the structural, chemical, and electrical modifications taking place at the localized current path, or conductive filament (CF). Read noise typically appears as a random telegraph noise (RTN), where the current randomly fluctuates between ON and OFF levels. This paper addresses RTN in RRAM, providing physical interpretations and models for the dependence on the programming and read conditions. First, we explain the RTN dependence on the compliance current during set transition in terms of the size-dependent depletion of carriers within the CF. Then, we discuss the bias dependence of the RTN switching times and amplitude, which can be explained by Joule heating and Poole-Frenkel barrier modifications arising from the electrostatics of the RTN fluctuating center.

Resistive switching memory (RRAM) relies on the voltage-driven formation/disruption of a conductive filament (CF) across a thin insulating layer. Due to the 1-D structure of the CF and discrete nature of defects, the set and reset states of the memory device generally display statistical variability from cycle to cycle. For projecting cell downscaling and designing improved programming operations, the variability as a function of the operation parameters, such as the maximum current in the set process and maximum voltage in the reset process, need to be evaluated and understood. This paper addresses set/reset variability, presenting statistical data for HfOx-based RRAM and introducing a physics-based Monte Carlo model for switching statistics. The model can predict the distribution of the set state as a function of the compliance (maximum) current during set and distribution of the reset state as a function of the stop (maximum) voltage during reset. Numerical modeling results are finally presented to provide additional insight into discrete fluctuation events.

To satisfy the growing market demand for embedded nonvolatile memory, alternative solutions to Flash technology are currently under investigation. Among these, phase change memory (PCM) is attracting strong interest due to the low cost of integration with the CMOS front-end and good scalability. Embedded PCM, however, must feature high reliability during both packaging and functional stages. This paper studies reliability of PCM based on Ge-rich GeSbTe, providing evidence for resistance drift and decay in both the reset and set states. Set-state instability is attributed to grain-boundary relaxation and grain growth. A unified model is presented, capable of predicting the reliability of set/reset states at elevated temperature.

The programming speed in a phase change memory (PCM) relies on the kinetics of crystallization in the pulsed regime. To predict the programming speed and retention of a PCM, a careful understanding and modeling of crystallization in the phase change material is essential. In this paper, we study crystallization kinetics directly in PCM devices. From thermal annealing and pulsed-set experiments, we extract the temperature dependence of the crystallization in a wide temperature range between 170°C and the melting point (about 620°C). Our results indicate two markedly different activation energies below/above 300°C, thus providing evidence for a non-Arrhenius crystallization kinetics in PCM.

Resistive switching memory (RRAM) devices are receiving considerable interest as future-generation high-density storage technology or possible enablers of storage class memory. For these applications, there is a strong push toward scaling, in terms of low current operation, low power consumption and small device area. To assess the scaling potential of RRAM, however, the physical mechanisms for switching and reliability issues, such as noise, must be understood in deep detail. This work reviews the current understanding of RRAM switching in terms of ion diffusion and migration mechanisms. The model is used to inspire new RRAM operation schemes, such as complementary switching (CS) which may allow self-select memory crossbar and novel multilevel storage approaches. The scaling dependence of random telegraph noise (RTN) is finally discussed based on numerical simulations of drift-diffusion transport and Poisson equation within the conductive filament.

Resistive-switching random access memory (RRAM) devices utilizing a crossbar architecture represent a promising alternative for Flash replacement in high-density data storage applications. However, RRAM crossbar arrays require the adoption of diodelike select devices with high on-off -current ratio and with sufficient endurance. To avoid the use of select devices, one should develop passive arrays where the nonlinear characteristic of the RRAM device itself provides self-selection during read and write. This paper discusses the complementary switching (CS) in hafnium oxide RRAM, where the logic bit can be encoded in two high-resistance levels, thus being immune from leakage currents and related sneak-through effects in the crossbar array. The CS physical mechanism is described through simulation results by an ion-migration model for bipolar switching. Results from pulsed-regime characterization are shown, demonstrating that CS can be operated at least in the 10-ns time scale. The minimization of the reset current is finally discussed.