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This paper reports investigation of failure mechanisms of GaN-on-Si power device under electrostatic discharge (ESD) stress using on-wafer transmission-line pulse (TLP) testing. Hot-hole injections under the gate and filament formation in the buffer layer are examined by monitoring the threshold voltage (Vth) and on-resistance (Ron) subjected to a floating gate or an off-state gate voltage. Distinct and continued degradation has been observed after the ESD stress is removed indicating a slow de-trapping process due to deep-level buffer traps. Finally, 2D device simulation is used to probe the physical insight into failure mechanisms.

Постановка задачи: современные тенденции в развитии радиоэлектронной аппаратуры (РЭА) заставляют проектировщиков уделять особое внимание электромагнитной совместимости (ЭМС). Это связано с повышением быстродействия и уменьшением рабочих напряжений и геометрических размеров элементов РЭА. Все это существенно снижает стойкость РЭА к перенапряжениям. Одной из причин таких перенапряжений является электростатический разряд (ЭСР), который может приводить к частичному или полному отказу РЭА и прерыванию ее функционирования. Опасность воздействия ЭСР на РЭА усугубляется тем, что традиционные устройства защиты имеют такие недостатки, как малые быстродействие и мощность. Кроме того, у традиционных устройств защиты ограниченный ресурс срабатываний, а также, из-за полупроводниковых компонентов в их составе, они в большой степени подвержены влиянию радиации. Это неприемлемо, например, для космической отрасли, из-за необходимости повышения срока активного существования космических аппаратов до 15 лет. В этой связи, необходим поиск новых подходов к защите РЭА, лишенных таких недостатков. Цель работы: показать возможность ослабления влияния электростатического разряда витком меандровой линии (МЛ) с лицевой связью. Используемые методы: использован подход, включающий анализ, структурно-параметрическую оптимизацию эвристическим поиском, а также вычислительный (с применением разных подходов на основе разных численных методов) и натурный эксперименты. Новизна: новизна заключается в использовании искажений в МЛ задержки впервые с целью ослабления влияния ЭСР. Впервые для этого использованы наличие перекрестной наводки и различие скоростей распространения мод в МЛ с лицевой связью. Результат: выполнен детальный анализ влияния геометрических параметров МЛ с лицевой связью на форму и амплитуду напряжения на ее выходе, при воздействии на ее входе источника тока, имитирующего ЭСР. Выявлены и продемонстрированы закономерности влияния отдельно каждого параметра МЛ с лицевой связью на форму напряжения ЭСР на ее выходе. По результатам анализа сформулированы условия, выполнение которых позволяет разложение пикового выброса ЭСР в МЛ с лицевой связью. Выполнена оптимизация параметров поперечного сечения исследуемой МЛ по критерию разложения ЭСР и минимизации его амплитуды с учетом технологических возможностей типового производства печатных плат. Полученные геометрические параметры обеспечили ослабление ЭСР в МЛ 1,61 раза. Согласно стандарту IPC-2221A, постоянный рабочий ток МЛ с полученными оптимальными параметрами может достигать 2,31 А, а напряжение – до 1,1 кВ. В ходе натурных испытаний продемонстрировано уменьшение амплитуды напряжения ЭСР после его прохождения по МЛ за счет разложения его пикового выброса. Выполнено сравнение полученных различными подходами результатов. Ослабление амплитуды напряжения ЭСР во всех использованных подходах составило не менее 1,6 раза: квазистатическом – 1,61 раза; электродинамическом – 1,66 раза; на основе измеренных S-параметров – 1,73 раза; натурном эксперименте – 1,67 раза. Практическая значимость: представленное решение может использоваться в критичной радиоэлектронной аппаратуре для защиты от ЭСР и его вторичных эффектов., Problem statement: Modern trends in the development of radio-electronic equipment (REE) require designers to pay special attention to electromagnetic compatibility (EMC). This is explained by an increase in speed and a decrease in operating voltages and geometric dimensions of REE elements. These changes significantly reduce the REE immunity to overvoltage. One of the reasons for such overvoltage is electrostatic discharge (ESD), which can lead to partial or complete REE failure and interruption of its operation. The danger of ESD impact on REE is exacerbated by the fact that traditional protection devices have disadvantages, such as low speed and power. Additionally, traditional protection devices have limited triggering resource, and since they have semiconductor components in their composition, they are largely susceptible to radiation. This is unacceptable, particularly in the space industry where it is necessary to increase the active lifespan of spacecraft to up to 15 years. Therefore, there is a need to develop new approaches to protecting REE that are free of these drawbacks. Purpose: The purpose of this work is to demonstrate the possibility of reducing the ESD impact by a meander line (ML) with broad-side coupling. Methods: The proposed approach involves analysis, structural-parametric optimization using heuristic search, as well as computational (using different approaches based on various numerical methods) and full-scale experiments. Novelty: The novelty lies in the use of ML distortions to reduce the ESD impact. For the first time, this reduction is achieved by utilizing the presence of crosstalk and the difference in mode propagation speeds in an ML with broad-side coupling. Results: The changes in geometric parameters of the ML were analyzed in detail, as well as their effect on the ESD waveform and amplitude at the ML output. The study revealed the regularities of the influence of each individual parameter of the ML on the ESD voltage waveform. Based on the analysis, conditions were formulated that allow the decomposition of the ESD peak surge in the ML. The cross-section parameters of the ML were optimized according to the criterion of ESD decomposition and minimization of its amplitude, while considering the technological capabilities of typical production of printed circuit boards. The obtained geometric parameters provided ESD attenuation in the line by 1.61 times. According to the IPC-2221A standard, the ML with the obtained optimal parameters can operate with a constant current of up to 2.31 A and a voltage of up to 1.1 kV. Full-scale tests were carried out, demonstrating a decrease in the ESD voltage amplitude after its propagation along the ML occurred due to the decomposition of its peak surge. The results obtained by different approaches were compared. The attenuation of the ESD voltage amplitude in all approaches used was at least 1.6 times: quasi-static – 1.61 times; electrodynamic – 1.66 times; based on the measured S-parameters – 1.73 times, full-scale experiment 1.67 times. Practical relevance: The proposed solution can be used in critical radio-electronic equipment to protect against ESD and its secondary effects.

Рассмотрены основные подходы проверки функциональности электронных средств при воздействии электростатического разряда, а также представлены основные этапы разработки автоматизированного тестера устойчивости электронных средств к электростатическому разряду. Электростатический разряд является одним из основных факторов, способствующих снижению надежности и производительности электронных устройств. Предложен подход к повышению качества разработки электронных изделий на основе автоматизированного устройства для тестирования электронных средств на устойчивость к электростатическим разрядам. Представлена концептуальная структура программно-аппаратного комплекса для оценки влияния электростатического разряда на электронные средства. В конструкции испытательного генератора предусмотрены защитные механизмы, предотвращающие создание непреднамеренных излучаемых или кондуктивных электромагнитных помех импульсного или непрерывного характера для исключения паразитных эффектов, способных оказать влияние на испытуемое или вспомогательное оборудование. Целью исследования, в рамках которого происходила разработка тестирующего устройства, является повышение надежности функционирования электронных средств и приборов при воздействии на них электростатических разрядов. Благодаря предлагаемому подходу становится возможным обеспечить эффективность тестирования конструкций электронных средств на устойчивость к электростатическому разряду на основе комплексных методов оптимального проектирования с учетом обеспечения требований международных стандартов The article discusses the main approaches to checking the functionality of electronic devices when exposed to electrostatic discharge. Electrostatic discharge (ESD) is a major contributor to the reliability and performance of electronic devices. This paper proposes an approach to improving the quality of development of electronic products based on an automated device for testing electronic devices for resistance to electrostatic discharges. We present the conceptual structure of a software and hardware complex for assessing the effect of electrostatic discharge on electronic means. The test generator is designed with protective mechanisms to prevent the creation of unintentional radiated or conducted electromagnetic interference of a pulsed or continuous nature to eliminate parasitic effects that could affect the tested or auxiliary equipment. The purpose of the study, within the framework of which the development of the testing device took place, is to increase the reliability of the functioning of electronic devices and devices when exposed to electrostatic discharges. Thanks to the proposed approach, it becomes possible to ensure the effectiveness of testing the structures of electronic devices for resistance to electrostatic discharge on the basis of complex methods of optimal design, taking into account the requirements of international standards

Numerous missions are being proposed which involve multiple spacecraft operating in close proximity in harsh charging environments. In such missions, the ability to sense the electrostatic potentia...

Electrostatic discharge (ESD) failures in high-speed integrated circuits (ICs) cause critical reliability problems in electronic devices. Transient voltage suppressor (TVS) diodes are installed on high-speed I/O traces to improve system-level ESD protection. To protect the circuit, the majority of ESD current must flow into the external TVS diode rather than into the IC, but due to turn- on behavior, the TVS diode may not snap back when needed and the IC's internal protection may take most of the current. These race conditions between the internal and external ESD protection circuits were investigated for a universal serial bus(USB) interface board. The transient turn- on behavior of the on-chip and off-chip protection circuitry was characterized by measurements and by system efficient ESD design (SEED) simulations. The effect of transmission line pulses (TLP pulses) and power supply voltages of different sizes on the response of the protection circuitry were monitored and compared with SEED simulations. SEED models showed good agreement with measurements and were used to study the impact of passive components added to a high-speed trace or within the IC package on the ESD protection response. Results show the importance of properly accounting for the parasitic resistance and inductance between the on-chip diode and off-chip TVS diode, as well as the length of the transmission line when choosing the external TVS device. Results also show that testing must be performed using mid-level events to account for possible problems due to race conditions.

To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static I–V model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators.

This letter focused on the additive effect of horizontal Schottky diodes on the drain side of a high-voltage p-channel laterally diffused metal–oxide–semiconductor (pLDMOS). These components were evaluated using transmission-line pulse and human body model (HBM) tests. When the parasitic Schottky area at the drain was smaller, the Schottky characteristics were less obvious; the device’s current mostly flowed through the heavily doped $\text{P}^{+}$ area, and the improvement in ${I}_{\text {t2}}$ was minor. When the parasitic Schottky area covered more than 60% of the drain side, the Schottky area accounted for the majority of current flow; therefore, the electrostatic discharge current could flow more evenly. These modified pLDMOSs can withstand higher voltages because of their parasitic Schottky diodes and higher impedance. In addition, their ${I}_{\text {t2}}$ values are superior to those of normal pLDMOSs. With the drain side of the pLDMOS completely covered by Schottky diodes, the device produced the highest ${I}_{\text {t2}}$ value of 1.659 A (130.4% higher than that of the reference sample), an HBM value of 5 kV (300% higher than the reference), and an improved holding voltage (4% greater than that of the reference).

A dual-MOS-triggered silicon-controlled rectifier (DMTSCR) has been firstly developed for high-voltage (HV) electrostatic discharge (ESD) protection. Compared to the reported SCRs with modified structures, the DMTSCR harvests a series of advantages such as a high holding voltage ( $V_{h}$ ), a strong ESD robustness, and a low $V_{t1}$ , thanks to its embedded structures including a gate-to-VDD PMOS, a gate-grounded NMOS, and a modified SCR. Thus, the DMTSCR has the largest figure of merit as high as 1.8 mA/ $\mu \text{m}^{2}$ . By further optimizing the layout and the key spacing between the embedded PMOS and NMOS of DMTSCR, $V_{h}$ increased from 8.4 to 17.4 V, the turn-on resistance remarkably decreased to $0.4~\Omega $ , and the turn-on voltage was clamped at $V_{h}$ . The optimized DMTSCR with a small chip area possesses an ESD robustness of 3000 V evaluated by the human body model. Meanwhile, the operation mechanism simulated by Sentaurus exhibited good agreements with the theoretical circuit analysis, and the simulated electrical characteristics were consistent with those measured from the experimental devices. The layout-optimized DMTSCR with good clamping ability and zero snapback voltage is a promising solution for stacking to meet various HV ESD protection requirements.

In this study, the electrostatic discharges from a metal protrusion existing inside a conical-cylindrical silo during continuous loading of polypropylene powders (PP, 3 to 4 mm) were experimentally investigated. A pilot-scale silo connected to a pneumatic powder transport facility was used while all parts were electrically grounded. The metal protrusion used in this study had a diameter of 4 cm. The silo was continuously loaded with PP powders at a mass flow rate of 0.68 kg/s to a total mass of approximately 800 kg. An image intensifier unit was used to observe the electrostatic discharges generated from the metal protrusion, and a current probe attached to an oscilloscope was used to measure the discharge amount (Q [nC]). As for the results, a multiplicity of small electrostatic discharges (brush discharges) from the protrusion was observed. The electrostatic discharge from the protrusion during PP powder loading clearly developed at the 391 s mark, when approximately 270 kg of the powder had been loaded. In addition, a difference was observed in the electrostatic discharges before and after the protrusion was embedded in the accumulated powder. That is to say, after the metal protrusion was embedded in the accumulated powder, the electrostatic discharges were stronger than when the protrusion was not embedded. As well, the Q after the immersion of the metal protrusion in the accumulated powder was several times larger than that when the protrusion was out. Strong broad bulk surface discharges clearly appeared after the protrusion was fully immersed in the powder.

On-chip electrostatic discharge (ESD) protection is becoming more challenging for integrated circuits (ICs) made in advanced technology nodes. The ESD-induced design overhead, including ESD parasitic effects and layout area, inherent to the traditional in-Silicon PN-junction-based ESD protection devices, rapidly becomes unbearable to high-performance and complex ICs. A disruptive above-Si mechanical ESD switch device, made in CMOS backend using a graphene nano-electromechanical-system (gNEMS) structure, was recently devised and demonstrated using poly-crystalline graphene films. This paper reports design, fabrication and comprehensive characterization of single-crystalline gNEMS ESD switch devices. Measurement using transmission line pulse (TLP) and very fast transmission line pulse (VFTLP) ESD testing reveals superior ESD protection capability of gNEMS devices made in single-crystalline graphene over its poly-crystalline counterparts, achieving a record-high ESD current handling capability of ${\text{I}}_{t2} {\sim }1.19 {\times }10^{10}\text{A}$ /cm2 under TLP zapping and ${\text{I}}_{t2} {\sim }6.09{\times }10^{9}\text{A}$ /cm2 under VFTLP stressing. The ESD robustness enhancement related to single-crystalline graphene material property is discussed.

The photomasks for contact-type lithography are vulnerable to electrostatic damage. In the present study, a conducting ITO material was introduced as a bridge between the chromium metal patterns to prevent electrostatic damage. The core of this research was to optimize the material and bridging structure to distribute the accumulated charges efficiently. On the other hand, when fabricating the bridging circuit, it is challengeable to deposit an ITO material without electrical disconnection due to the inevitable chromium undercut shape caused by isotropic etching during the wet etching process. A method called UV-Assisted-Partial-Strip (UAPS) was adopted in this study. UAPS induces a change in the solubility and erosion properties of resistance through irradiation with 365 nm light and optimization of the alkaline solution process. Focused ion beam-scanning electron microscopy confirmed that the conducting ITO film was deposited without electrical disconnection on the side of the chromium pattern over the entire area of the photomask. ITO thin film was optimized 20 nm-thick, 3.0 × 102 Ω/□ sheet resistance, and about 84% transmittance. The subsequent hand roller test and electrostatic discharge immunity test showed that the initiation voltage of the electrostatic melted-typed defect had been increased remarkably.

This article proposes a novel power p-GaN high-electron-mobility transistor (HEMT) with self-triggered discharging channel to improve gate-to-source electrostatic discharge (ESD) robustness. The self-triggered discharging channel consists of a small-size self-triggered p-GaN HEMT, a current-limiting resistor ${R}_{{1}}$ , and a proportional amplification resistor ${R}_{{2}}$ . At ESD events, the proposed power p-GaN HEMT will be self-triggered by the high transient ESD voltage, and hence the accumulated electrostatic charges at its gate will be released through the self-triggered discharging channel. This avoids the gate-to-source damage of the proposed device, thereby enhancing the gate-to-source ESD robustness. Compared with the conventional power p-GaN HEMT, simulation results show that the transmission line pulsing (TLP) current handling capability (over 6.5 kV human body model failure voltage) of the proposed device is improved by 1900% without compromising other device characteristics. In addition, the fabrication process of the proposed device is fully compatible with the traditional power p-GaN HEMT platform, and the increase of total active area is less than 0.5%. The proposed device with self-triggered discharging channel can be a good reference for the design of power p-GaN HEMT with high ESD robustness.

Current filament (CF)-related double-hysteresis ${I}$ – ${V}$ behavior and holding current, ${I} _{\text {HOLD}}$ , are analyzed using experiments and 3-D technology computer-aided design (TCAD) simulation in silicon-controlled rectifiers (SCR) for system-level electrostatic discharge (ESD) protection. Our 3-D TCAD methodology uses up and down quasi-dc current sweeps to reveal a memory effect in the current density distribution along the device width. ${I} _{\text {HOLD}}$ is related to the smallest possible CF where the self-sustaining SCR action takes place during down current sweep. ${I} _{\text {HOLD}}$ exhibits a nontrivial dependence on device width, depending on whether a CF is created or not. Analyzing devices of different layouts shows that ${I} _{\text {HOLD}}$ values determined from experiments and 3-D TCAD are almost layout-independent and substantially lower than those evaluated from 2-D TCAD. ${I} _{\text {HOLD}}$ calculated by 3-D TCAD in edge-terminated devices is higher than that in 3-D structures obtained from simple width-extended 2-D doping profiles. The use of latter devices, thus, simplifies the 3-D TCAD ${I}$ – ${V}$ analysis and provides a safe margin for ${I} _{\text {HOLD}}$ prediction. The work is relevant for designing the latch-up immunity of ESD protection devices, and it also shows that conventional 2-D TCAD can provide unwanted overestimation of ${I} _{\text {HOLD}}$ .

A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure.

In this paper, the electrostatic discharge of solar arrays in spacecraft energy systems is taken as the research object. The influence and internal mechanism of external electromagnetic radiation on electrostatic discharge is studied. Meanwhile, the charging and discharging test platform of spacecraft solar arrays under a strong field is first established. Then, the influence of irradiation field strength, electron beam energy and beam density on electrostatic discharge of solar arrays is analyzed and summarized. The results show that during the irradiation process of solar arrays using a high-energy electron beam under vacuum conditions, the higher the electron beam energy and the beam current density, the higher the discharge frequency of the solar array. When the intensity of the external electromagnetic radiation field increases, the discharge frequency also increases. Under the action of external radiation field with the same peak field strength, the larger the gap, the smaller the discharge frequency. With the increase in the field strength, the potential difference of each part of the solar array becomes smaller, and the peak of the discharge current decreases. The research results can provide technical reference for electrostatic protection of spacecraft solar arrays.

This letter presents a fully integrated wideband, ultralow average noise figure (NF), low power consumption, compact, and electrostatic discharge protected 6.7–15.3-GHz low-noise amplifier (LNA). A peak-gain distribution technique with a large transistor and two-stage broadband noise matching technique are proposed. For verification, a two-stage common source LNA is implemented in a 65-nm bulk complementary metal–oxide–semiconductor technology. The fabricated LNA achieved an average NF of 2.08 dB and an average gain of 19.1 dB with in-band gain ripple of ±0.75 dB in the frequency range of 7.6–14.7 GHz. It has a 3-dB fractional bandwidth of 78% and the third-order input intercept point is −9.0 dBm at 10 GHz. It consumes a 16 mA at a 0.8-V supply and has an area of 0.144 mm2.

System efficient electrostatic discharge (ESD) design is an effective method for simulating the ESD behaviors of a system. Based on this simulation method, this article mainly investigates the transient behaviors of a system-level ESD protection circuit with and without a 2.5 V power supply. During power- on state, latch-up levels of a feedback power clamp protected by off-chip elements are predicted and mainly analyzed under machine model stress. During power- off state, the physical failure of a hybrid-triggered power clamp under surge stress is investigated. In addition to the utilization of transmission line pulsing (TLP) I-V curves, transient TLP waveforms are also used for building the component models in the system-level ESD protection circuit. Moreover, the relevant measurements for the power- on state and power- off state are included in this article for verifying the simulation results. For ESD designers, this article provides a complete modeling and analysis process of co-design protection circuit to investigate the electrical behaviors.

Circuits design that meets various IEC electrical overstress (EOS) standards is still a challenge, for that different kinds of EOS are at different frequency bands. In this paper, a physics-based transient simulation and modeling method is proposed, which can simulate wide-frequency EOS including electrostatic discharge (ESD) and AC characteristics. In this method, the physical model is used to characterize the nonlinear semiconductor devices in the finite-difference time-domain (FDTD)-SPICE co-simulation. Moreover, the modeling and physical parameters extraction method of the ESD protect devices, the transient voltage suppressor diode, is demonstrated. Taking an EOS protection circuit for example, it is modeled and simulated by the proposed method. Moreover, the circuit is also simulated by the widely-used System-Efficient ESD Design (SEED) method, in which the TVS diode is modeled based on 100 ns Transmission Line Pulse (TLP) measurements. The experiments show that both this method and SEED method can characterize the IEC system-level ESD behaviors well. However, the error of the SEED is about 219.2% at 10 MHz AC characteristics, but the maximum error of the proposed method is only 7.8%. Hence, compared with the widely-used SEED method, this method is more accurate when characterizing the EOS event during AC operation and switching.

An electrostatic discharge (ESD)-protected one-time-programmable (OTP) memory front-end circuit, for high-voltage (HV) applications, designed and manufactured in silicon-on-insulator (SOI) technology, is presented. The SOI technology meets HV functional-isolation and level-shifting requirements but is not suitable for advanced analog circuits. The presented OTP memory is discussed as an introduction to digital programmability in the considered technology. The memory element consists of an antifuse type structure and is implemented using a 5-V nMOS with $\text {L}={1}\,\, \mathbf {\mu \text {m}}$ and $\text {W}={1.2}\,\, \mathbf {\mu \text {m}}$ . The cell memory allows for significant area and power savings in the adopted HV technology. Conditions for this require that an efficient ESD protection will guarantee safe operation, even in the presence of a small and fragile on-chip element whose undesired burning would compromise the programming mechanism, and consequently the reliability, of the circuit. Details about the circuit design implementation of the front-end circuit for both read and write circuits and ESD protection are described with experimental results validating the proposed implementation.

In order to guide the design of effective shielding layer to reduce the risk of dielectric electrostatic discharge in high-power and high-voltage spacecraft under GEO environment, it is necessary to explore the influence of grounding method and the joint action of high working voltage and deposited charge on the deep dielectric charging characteristics. In this article, based on the FLUMIC3 model, the electron flux of GEO environment is calculated, and an assessment method for the dielectric electrostatic discharge risk is established by combining Geant4 and a finite element method. Then, this method is used to calculate and analyze the influence of the grounding method and operating voltage on the electric field distribution of the polyimide under different shielding thicknesses. The results show that increasing the shielding thickness and grounding area can effectively reduce the polyimide internal electric field, and the aluminum shielding safety threshold required under the worst conditions is 2.920 mm; the influence of the working voltage mainly depends on the application method and the voltage value. During the working voltage increase from 100 to 5000 V, assume the working voltage ( $V_{s}$ ) is applied to one side of the polyimide sample, when the other side is suspended, namely, not grounded (B, $V_{s}$ -S; C, S- $V_{s}$ ), the maximum electric field depends on the deposited charge and it does not change with the working voltage; when the other side of the sample is grounded (A, $V_{s}$ -G; D, G- $V_{s}$ ), the maximum electric field and its distribution are determined by the working voltage and the deposited charge. Within this voltage range, the safety threshold of the aluminum shielding layer needs to reach 4–5 mm. In summary, under high working voltage, the grounding area of the sample can be increased, and the appropriate working conditions can be selected to determine the optimal shielding thickness that can suppress dielectric electrostatic discharge.

The purpose of this research is to investigate the design of an electrostatic discharge protection device made of single-layer graphene nanoribbons. The device is meant to trigger electrostatic discharge at a target voltage of 1.5V. Other design requirements include the minimization of parasitic capacitance, electrical response time and mechanical response time. The device is designed to discharge static electricity by being pulled to ground through electrostatic forces, then making contact with ground before returning to its original position. Previous designs experienced repeatability issues due to a lack of securing the ribbon and mechanical failure due to high stresses at the boundary conditions. New designs are presented and optimized to maintain a high effective spring constant for the device while reducing stress during electrostatic pull-in. A single-degree-of-freedom model is used in conjunction with the Bernoulli-Euler beam equations and Castigliano’s method to guide the design process. Multi-degree-of-freedom and finite element models are used to validate the predicted pull-in behavior of the new devices and to explore how stresses and reaction forces might affect the reliability. A residual PMMA layer that results from the fabrication process is also incorporated into the finite element model. Molecular dynamics simulations are performed to further explore the behavior of graphene nanoribbons under electrostatic pull-in and to check the accuracy of the finite element approach. The fabrication process is explained and experimental results for the new devices are reported.