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The recording performance of a new magnetic tape based on perpendicularly oriented barium ferrite particles was investigated using a 90-nm-wide giant-magnetoresistive reader and a prototype enhanced-field write head. A linear density of 600 kb/in with a postdetection byte-error rate < 3\times 10^-2 was demonstrated based on measured recording data and a software read channel that used a noise-predictive maximum likelihood detection scheme. Using a new iterative decoding architecture, a user bit-error rate of < 1\times 10^-20 can be achieved at this operating point. To facilitate aggressive scaling of the track density, we made several advances in the area of the track-following servo. First, we developed an experimental low-noise tape transport. Second, we implemented an optimized servo channel that together with an experimental timing-based servo pattern enables the generation of position estimates with nanoscale resolution at a high update rate. Third, we developed a field-programmable gate array-based prototyping platform in which we have implemented the servo channel and an H\infty -based track-following controller, enabling real-time closed-loop track-following experiments. Combining these technologies, we achieved a position-error signal (PES) with a standard deviation of 10.3 nm. This magnitude of PES in combination with a 90-nm-wide reader allows the writing and reading of 177-nm-wide tracks at 600 kb/in, for an equivalent areal density of 85.9 Gb/in ^2 . This paper clearly demonstrates the continued scaling potential of tape technologies based on low-cost particulate media. [ABSTRACT FROM AUTHOR]

The recording performance of a new magnetic tape based on ultra-fine, perpendicularly-oriented BaFe particles was investigated. Specifically, using a low lateral tape motion demonstration platform, a new servo pattern written on the advanced perpendicularly oriented BaFe medium, a new low friction head technology, a novel synchronous servo channel design, and advanced servo control concepts, we were able to demonstrate a record closed-loop track-follow performance with a 23.4 nm standard deviation of position-error signal, roughly one order of magnitude better than in current tape products. In addition, using read back waveforms captured on the same advanced perpendicularly oriented BaFe medium with a 0.2-\mu\m-wide data reader, we demonstrated write/read performance at 518 kbpi using advanced noise-predictive maximum likelihood (NPML) detection schemes. Combining these two results, we estimate that the new medium can support an areal recording density of up to 29.5 \Gb/in^2. This result demonstrates the scalability and extendability of tape technology using low-cost particulate media. [ABSTRACT FROM AUTHOR]

We present an integrated analog front-end (AFE) for the read-channel of a parallel scanning-probe storage device. The read/write element is based on an array of microfabricated silicon cantilevers equipped with heating elements to form nanometer-sized indentations in a polymer surface using integral atomic-force microscope (AFM) tips. An accurate cantilever model based on the combination of a thermal/electrical lumped-element model and a behavioral model of the electrostatic/mechanical part are introduced. The behavioral model of the electrostatic/mechanical part is automatically generated from a full finite-element model (FEM). The model is completely implemented in Verilog-A and was used to co-develop the integrated analog front-end circuitry together with the read/write cantilever. The cantilever model and the analog front-end were simulated together and the results were experimentally verified. The approach chosen is well suited for system-level simulation and verification/extraction in a design environment based on standard EDA tools. [ABSTRACT FROM AUTHOR]

We present a reverse concatenation (RC) architecture using Reed-Solomon (RS) error-correction codes (ECCs). The scheme employs very-high-rate pre-RS modulation codes followed by RS parity symbol insertion. The very-high-rate modulation codes in the RC scheme, which facilitate timing recovery and automatic gain control and reduce the detector path memory, are of the same type as the modulation codes that have been used in generalized partial-response maximum-likelihood (PRML) detection systems. [ABSTRACT FROM AUTHOR]

Various log-likelihood-ratio-based belief-propagation (LLR-BP) decoding algorithms and their reduced-complexity derivatives for low-density parity-check (LDPC) codes are presented. Numerically accurate representations of the check-node update computation used in LLR-BP decoding are described. Furthermore, approximate representations of the decoding computations are shown to achieve a reduction in complexity by simplifying the check-node update, or symbol-node update, or both. In particular, two main approaches for simplified check-node updates are presented that are based on the so-called min-sum approximation coupled with either a normalization term or an additive offset term. Density evolution is used to analyze the performance of these decoding algorithms, to determine the optimum values of the key parameters, and to evaluate finite quantization effects. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of the BP algorithm. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate scheme from performance, latency, computational-complexity, and memory-requirement perspectives. [ABSTRACT FROM AUTHOR]

We propose a general method for constructing Tanner graphs having a large girth by establishing edges or connections between symbol and check nodes in an edge-by-edge manner, called progressive edge-growth (PEG) algorithm. Lower bounds on the girth of PEG Tanner graphs and on the minimum distance of the resulting low-density parity-check (LDPC) codes are derived in terms of parameters of the graphs. Simple variations of the PEG algorithm can also be applied to generate linear-time encodeable LDPC codes. Regular and irregular LDPC codes using PEG Tanner graphs and allowing symbol nodes to take values over GF(q) (q > 2) are investigated. Simulation results show that the PEG algorithm is a powerful algorithm to generate good short-block-length LDPC codes. [ABSTRACT FROM AUTHOR]

Digital signal processing and coding are increasingly being recognized as a cost-efficient approach in achieving substantial areal density gains while preserving the high reliability of disk drives, although historically advances in head and media technologies have been the main driving force behind areal density growth. The recent advances in capacity-approaching codes hold the promise to push the areal density to the ultimate limit. In this article the various configurations regarding the interplay between soft detection and soft decoding through an iterative process, as it applies to the magnetic recording channel, are presented. In particular, the state of the art in turbo and turbo-like coding, including LDPC coding, is reviewed and the serial con-catenation of these coding schemes with inner generalized PR channels in a turbo equalization structure is described. Finally, an attempt is made to assess the performance and limitations of these AWGN channel-capacity-approaching codes when applied to the magnetic recording channel. [ABSTRACT FROM AUTHOR]

Presents a study that examined equalization and noise prediction followed by sequence detection and postprocessing of double-layer perpendicular magnetic recording channels that are corrupted by electronics and transition noise. Description of the recording channel model; Analysis of the equalization targets and noise whitening for perpendicular recording from a minimum mean-square error viewpoint; Characterization of the capacity of recording channels.

Intimal thickening in the coronary artery bypass graft (CABG) distal anastomosis has been implicated as the major cause of restenosis and long-term graft failure. Several studies point to the interplay between nonuniform hemodynamics including disturbed flows and recirculation zones, wall shear stress, and long particle residence time as possible etiologies. The hemodynamic features of two anatomic models of saphenous-vein CABGs were studied and compared. One simulated an anastomosis with both diameter and compliance mismatch and a curvature at the connection, analogous to the geometry observed in a conventional cardiothoracic procedure. The other, simulated an anastomosis with a flow stabilizing anastomotic implant connector which improves current cardiothoracic procedures by eliminating the distal vein bulging and curvature. Physiologic flow conditions were imposed on both models and qualitative analysis of the flow was performed with dye injection and a digital camera. Quantitative analysis was performed with laser Doppler velocimetry. Results showed that the presence of the bulge at the veno-arterial junction, contributed to the formation of accentuated secondary structures (helices), which progress into the flow divider and significantly affect radial velocity components at the host vessel up to four diameters downstream of the junction. The model with the implant, achieved more hemodynamically efficient conditions on the host vessel with higher mean and maximum axial velocities and lower radial velocities than the conventional model. The presence of the sinus may also affect the magnitude and shape of the shear stress at locations where intimal thickening occurs. Thus, the presence of the implant creates a more streamlined environment with more primary and less secondary flow components which may then inhibit the development of intimal thickening, restenosis, and ultimate failure of the saphenous vein graft. © 2002 Biomedical Engineering Society. PAC2002: 8780Rb, 8719Rr, 8719Uv, 8763Lk, 8719Xx, 4262Be, 4780+v, 8710+e [ABSTRACT FROM AUTHOR]

Presents a study which described a filter-bank modulation technique called filtered multitone (FMT) and its application to data transmission for very high-speed digital subscriber line (VDSL) technology. Characteristics of VDSL; Discussion on the filter-bank communication system and FMT modulation; Realization of FMT modulation; Description of the frequency responses of FMT subchannels.

Introduces a series of articles on turbo-decoding algorithm.

Introduces an emerging twins constraint for maximum transition run (MTR) codes to eliminate quasi-catastrophic error propagation in sequence detectors for generalized partial response channels with spectral nulls. Description of the recording system model; Characterization of the sequences that must be eliminated; Constructions of specific MTR codes.

Discusses the multicarrier basis functions and related issues with an emphasis on filtered multitone modulation for very high-speed digital subscriber line technology. Subdivision of signal frequency; Perfect reconstruction and spectral containment; Conclusions.

The article discusses various reports published within the issue, including one on control of microelectromechanical systems (MEMS)-based scanning-probe data-storage devices and another on high-performance control of piezoelectric tube scanners.

Information theory concepts are leveraged with the goal of better understanding and improving Deep Neural Networks (DNNs). The information plane of neural networks describes the behavior during training of the mutual information at various depths between input/output and hidden-layer variables. Previous analysis revealed that most of the training epochs are spent on compressing the input, in some networks where finiteness of the mutual information can be established. However, the estimation of mutual information is nontrivial for high-dimensional continuous random variables. Therefore, the computation of the mutual information for DNNs and its visualization on the information plane mostly focused on low-complexity fully connected networks. In fact, even the existence of the compression phase in complex DNNs has been questioned and viewed as an open problem. In this paper, we present the convergence of mutual information on the information plane for a high-dimensional VGG-16 Convolutional Neural Network (CNN) by resorting to Mutual Information Neural Estimation (MINE), thus confirming and extending the results obtained with low-dimensional fully connected networks. Furthermore, we demonstrate the benefits of regularizing a network, especially for a large number of training epochs, by adopting mutual information estimates as additional terms in the loss function characteristic of the network. Experimental results show that the regularization stabilizes the test accuracy and significantly reduces its variance. [ABSTRACT FROM AUTHOR]

Carbon-based electronics is a promising alternative to traditional silicon-based electronics as it could enable faster, smaller and cheaper transistors, interconnects and memory devices. However, the development of carbon-based memory devices has been hampered either by the complex fabrication methods of crystalline carbon allotropes or by poor performance. Here we present an oxygenated amorphous carbon (a-COx) produced by physical vapour deposition that has several properties in common with graphite oxide. Moreover, its simple fabrication method ensures excellent reproducibility and tuning of its properties. Memory devices based on a-COx exhibit outstanding non-volatile resistive memory performance, such as switching times on the order of 10 ns and cycling endurance in excess of 104 times. A detailed investigation of the pristine, SET and RESET states indicates a switching mechanism based on the electrochemical redox reaction of carbon. These results suggest that a-COx could play a key role in non-volatile memory technology and carbon-based electronics. [ABSTRACT FROM AUTHOR]

Spiking neural networks (SNNs) are mimicking computationally powerful biologically inspired models in which neurons communicate through sequences of spikes, regarded here as sparse binary sequences of zeros and ones. In neuroscience it is conjectured that time encoding, where the information is carried by the temporal position of spikes, is playing a crucial role at least in some parts of the brain where estimation of the spiking rate with a large latency cannot take place. Motivated by the efficiency of temporal coding, compared with the widely used rate coding, the goal of this paper is to develop and train an energy-efficient time-coded deep spiking neural network system. To ensure that the similarity among input stimuli is translated into a correlation of the spike sequences, we introduce correlative temporal encoding and extended correlative temporal encoding techniques to map analog input information into input spike patterns. Importantly, we propose an implementation where all multiplications in the system are replaced with at most a few additions. As a more efficient alternative to both rate-coded SNNs and artificial neural networks, such system represents a preferable solution for the implementation of neuromorphic hardware. We consider data classification tasks where input spike patterns are presented to a feed-forward architecture with leaky-integrate-and-fire neurons. The SNN is trained by backpropagation through time with the objective to match sequences of output spikes with those of specifically designed target spike patterns, each corresponding to exactly one class. During inference the target spike pattern with the smallest van Rossum distance from the output spike pattern determines the class. Extensive simulations indicate that the proposed system achieves a classification accuracy at par with that of state-of-the-art machine learning models. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) is an emerging non-volatile memory technology that is based on the reversible and rapid phase transition between the amorphous and crystalline phases of certain phase-change materials. The ability to alter the conductance levels in a controllable way makes PCM devices particularly well-suited for synaptic realizations in neuromorphic computing. A key attribute that enables this application is the progressive crystallization of the phase-change material and subsequent increase in device conductance by the successive application of appropriate electrical pulses. There is significant inter- and intra-device randomness associated with this cumulative conductance evolution, and it is essential to develop a statistical model to capture this. PCM also exhibits a temporal evolution of the conductance values (drift), which could also influence applications in neuromorphic computing. In this paper, we have developed a statistical model that describes both the cumulative conductance evolution and conductance drift. This model is based on extensive characterization work on 10 000 memory devices. Finally, the model is used to simulate the supervised training of both spiking and non-spiking artificial neuronal networks. [ABSTRACT FROM AUTHOR]

There is a significant need to build efficient non-von Neumann computing systems for highly data-centric artificial intelligence related applications. Brain-inspired computing is one such approach that shows significant promise. Memory is expected to play a key role in this form of computing and, in particular, phase-change memory (PCM), arguably the most advanced emerging non-volatile memory technology. Given a lack of comprehensive understanding of the working principles of the brain, brain-inspired computing is likely to be realized in multiple levels of inspiration. In the first level of inspiration, the idea would be to build computing units where memory and processing co-exist in some form. Computational memory is an example where the physical attributes and the state dynamics of memory devices are exploited to perform certain computational tasks in the memory itself with very high areal and energy efficiency. In a second level of brain-inspired computing using PCM devices, one could design a co-processor comprising multiple cross-bar arrays of PCM devices to accelerate the training of deep neural networks. PCM technology could also play a key role in the space of specialized computing substrates for spiking neural networks, and this can be viewed as the third level of brain-inspired computing using these devices. [ABSTRACT FROM AUTHOR]

In-memory computing is an emerging computing paradigm enabling deep-learning inference at significantly higher energy-efficiency and reduced latency. The essential idea is mapping the synaptic weights of each layer to one or more in-memory computing (IMC) cores. During inference, these cores perform the associated matrix-vector multiplications in place with O(1) time complexity, obviating the need to move the synaptic weights to additional processing units. Moreover, this architecture enables the execution of these networks in a highly pipelined fashion. However, a key challenge is designing an efficient communication fabric for the IMC cores. In this work, we present one such communication fabric based on a graph topology that is well-suited for the widely successful convolutional neural networks (CNNs). We show that this communication fabric facilitates the pipelined execution of all state-of-the-art CNNs by proving the existence of a homomorphism between the graph representations of these networks and that corresponding to the proposed communication fabric. We then present a quantitative comparison with established communication topologies and show that our proposed topology achieves the lowest bandwidth requirements per communication channel. Finally, we present one hardware implementation and show a concrete example of mapping ResNet-32 onto an IMC core array interconnected via the proposed communication fabric. [ABSTRACT FROM AUTHOR]

Spiking neural networks (SNN) are computational models inspired by the brain's ability to naturally encode and process information in the time domain. The added temporal dimension is believed to render them more computationally efficient than the conventional artificial neural networks, though their full computational capabilities are yet to be explored. Recently, in-memory computing architectures based on non-volatile memory crossbar arrays have shown great promise to implement parallel computations in artificial and spiking neural networks. In this work, we evaluate the feasibility to realize high-performance event-driven in-situ supervised learning systems using nanoscale and stochastic analog memory synapses. For the first time, the potential of analog memory synapses to generate precisely timed spikes in SNNs is experimentally demonstrated. The experiment targets applications which directly integrates spike encoded signals generated from bio-mimetic sensors with in-memory computing based learning systems to generate precisely timed control signal spikes for neuromorphic actuators. More than 170,000 phase-change memory (PCM) based synapses from our prototype chip were trained based on an event-driven learning rule, to generate spike patterns with more than 85% of the spikes within a 25 ms tolerance interval in a 1250 ms long spike pattern. We observe that the accuracy is mainly limited by the imprecision related to device programming and temporal drift of conductance values. We show that an array level scaling scheme can significantly improve the retention of the trained SNN states in the presence of conductance drift in the PCM. Combining the computational potential of supervised SNNs with the parallel compute power of in-memory computing, this work paves the way for next-generation of efficient brain-inspired systems. [ABSTRACT FROM AUTHOR]