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Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because they promise superior input characteristics. However, the output characteristics of TFETs are poorly understood, and sometimes a superlinear onset, undesirable for circuit design, is observed. We present the first analytical model to include the impact of the drain voltage on the TFET performance. The model is developed for both a pure line-tunneling TFET and a pure point-tunneling TFET. Good agreement is observed with device simulations, especially for line-tunneling TFETs. Our model highlights and explains the superlinear onset of the output characteristics, thereby enabling an improved analysis of experimental data. Increasing the source doping level and switching to a smaller bandgap material can remove the undesired onset. We confirm this finding with our experimental data. [ABSTRACT FROM AUTHOR]

Recently, a renewed interest in Zener tunneling has arisen because of its increasing impact on semiconductor device performance at nanometer dimensions. In this paper we evaluate the tunnel probability under the action of a nonuniform electric field using a two-band model and arrive at significant deviations from the commonly used Kane’s model, valid for weak uniform fields only. A threshold on the junction bias where Kane’s model for Zener tunneling breaks down is determined. Comparison with Kane’s model particularly shows that our calculation yields a higher tunnel probability for intermediate electric fields and a lower tunnel probability for high electric fields. When performing a current calculation comparing to the WKB approximation for the case of an abrupt p-n junction significant differences concerning the shape of the I-V curve are demonstrated. [ABSTRACT FROM AUTHOR]

Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data. [ABSTRACT FROM AUTHOR]

Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because of the absence of short-channel effects and of a subthreshold-slope limit. As a solution to the low on-currents of silicon-based TFETs, the incorporation of silicon-germanium at the source-channel interface has been considered. However, the understanding of the band-to-band-tunneling mechanism at heterojunctions is incomplete. We have investigated through device simulations and modeling the impact of source-material modifications on the tunnel current in n-channel nanowire TFETs. Our modeling work includes the development of a semi-analytical model, which determines the tunnel probability along the dominant tunnel path in two-dimensional TFETs. In particular, we have analyzed the impact of the bandgap, electron affinity, effective mass, dielectric constant, and density of states of both source and channel material. We show that a small-bandgap source material and a large positive electron-affinity offset at the source-channel interface boost the tunnel current of n-channel TFETs. [ABSTRACT FROM AUTHOR]

We investigated plasma treatment induced water absorption in a SiOCH low-k dielectric and the influence of the absorbed water components on the low-k dielectric reliability. By using thermal desorption spectroscopy (TDS), water absorption in SiOCH was evidenced for N2/H2 plasma treatments. Based on these TDS results, two anneal temperatures were selected to separate and quantify the respective contributions of two absorbed water components, physisorbed (α) and chemisorbed (β) water, to low-k dielectric reliability. With the physisorbed water desorbed by an anneal at 190 °C, the low-k dielectric shows reduced leakage currents and slightly improved time-dependent dielectric breakdown (TDDB) lifetimes. However, the observed failure mechanism represented by the TDDB thermal activation energy (Ea) does not change until the chemisorbed water component was desorbed by an anneal at 400 °C. The close similarity between Ea and the bond energy associated with the β water component demonstrates that the β bond is among the weakest links for the SiOCH low-k dielectric breakdown. [ABSTRACT FROM AUTHOR]

In this work, we employ the substrate hot electron injection technique as a characterization tool to examine the defect creation mechanisms in high-k HfSiON gate stacks, taking advantage of the independent control over oxide field, electron fluence, and injected electron energy which the technique allows. We show that defect creation and oxide breakdown are dependent on the energy of the injected electrons and not on the oxide field. Furthermore, we show that the energy of the injected electrons governs whether the majority of the defects are created at the Si/SiO2 interface or in the bulk of the material. Results show that at operating conditions, the primary threat to device reliability from hot carrier damage is the introduction of a permanent 3D positive bias temperature instability component introduced by increased interface trap generation, even for carriers with energy slightly above that of field accelerated electrons. We also discuss the feasibility of using substrate hot electron injection as a means to accelerate time dependent dielectric breakdown measurements, thereby allowing degradation at lower oxide fields to be probed. [ABSTRACT FROM AUTHOR]

The charge trapping is studied in metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with SrBi2Ta2O9 (SBT)/Al2O3/SiO2 gate stack by high-frequency and pulsed capacitance-voltage (CV) measurements. The ferroelectric polarization is observed by high-frequency CV. Under fast gate voltage sweep in pulsed CV, the delay of electron trapping detrapping in the buffer layer induces an opposite CV hysteresis direction than that of the ferroelectric polarization. For memory programming, the hole trapping in the gate stack limits the electric field in SBT. Furthermore, the electron trapping during stress induces serious threshold voltage instability as well as erratic memory read out. All these charge trapping problems are important for the practical application and reliability of the memory with MFIS structure. [ABSTRACT FROM AUTHOR]

The origin of the substrate hole currents after gate oxide breakdown in metal-oxide-semiconductor field-effect transistor (nMosFET) devices is investigated, using spectroscopic and conventional photon emission microscopy. Spectral analysis of light from the breakdown locations, under positive gate bias, indicates that hot electrons mediate the light emitted from the breakdown spots. These hot electrons are generated by the high electric fields at the location of the breakdown. Furthermore, light emission due to substrate hole recombination with electrons injected from the gate through the leakage path (breakdown location) dominates the light emission spectrum under negative gate bias. This finding is further verified using carrier separation measurements. In these measurements, minority carrier currents induced by the light emitted at the breakdown location and measured at a remote pn junction are compared with the substrate hole currents before and after oxide breakdown. These measurements prove that under positive gate bias, the substrate hole current and the light emission from the breakdown locations, are dominated by hot electron impact ionization mechanism in the substrate. © 2002 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Plasma treatment induced water absorption in a SiOCH low-k dielectric and the affect of the absorbed water components on the low-k dielectric reliability are examined. The close similarity between the thermal activation energy and the bond energy associated with the chemisorbed ([beta]) water component has shown that the [beta] bond is among the weakest links for the SiOCH low-k dielectric breakdown.

The charge trapping in metal-ferroelectric-insulator-semiconductor structure with SrBi2Ta2O9/AI2O3/SiO2 stack is discussed. The competition between hole trapping and polarization effect is examined.

Presents a study that characterized substrate hot-hole injection induced hole trapping and interface trap generation. Temperature by which the characterization was made; Independence of the trapping from injection conditions in the silicon; Insensitivity of the trapping to the oxide field; Rate of initial trapping efficiencies.