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[EN] Computer simulations are broadly used nowadays in order to obtain information that would be impossible to gain otherwise. These computational workloads have grown in size to the point where even a small improvement in its implementation can lead to a substantial speed-up. For this reason, researchers have studied the impact linked to the usage of less precise numbers, since it would accelerate calculations. Likewise, this study aims to determine the feasibility of using mixed-precision arithmetic in iPIC3D, a 3D implicit Particle-in-cell (PIC) implementation used in plasma simulations. Specifically, the use of mixed-precision numbers will be limited to the particle mover, the section that solves the equations of motion for each particle of the plasma, resulting in the most time-consuming part of the code. The results show a maximum divergence or error of about 2% between the original implementation and the new one when comparing the output values. All of this, performing a relatively short simulation of 2250 cycles, therefore, with longer tasks we the error could increase. Thus, we come to the conclusion that in most cases, the loss in precision is too high to justify the use of this new implementation., [ES] Las simulaciones por ordenador son ampliamente usadas a dia de hoy para obtener información que sería imposible de conseguir de otra forma. Estas simulaciones se han hecho cada vez más grandes y complejas y cualquier mejora en el coste temporal de las mismas es algo muy importante. Así, investigadores de todo el mundo están intentando crear nuevos algoritmos y mejorar los que ya existen. Uno de los campos que se están desarrollando para intentar mejorar algoritmos existentes es el que estudia el efecto que tiene el uso de operaciones de coma flotante de menor precisión, puesto que estas operaciones son más rápidas. Asímismo, este estudio busca cuantificar el impacto que conlleva el uso de operaciones de simple precisión en iPIC3D, una implementación implícita y 3D del método "Particle-in-cell" (PIC), permitiendo llevar a cabo simulaciones de plasma. El uso de números con simple precisión se limitará al "particle mover", la sección del codigo que resuelve las ecuaciones de movimiento para cada partícula de plasma, siendo la parte del código más costosa a nivel de tiempo. Los resultados obtenidos muestran un máximo de divergencia del 2% entre la implementación original y la nueva cuando se comparan los valores finales. Todo ello, realizando una simulación de 2250 ciclos, lo cual es relativamente poco y, por lo tanto, con tareas que requieran un numero elevado de ciclos este error podría aumentar. Por todo esto, concluimos que en la mayoría de casos, lá pérdida de precisión es demasiado alta como para justificar el uso de la nueva implmementación.

The LS-STAG method is an immersed boundary/cut-cell method for viscous incompressible flows based on the staggered MAC arrangement for Cartesian grids, where the irregular boundary is sharply represented by its level-set function , results in a significant gain in computer resources (wall time, memory usage) compared to commercial body-fitted CFD codes. The 2D version of LS-STAG method is now well-established (Cheny and Botella, 2010), and this paper presents its extension to 3D geometries with translational symmetry in the z direction (hereinafter called 3D extruded configurations). This intermediate step towards the fully 3D implementation can be applied to a wide variety of canonical flows and will be regarded as the keystone for the full 3D solver, since both discretization and implementation issues on distributed memory machines are tackled at this stage of development. The LS-STAG method is then applied to various Newtonian and non-Newtonian flows in 3D extruded geometries (axisymmetric pipe, circular cylinder, duct with an abrupt expansion) for which benchmark results and experimental data are available. The purpose of these investigations are (a) to investigate the formal order of accuracy of the LS-STAG method, (b) to assess the versatility of method for flow applications at various regimes (Newtonian and shear-thinning fluids, steady and unsteady laminar to turbulent flows) (c) to compare its performance with well-established numerical methods (body-fitted and immersed boundary methods).

The LS-STAG method is an immersed boundary/cut-cell method for viscous incompressible flows based on the staggered MAC arrangement for Cartesian grids where the irregular boundary is sharply represented by its level-set function. This approach results in a significant gain in computer resources compared to commercial body-fitted CFD codes. The 2D version of LS-STAG method is now well-established and this manuscript presents its extension to 3D geometries with translational symmetry in the z direction (3D extruded configurations). This intermediate step will be regarded as the milestone for the full 3D solver, since both discretization and implementation issues on distributed memory machines are tackled at this stage of development. The LS-STAG method is then applied to Newtonian and non-Newtonian flows in 3D extruded geometries (axisymmetric pipe, circular cylinder, duct with an abrupt expansion, etc.) for which benchmark results and experimental data are available. The purpose of these investigations is to evaluate the accuracy of LS-STAG method, to assess the versatility of method for flow applications at various regimes (Newtonian and shear-thinning fluids, steady and unsteady laminar to turbulent flows, granular flows) and to compare its performance with well-established numerical methods (body-fitted and immersed boundary methods); La méthode LS-STAG est une méthode de type frontière immergée/cut-cell pour le calcul d’écoulements visqueux incompressibles qui est basée sur la méthode MAC pour grilles cartésiennes décalées, où la frontière irrégulière est nettement représentée par sa fonction level-set, résultant en un gain significatif en ressources informatiques par rapport aux codes MFN commerciaux utilisant des maillages qui épousent la géométrie. La version 2D est maintenant bien établie et ce manuscrit présente son extension aux géométries 3D avec une symétrie translationnelle dans la direction z (configurations extrudées 3D). Cette étape intermédiaire sera considérée comme la clé de voûte du solveur 3D complet, puisque les problèmes de discrétisation et d’implémentation sur les machines à mémoire distribuée sont abordés à ce stade de développement. La méthode LS-STAG est ensuite appliquée à divers écoulements newtoniens et non-newtoniens dans des géométries extrudées 3D (conduite axisymétrique, cylindre circulaire, conduite cylindrique avec élargissement brusque, etc.) pour lesquels des résultats de références et des données expérimentales sont disponibles. Le but de ces investigations est d’évaluer la précision de la méthode LS-STAG, d’évaluer la polyvalence de la méthode pour les applications d’écoulement dans différents régimes (fluides newtoniens et rhéofluidifiants, écoulement laminaires stationnaires et instationnaires, écoulements granulaires) et de comparer ses performances avec de méthodes numériques bien établies (méthodes non structurées et de frontières immergées)

The LS-STAG method is an immersed boundary/cut-cell method for viscous incompressible flows based on the staggered MAC arrangement for Cartesian grids where the irregular boundary is sharply represented by its level-set function. This approach results in a significant gain in computer resources compared to commercial body-fitted CFD codes. The 2D version of LS-STAG method is now well-established and this manuscript presents its extension to 3D geometries with translational symmetry in the z direction (3D extruded configurations). This intermediate step will be regarded as the milestone for the full 3D solver, since both discretization and implementation issues on distributed memory machines are tackled at this stage of development. The LS-STAG method is then applied to Newtonian and non-Newtonian flows in 3D extruded geometries (axisymmetric pipe, circular cylinder, duct with an abrupt expansion, etc.) for which benchmark results and experimental data are available. The purpose of these investigations is to evaluate the accuracy of LS-STAG method, to assess the versatility of method for flow applications at various regimes (Newtonian and shear-thinning fluids, steady and unsteady laminar to turbulent flows, granular flows) and to compare its performance with well-established numerical methods (body-fitted and immersed boundary methods), La méthode LS-STAG est une méthode de type frontière immergée/cut-cell pour le calcul d’écoulements visqueux incompressibles qui est basée sur la méthode MAC pour grilles cartésiennes décalées, où la frontière irrégulière est nettement représentée par sa fonction level-set, résultant en un gain significatif en ressources informatiques par rapport aux codes MFN commerciaux utilisant des maillages qui épousent la géométrie. La version 2D est maintenant bien établie et ce manuscrit présente son extension aux géométries 3D avec une symétrie translationnelle dans la direction z (configurations extrudées 3D). Cette étape intermédiaire sera considérée comme la clé de voûte du solveur 3D complet, puisque les problèmes de discrétisation et d’implémentation sur les machines à mémoire distribuée sont abordés à ce stade de développement. La méthode LS-STAG est ensuite appliquée à divers écoulements newtoniens et non-newtoniens dans des géométries extrudées 3D (conduite axisymétrique, cylindre circulaire, conduite cylindrique avec élargissement brusque, etc.) pour lesquels des résultats de références et des données expérimentales sont disponibles. Le but de ces investigations est d’évaluer la précision de la méthode LS-STAG, d’évaluer la polyvalence de la méthode pour les applications d’écoulement dans différents régimes (fluides newtoniens et rhéofluidifiants, écoulement laminaires stationnaires et instationnaires, écoulements granulaires) et de comparer ses performances avec de méthodes numériques bien établies (méthodes non structurées et de frontières immergées)

With the advent of ever-increasing graph datasets in a large number of domains, parallel graph-processing applications deployed on distributed architectures are more and more needed to cope with the growing demand for memory and compute resources. Though large-scale distributed architectures are available, notably in the High-Performance Computing (HPC) domain, the programming and deployment complexity of such graphprocessing algorithms, whose parallelization and complexity are highly data-dependent, hamper usability. Moreover, the difficult evaluation of performance behaviors of these applications complexifies the assessment of the relevance of the used architecture. With this in mind, this thesis work deals with the exploration of graph-processing algorithms on distributed architectures, notably using GraphLab, a state of the art graphprocessing framework. Two use-cases are considered. For each, a parallel implementation is proposed and deployed on several distributed architectures of varying scales. This study highlights operating ranges, which can eventually be leveraged to appropriately select a relevant operating point with respect to the datasets processed and used cluster nodes. Further study enables a performance comparison of commodity cluster architectures and higher-end compute servers using the two use-cases previously developed. This study highlights the particular relevance of using clustered commodity workstations, which are considerably cheaper and simpler with respect to node architecture, over higher-end systems in this applicative context. Then, this thesis work explores how performance studies are helpful in cluster design for graph-processing. In particular, studying throughput performances of a graph-processing system gives fruitful insights for further node architecture improvements. Moreover, this work shows that a more in-depth performance analysis can lead to guidelines for the appropriate sizing of a cluster for a given workload, paving the way toward resource allocation for graph-processing. Finally, hardware improvements for next generations of graph-processing servers areproposed and evaluated. A flash-based victim-swap mechanism is proposed for the mitigation of unwanted overloaded operations. Then, the relevance of ARM-based microservers for graph-processing is investigated with a port of GraphLab on a NVIDIA TX2-based architecture.; Avec l'explosion du volume de données produites chaque année, les applications du domaine du traitement de graphes ont de plus en plus besoin d'être parallélisées et déployées sur des architectures distribuées afin d'adresser le besoin en mémoire et en ressource de calcul. Si de telles architectures larges échelles existent, issue notamment du domaine du calcul haute performance (HPC), la complexité de programmation et de déploiement d’algorithmes de traitement de graphes sur de telles cibles est souvent un frein à leur utilisation. De plus, la difficile compréhension, a priori, du comportement en performances de ce type d'applications complexifie également l'évaluation du niveau d'adéquation des architectures matérielles avec de tels algorithmes. Dans ce contexte, ces travaux de thèses portent sur l’exploration d’algorithmes de traitement de graphes sur architectures distribuées en utilisant GraphLab, un Framework de l’état de l’art dédié à la programmation parallèle de tels algorithmes. En particulier, deux cas d'applications réelles ont été étudiées en détails et déployées sur différentes architectures à mémoire distribuée, l’un venant de l’analyse de trace d’exécution et l’autre du domaine du traitement de données génomiques. Ces études ont permis de mettre en évidence l’existence de régimes de fonctionnement permettant d'identifier des points de fonctionnements pertinents dans lesquels on souhaitera placer un système pour maximiser son efficacité. Dans un deuxième temps, une étude a permis de comparer l'efficacité d'architectures généralistes (type commodity cluster) et d'architectures plus spécialisées (type serveur de calcul hautes performances) pour le traitement de graphes distribué. Cette étude a démontré que les architectures composées de grappes de machines de type workstation, moins onéreuses et plus simples, permettaient d'obtenir des performances plus élevées. Cet écart est d'avantage accentué quand les performances sont pondérées par les coûts d'achats et opérationnels. L'étude du comportement en performance de ces architectures a également permis de proposer in fine des règles de dimensionnement et de conception des architectures distribuées, dans ce contexte. En particulier, nous montrons comment l’étude des performances fait apparaitre les axes d’amélioration du matériel et comment il est possible de dimensionner un cluster pour traiter efficacement une instance donnée. Finalement, des propositions matérielles pour la conception de serveurs de calculs plus performants pour le traitement de graphes sont formulées. Premièrement, un mécanisme est proposé afin de tempérer la baisse significative de performance observée quand le cluster opère dans un point de fonctionnement où la mémoire vive est saturée. Enfin, les deux applications développées ont été évaluées sur une architecture à base de processeurs basse-consommation afin d'étudier la pertinence de telles architectures pour le traitement de graphes. Les performances mesurés en utilisant de telles plateformes sont encourageantes et montrent en particulier que la diminution des performances brutes par rapport aux architectures existantes est compensée par une efficacité énergétique bien supérieure.

With the advent of ever-increasing graph datasets in a large number of domains, parallel graph-processing applications deployed on distributed architectures are more and more needed to cope with the growing demand for memory and compute resources. Though large-scale distributed architectures are available, notably in the High-Performance Computing (HPC) domain, the programming and deployment complexity of such graphprocessing algorithms, whose parallelization and complexity are highly data-dependent, hamper usability. Moreover, the difficult evaluation of performance behaviors of these applications complexifies the assessment of the relevance of the used architecture. With this in mind, this thesis work deals with the exploration of graph-processing algorithms on distributed architectures, notably using GraphLab, a state of the art graphprocessing framework. Two use-cases are considered. For each, a parallel implementation is proposed and deployed on several distributed architectures of varying scales. This study highlights operating ranges, which can eventually be leveraged to appropriately select a relevant operating point with respect to the datasets processed and used cluster nodes. Further study enables a performance comparison of commodity cluster architectures and higher-end compute servers using the two use-cases previously developed. This study highlights the particular relevance of using clustered commodity workstations, which are considerably cheaper and simpler with respect to node architecture, over higher-end systems in this applicative context. Then, this thesis work explores how performance studies are helpful in cluster design for graph-processing. In particular, studying throughput performances of a graph-processing system gives fruitful insights for further node architecture improvements. Moreover, this work shows that a more in-depth performance analysis can lead to guidelines for the appropriate sizing of a cluster for a given workload, paving the way toward resource allocation for graph-processing. Finally, hardware improvements for next generations of graph-processing servers areproposed and evaluated. A flash-based victim-swap mechanism is proposed for the mitigation of unwanted overloaded operations. Then, the relevance of ARM-based microservers for graph-processing is investigated with a port of GraphLab on a NVIDIA TX2-based architecture., Avec l'explosion du volume de données produites chaque année, les applications du domaine du traitement de graphes ont de plus en plus besoin d'être parallélisées et déployées sur des architectures distribuées afin d'adresser le besoin en mémoire et en ressource de calcul. Si de telles architectures larges échelles existent, issue notamment du domaine du calcul haute performance (HPC), la complexité de programmation et de déploiement d’algorithmes de traitement de graphes sur de telles cibles est souvent un frein à leur utilisation. De plus, la difficile compréhension, a priori, du comportement en performances de ce type d'applications complexifie également l'évaluation du niveau d'adéquation des architectures matérielles avec de tels algorithmes. Dans ce contexte, ces travaux de thèses portent sur l’exploration d’algorithmes de traitement de graphes sur architectures distribuées en utilisant GraphLab, un Framework de l’état de l’art dédié à la programmation parallèle de tels algorithmes. En particulier, deux cas d'applications réelles ont été étudiées en détails et déployées sur différentes architectures à mémoire distribuée, l’un venant de l’analyse de trace d’exécution et l’autre du domaine du traitement de données génomiques. Ces études ont permis de mettre en évidence l’existence de régimes de fonctionnement permettant d'identifier des points de fonctionnements pertinents dans lesquels on souhaitera placer un système pour maximiser son efficacité. Dans un deuxième temps, une étude a permis de comparer l'efficacité d'architectures généralistes (type commodity cluster) et d'architectures plus spécialisées (type serveur de calcul hautes performances) pour le traitement de graphes distribué. Cette étude a démontré que les architectures composées de grappes de machines de type workstation, moins onéreuses et plus simples, permettaient d'obtenir des performances plus élevées. Cet écart est d'avantage accentué quand les performances sont pondérées par les coûts d'achats et opérationnels. L'étude du comportement en performance de ces architectures a également permis de proposer in fine des règles de dimensionnement et de conception des architectures distribuées, dans ce contexte. En particulier, nous montrons comment l’étude des performances fait apparaitre les axes d’amélioration du matériel et comment il est possible de dimensionner un cluster pour traiter efficacement une instance donnée. Finalement, des propositions matérielles pour la conception de serveurs de calculs plus performants pour le traitement de graphes sont formulées. Premièrement, un mécanisme est proposé afin de tempérer la baisse significative de performance observée quand le cluster opère dans un point de fonctionnement où la mémoire vive est saturée. Enfin, les deux applications développées ont été évaluées sur une architecture à base de processeurs basse-consommation afin d'étudier la pertinence de telles architectures pour le traitement de graphes. Les performances mesurés en utilisant de telles plateformes sont encourageantes et montrent en particulier que la diminution des performances brutes par rapport aux architectures existantes est compensée par une efficacité énergétique bien supérieure.

In recent years, the HPC community has increasingly grown its interest towards the Arm architecture with research projects targeting primarily the installation of Arm-based clusters. State of the art research project examples are the European Mont-Blanc, the Japanese Post-K, and the UKs GW4/EPSRC. Primarily attention is usually given to hardware platforms, and the Arm HPC community is growing as the hardware is evolving towards HPC workloads via solutions borrowed from mobile market e.g., big.LITTLE and additions such as Armv8-A Scalable Vector Extension (SVE) technology. However the availability of a mature software ecosystem and the possibility of running large and complex HPC applications plays a key role in the consolidation process of a new technology, especially in a conservative market like HPC. For this reason in this poster we present a preliminary evaluation of the Arm system software ecosystem, limited here to the Arm HPC Compiler and the Arm Performance Libraries, together with a porting and testing of three fairly complex HPC code suites: QuantumESPRESSO, WRF and FEniCS. The selection of these codes has not been totally random: they have been in fact proposed as HPC challenges during the last two editions of the Student Cluster Competition at ISC where all the authors have been involved operating an Arm-based cluster and awarded with the Fan Favorite award. The research leading to these results has received funding from the European Community's Seventh Framework Programme [FP7/2007-2013] and Horizon 2020 under the Mont-Blanc projects [3], grant agreements n. 288777, 610402 and 671697. The authors would also like to thank E4 Computer Engineering for providing part of the hardware resources needed for the evaluation carried out in this poster as well as for greatly supporting the Student Cluster Competition team.

Supercomputers offer new opportunities for scientific computing as they grow in size. However, their growth also poses new challenges. Resilience has been recognized as one of the most pressing issues to solve for extreme scale computing. Transistor scaling in the single-digit nanometer era and power constraints might dramatically increase the failure rate of next generation machines. DRAM errors have been analyzed in the past for different supercomputers but those studies are usually based on job scheduler logs and counters produced by hardware-level error correcting codes. Consequently, little is known about errors escaping hardware checks, which lead to silent data corruption. This work attempts to fill that gap by analyzing memory errors for over a year on a cluster with about 1000 nodes featuring low-power memory without error correction. The study gathered millions of events recording detailed information of thousands of memory errors, many of them corrupting multiple bits. Several factors are analyzed, such as temporal and spatial correlation between errors, but also the influence of temperature and even the position of the sun in the sky. The study showed that most multi-bit errors corrupted non-adjacent bits in the memory word and that most errors flipped memory bits from 1 to 0. In addition, we observed thousands of cases of multiple single-bit errors occurring simultaneously in different regions of the memory. These new observations would not be possible by simply analyzing error correction counters on classical systems. We propose several directions in which the findings of this study can help the design of more reliable systems in the future. The research leading to these results has received funding from the European Community’s Seventh Framework Programme [FP7/2007-2013] under the Mont-Blanc 2 Project (www.montblanc-project.eu), grant agreement n 610402 and it has been supported in part by the European Union (FEDER funds) under contract TIN2015-65316-P.

As machines get larger and scientific applications advance, it is more and more imperative to fully utilize high performance computing (HPC) capability. The complexity and changing landscape of parallel computers may lead to users being unable or unsure how to achieve optimal performance from their applications and fully utilize their HPC resources. The Performance Optimisation and Productivity Centre of Excellence in Computing Applications (POP) has received funding from the European Commission as part of the Horizon 2020 programme to help alleviate these issues. It aims to uncover inefficiencies and their causes in existing parallel HPC applications that will lead to an improvement in the productivity and competitiveness of European organizations, in academia, government and industry. The POP project will drive efforts to highlight the need for and best practices in performance optimization through performance audits on codes along with training events to improve knowledge in this area. The aim is to help developers target their code development and refactoring in the most efficient direction and provide a return on investment from the savings due to the performance improvement. The POP project combines the expertise and experience of Barcelona Supercomputing Center (BSC), High Performance Computing Center Stuttgart, Jülich Supercomputing Centre (JSC), Numerical Algorithms Group Ltd (NAG), RWTH Aachen and TERATEC. This combination provides longstanding and well respected resources in the academic and commercial realms. The POP members have come together to create a coherent and consistent methodology to give a clear, precise and useful overview of the performance of each HPC application. The services of the POP project are free of charge to organizations with in the EU to analyze and advise on any parallel code in academic, government or industrial organizations of any domain.

In this paper, we evaluate the error criticality of radiation-induced errors on modern High-Performance Computing (HPC) accelerators (Intel Xeon Phi and NVIDIA K40) through a dedicated set of metrics. We show that, as long as imprecise computing is concerned, the simple mismatch detection is not sufficient to evaluate and compare the radiation sensitivity of HPC devices and algorithms. Our analysis quantifies and qualifies radiation effects on applications’ output correlating the number of corrupted elements with their spatial locality. Also, we provide the mean relative error (dataset-wise) to evaluate radiation-induced error magnitude. We apply the selected metrics to experimental results obtained in various radiation test campaigns for a total of more than 400 hours of beam time per device. The amount of data we gathered allows us to evaluate the error criticality of a representative set of algorithms from HPC suites. Additionally, based on the characteristics of the tested algorithms, we draw generic reliability conclusions for broader classes of codes. We show that arithmetic operations are less critical for the K40, while Xeon Phi is more reliable when executing particles interactions solved through Finite Difference Methods. Finally, iterative stencil operations seem the most reliable on both architectures. This work was supported by the STIC-AmSud/CAPES scientific cooperation program under the EnergySFE research project grant 99999.007556/2015-02, EU H2020 Programme, and MCTI/RNP-Brazil under the HPC4E Project, grant agreement n° 689772. Tested K40 boards were donated thanks to Steve Keckler, Timothy Tsai, and Siva Hari from NVIDIA.

High-performance computing (HPC) is recognized as one of the pillars for further progress in science, industry, medicine, and education. Current HPC systems are being developed to overcome emerging architectural challenges in order to reach Exascale level of performance, projected for the year 2020. The much larger embedded and mobile market allows for rapid development of intellectual property (IP) blocks and provides more flexibility in designing an application specific system-on-chip (SoC), in turn providing the possibility in balancing performance, energy-efficiency, and cost. In the Mont-Blanc project, we advocate for HPC systems being built from such commodity IP blocks, currently used in embedded and mobile SoCs. As a first demonstrator of such an approach, we present the Mont-Blanc prototype; the first HPC system built with commodity SoCs, memories, and network interface cards (NICs) from the embedded and mobile domain, and off-the-shelf HPC networking, storage, cooling, and integration solutions. We present the system’s architecture and evaluate both performance and energy efficiency. Further, we compare the system’s abilities against a production level supercomputer. At the end, we discuss parallel scalability and estimate the maximum scalability point of this approach across a set of applications.

Robust projections and predictions of climate variability and change, particularly at regional scales, rely on the driving processes being represented with fidelity in model simulations. The role of enhanced horizontal resolution in improved process representation in all components of the climate system is of growing interest, particularly as some recent simulations suggest both the possibility of significant changes in large-scale aspects of circulation as well as improvements in small-scale processes and extremes. However, such high-resolution global simulations at climate timescales, with resolutions of at least 50 km in the atmosphere and 0.25° in the ocean, have been performed at relatively few research centres and generally without overall coordination, primarily due to their computational cost. Assessing the robustness of the response of simulated climate to model resolution requires a large multi-model ensemble using a coordinated set of experiments. The Coupled Model Intercomparison Project 6 (CMIP6) is the ideal framework within which to conduct such a study, due to the strong link to models being developed for the CMIP DECK experiments and other model intercomparison projects (MIPs). Increases in high-performance computing (HPC) resources, as well as the revised experimental design for CMIP6, now enable a detailed investigation of the impact of increased resolution up to synoptic weather scales on the simulated mean climate and its variability. The High Resolution Model Intercomparison Project (HighResMIP) presented in this paper applies, for the first time, a multi-model approach to the systematic investigation of the impact of horizontal resolution. A coordinated set of experiments has been designed to assess both a standard and an enhanced horizontal-resolution simulation in the atmosphere and ocean. The set of HighResMIP experiments is divided into three tiers consisting of atmosphere-only and coupled runs and spanning the period 1950–2050, with the possibility of extending to 2100, together with some additional targeted experiments. This paper describes the experimental set-up of HighResMIP, the analysis plan, the connection with the other CMIP6 endorsed MIPs, as well as the DECK and CMIP6 historical simulations. HighResMIP thereby focuses on one of the CMIP6 broad questions, “what are the origins and consequences of systematic model biases?”, but we also discuss how it addresses the World Climate Research Program (WCRP) grand challenges. PRIMAVERA project members (Malcolm J. Roberts, Reindert J. Haarsma, Pier Luigi Vidale, Torben Koenigk, Virginie Guemas, Susanna Corti, Jost von Hardenberg, Jin-Song von Storch,Wilco Hazeleger, Catherine A. Senior, Matthew S. Mizielinsky, Tido Semmler, Alessio Bellucci, Enrico Scoccimarro, Neven S. Fuckar) acknowledge funding received from the European Commission under grant agreement 641727 of the Horizon 2020 research programme. Chihiro Kodama acknowledges Y. Yamada, M. Nakano, T. Nasuno, T. Miyakawa, and H. Miura for analysis ideas. Neven S. Fuckar acknowledges support of the Juan de la Ciervaincorporación postdoctoral fellowship from the Ministry of Economy and Competitiveness of Spain. L. Ruby Leung and Jian Lu acknowledge support from the U.S. Department of Energy Office of Science Biological and Environmental Research as part of the Regional and Global Climate Modeling Program. The Pacific Northwest National Laboratory is operated for the DOE by Battelle Memorial Institute under contract DE-AC05-76RLO1830. Jiafu Mao is supported by the Biogeochemistry-Climate Feedbacks Scientific Focus Area project funded through the Regional and Global Climate Modeling Program in Climate and Environmental Sciences Division (CESD) of the Biological and Environmental Research (BER) Program in the U.S. Department of Energy Office of Science. Oak Ridge National Laboratory is managed by UTBATTELLE for the DOE under contract DE-AC05-00OR22725. Paulo Nobre acknowledges support from CNPq grant nos. 573797/2008-0 and 490237/2011-8, and FAPESP grant no. 2008/57719-9. Chihiro Kodama and Masaki Satoh are supported by the Program for Risk Information on Climate Change (SOSEI) and the FLAGSHIP2020 within the priority study4 (Advancement of meteorological and global environmental predictions utilizing observational “Big Data”), which are promoted by the Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan. Ping Chang is supported by US National Science Foundation grants AGS-1462127 and AGS-1067937, and National Oceanic and Atmospheric Administration grant NA11OAR4310154, as well as by China’s National Basic Research Priorities Programme (2013CB956204 and 2014CB745000). We thank Martin Juckes and his team for all their work on the HighResMIP and CMIP6 data request. Nick Rayner and John Kennedy for allowing early access to the HadISST2 daily, 1/4º SST and sea-ice dataset. Mark Ringer and Mark Webb for ideas for the targeted CFMIP-style experiment. Francois Massonnet for discussions on high-resolution modelling and sea ice.

Verification of electro-mechanic models of the heart require a good amount of reliable, high resolution, thorough in-vivo measurements. The detail of the mathematical models used to create simulations of the heart beat vary greatly. Generally, the objective of the simulation determines the modeling approach. However, it is important to exactly quantify the amount of error between the various approaches that can be used to simulate a heart beat by comparing them to ground truth data. The more detailed the model is, the more computing power it requires, we therefore employ a high-performance computing solver throughout this study. We aim to compare models to data measured experimentally to identify the effect of using a mathematical model of fibre orientation versus the measured fibre orientations using DT-MRI. We also use simultaneous endocardial stimuli vs an instantaneous myocardial stimulation to trigger the mechanic contraction. Our results show that synchronisation of the electrical and mechanical events in the heart beat are necessary to create a physiological timing of hemodynamic events. Synchronous activation of all of the myocardium provides an unrealistic timing of hemodynamic events in the cardiac cycle. Results also show the need of establishing a protocol to quantify the zero-pressure configuration of the left ventricular geometry to initiate the simulation protocol; however, the predicted zero-pressure configuration of the same geometry was different, depending on the origin of the fibre field employed. This work has been done with the support of the grant SEV-2011-00067 of Severo Ochoa Program, awarded by the Spanish Government to the Barcelona Supercomputing Center. Part of the research leading to these results has received funding from the Seventh Framework Programme (FP7/2007-2013) under grant agreement n 611823. It has also been partially funded from the by the Spanish Ministry of Economy and Competitiveness (TIN2011-28067).

Modern society relies on convenience services and mobile communication. Cloud computing is the current trend to make data and applications available at any time on every device. Data centers concentrate computation and storage at central locations, while they claim themselves green due to their optimized maintenance and increased energy efficiency. The key enabler for this evolution is the microelectronics industry. The trend to power efficient mobile devices has forced this industry to change its design dogma to: ”keep data locally and reduce data communication whenever possible”. Therefore we ask: is cloud computing repeating the aberrations of its enabling industry?

In recent years, several lightweight thread (LWT) libraries have emerged to tackle exascale challenges. These offer programming models (PMs) based on user-level threads and incorporate their own lightweight mechanisms. However, each library proposes its own PM, exposing different semantics and hindering portability. To address this drawback, we have designed Generic Lightweight Thread (GLT), an application programming interface that frames the functionality of the most popular LWT libraries for high-performance computing under a single PM. We implement GLT on top of Argobots, MassiveThreads, and Qthreads. We provide GLT as a dynamic library, as well as in the form of a static version based on macro preprocessing resolution to reduce overhead. This paper discusses the GLT PM and demonstrates its minimal performance impact. Researchers from the Universitat Jaume I de Castelló were supported by project TIN2014-53495-R of the MINECO, the Generalitat Valenciana fellowship programme Vali+d 2015, and FEDER. Antonio J. Peña is cofinancied by the Spanish Ministry of Economy and Competitiveness under Juan de la Cierva fellowship number IJCI-2015-23266. This work was partially supported by the U.S. Dept. of Energy, Office of Science, Office of Advanced Scientific Computing Research (SC-21), under contract DE-AC02-06CH11357.