Search

In this paper, we apply the voltage overscaling (VOS) technique to the residue-number-system (RNS)-based digital signal processing system for achieving high energy efficiency. To mitigate the soft errors caused by VOS, we propose a new method, called joint RNS-RPR (JRR), which is the combination of RNS and the reduced precision redundancy (RPR) technique. The JRR technology inherits the properties of RNS, including shorter critical path, low complexity, and low power. Moreover, JRR can achieve higher power reduction than RNS for VOS applications. Since the soft errors caused by VOS lead to significant performance degradation of RNS, we use the information from RNS and RPR to achieve a high recovering probability of the soft errors with low hardware complexity. From the case study of finite impulse response (FIR) filter design based on the 0.25-\mum 2.5-V CMOS technology, we find that JRR can save 62% more energy compared to the traditional FIR with a less than 2-dB signal noise ratio performance loss. We also find that JRR has lower complexity and better performance than the traditional soft error mitigation methods. [ABSTRACT FROM PUBLISHER]

We propose an effective scheme based on redundant residue number systems (RRNS) for radiation hardening of datapath in this paper. The proposed hardening scheme employs redundant residues to mitigate soft errors. We use the properties of RRNS, such as independence, parallel and error correction, to establish the radiation hardening architecture for datapath in radiation environments. In the architecture, all of the residues can be processed independently, and most of soft errors in datapath can be corrected with the redundant relationship of the residues at correction module, which is allocated at the end of the architecture. There is not any additional processing in the architecture but correction operation and binary to residue translation. Thus, the proposed scheme has high efficiency when the processing steps of datapath are large. In order to provide protection for the key module in the proposed scheme, correction module, some traditional protection methods, including Guard-gate register triple modular redundancy (G-RTMR), pipeline-level TMR, and module-level TMR, are used to construct the hybrid protection schemes. In the case studies, we find that the RRNS based scheme and the hybrid schemes can reduce soft error rate from 10-12 to 10-17, -18,10-25, and -25-respectively, only with 45.-46.1% area overheads and negligible latency overheads, when the pipeline stages of datapath are 104 and the moduli set with correction capability of one residue is adopted. The case studies also show that the proposed schemes can achieve less area and latency overheads than that of datapath without radiation hardening, because RRNS can reduce the complexity of operations in datapath. [ABSTRACT FROM AUTHOR]

High efficient implementation of scaling in residue number system (RNS) is one of the critical issues for the applications of RNS in digital signal processing (DSP) systems. In this paper, an efficient scaling algorithm for signed integers in RNS is proposed firstly through introducing a correction constant in negative integers scaling procedure. Based on the proposed scaling algorithm, an efficient RNS 2 n scaling implementation method is presented, in which Chinese remainder theorem (CRT) and a redundant modulus are used to perform the base extension to obtain the least significant n bits of RNS integers. With the redundant modulus, the RNS sign detection can be achieved by the parity detection. And then, an approach to update the residue digit of the redundant channel is also proposed. Meanwhile, this paper provides a method of computing the correction constant of the redundant channel in negative integers scaling. The analysis results indicate that the complexity of the proposed scaling algorithm grows linearly with the word-length of the RNS dynamic range without using Look-up Table (LUT). Furthermore, the proposed algorithm is employed for a specific moduli set 2 n scaling. The synthesis results show that the critical path of the proposed algorithm is shortened by 12%, the area and power consumption performance is improved by about 35%, compared to the existing cascading 2 n scaling method for very large scale integration (VLSI) implementation under the same restriction. Besides, the VLSI layout indicates that the parallel structure is simpler. [ABSTRACT FROM AUTHOR]

Residue number system (RNS) has received considerable attention since decades before, because it has inherent carry-free and parallel properties in addition, subtraction, and multiplication operations. For an odd moduli set, the fundamental problems in RNS, such as number comparison, sign determination, and overflow detection, can be solved based on parity checking. The paper proposes a parity checking algorithm along with related propositions and the certification based on the celebrated Chinese remainder theory (CRT) and mixed radix conversion (MRC) for the moduli set {2 n − 1, 2 n + 1, 22 n + 1}. The parity checker consists of two modular adders and a carry-look-ahead chain. The hardware implementation requires less area and path delay. Besides, the implementations of number comparison, sign determination, and overflow detection, which are based on this parity checker, are also performed in this paper. And this kind of parity checker can be used as a basic element to design ALUs and DSP module in RNS. [ABSTRACT FROM AUTHOR]