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Summary form only given, as follows. Tremendous advances in application specific integrated circuit (ASIC) technology are continually being made in speed, power, and gate density. This paper discusses the development of an automated translation process that allows the advances in ASIC technology to be applied to existing ASIC designs without having to redesign the ASICs. This translation process is accomplished by replacing an existing design with a functionally equivalent design that is created to take advantage of the advances in ASIC technologies. The translation process makes use of various HDL (Hardware Design Language) based computer tools, old and new technology libraries, and VHDL (Very High Speed Integrated Circuit HDL). Automated translation has proven to be time and cost effective and is being applied in various projects at the author's sponsoring company.

For pt. I see ibid., p. 550-6 (1998). This paper illustrates via examples problems at the design-manufacturing interface that exist in the IC industry today, and the ability of the YAN/PODEMA framework in solving these problems. The need for further development of the framework is also emphasized.

In the past 50 years, the semiconductor industry has experienced unprecedented growth. Identifying pivotal factors and technology trends in future generations will be key to understanding how we can maintain the historical growth and improve customer value. Processor performance will be one of the essential factors in this quest. This paper presents a high-level model of microprocessor clock-cycle performance. The model considers the impact of interconnect technology, device and circuit technology, along with architectural and physical design factors, to estimate clock speeds of future microprocessors.

An integrated circuit process R&D facility concurrently conducts advanced research, process control and product prototyping of three Very Large Scale Integrated Circuit process generations. Self-managed inter-departmental teams of process engineers and device physicists govern most aspects of process integration through a peer review process, and collectively design short cycle experiments. Organizational structures are adjusted to minimize the number of communication channels. Key metrics traditionally associated with process integration improve by a factor of three.

We describe a tool to predict and analyze the effects of processing fluctuations on circuit behaviour. This tool enables the designer to optimize the performance and robustness of the design. Furthermore, the tool helps to reduce the time to market by helping to fit the design in a given process. Information gained in this way can also help to decide where to put more effort in controlling the process and where the control might perhaps be relaxed. After the description of the tool we present results and application examples.

The traditional design of analog integrated circuits relies largely on a mixture of expertise, some manual calculations, and numerical circuit simulation. Recent research and development in the field of symbolic circuit analysis has produced results which may have considerable impact on some parts of the traditional design flow, but few analog designers have adopted symbolic analysis techniques as standard tools in their CAD environments yet. To a large extent this may be due to the lack of documented methodologies which show what can be expected from symbolic analysis and how it can be efficiently employed to solve industrial circuit design problems. In this paper, the application of symbolic analysis and computer algebra to such a design problem is demonstrated. It will be shown how symbolic analysis can help to better understand a circuit in order to improve the quality of the design.

In general, product design can be viewed as an optimization problem, where the objective is some measure of performance or life cycle cost. An important feature of integrated circuit fabrication that has no apparent analog in other industries is the need to consider the net yield of the fabrication process during the design phase of product development. This paper discusses the problem of optimal circuit design with respect to yield, which has become an important application for nonlinear optimization techniques.

A simple, accurate and inexpensive approach to worst case analysis of integrated circuits is presented. The approach may be applied to either known process statistics or a database of candidate simulation points.

Success in the competitive global markets of integrated circuits and electronics systems requires the design and fabrication of increasingly complex products coupled with ever-increasing quality requirements and ever-decreasing market windows of opportunity. Gone are the days when integrated circuit testing was it task not considered to add any value to a product and thus when test responsibilities could simply be passed on from designers to test engineers, leaving all testing considerations for the bad-end of the design or manufacturing process. Testing costs are often reported as representing anywhere from 10 to 50% or more of total product development costs. This paper reviews the principles of integrated circuit design for testability (DFT) and shows how such practice can be valuable and helpful to successfully harness the available semiconductor technology to meet stringent market and customer requirements. Structured DFT techniques are reviewed, and, in particular, the highly effective DFT strategy known as built-in self-test (BIST).

This paper shows an environment for Bluetooth baseband integrated circuit development. Each phase in development is shown as well as all introduced advantages with this methodology. All phases are interconnected and create a complex testing environment.

The complexity of the interconnect topology of a circuit is well captured by Rent's rule. This rule can be applied for a priori wire-length estimation, which is useful for improving the quality of generated layouts, and could be used for reducing the number of design iterations. It can also successfully be applied for the generation of synthetic benchmark circuits. However Rent's role is an empirical approximation, and there are many deviations. This paper describes possible extensions to Rent's rule and discusses some of its applications.

This paper considers the questions of distributed framework hybrid integration circuits CAD environment using Common Object Request Broker Architecture.

Architectural synthesis is an efficient design process that reduces the gap between algorithms and architectures by raising the abstraction level. However, this process currently does not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant using submicron technologies. In this paper, an interconnection cost analysis at the behavioural level is performed in order to provide rapid prototyping results and to direct the synthesis process with additional path constraints. Results are presented showing the interest of this approach.

A sophisticated software framework, AMODA, is presented for the automatic migration of analog macro designs between different manufacturing processes. This very important requirement for efficient design re-use is formulated as an optimization problem, while AMODA provides full flexibility in the problem formulation to achieve high efficiency and quality design. The examples demonstrate the effective design re-use techniques that are integrated into the framework.

Improvement of the traditional ASIC design methodology is targeted towards achieving significant increase in design productivity. This is especially critical in handling complex system-on-a-chip (SOC) products that allow only a short design cycle. In order to meet delivery times and avoid loss of opportunity to market, a technique that allows reuse of pre-designed intellectual properties (IPs) must be developed. Designers at MIMOS' Microelectronics Lab focus on quick integration of CPU, peripherals and memory blocks to a flexible system interconnect architecture (IA) to aggressively shorten design time. This paper describes a versatile approach in IA-based SOC design and gives a detail accounts of integration of a variety of IPs to the IA.

This paper concerns the design and development of an application specific integrated circuit, targeting advanced ATM over ADSL applications. The work focuses on the functional verification of this processor and presents the hardware and the basic software architecture of the entire integrated circuit.

Architectural synthesis tools map algorithms to architectures under real time constraints and quickly provide estimations of area and performance. However, these tools do not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant with the technology decrease and the application complexity increase. A new methodology that enables the interconnection cost to be controlled all along the architectural synthesis process is presented in this paper.

This paper presents a method for deriving a BIST specification directly from the initial specification of datapath architectures. It minimizes BIST area overhead while guaranteeing user chosen fault coverage. The results show great improvements over lower level techniques.

It has been estimated recently that within few years there will be more wireless terminals connected to the Internet and related services than there will be fixed equipment (desktop PCs, etc.). This means that the portable equipment needs high performance and high functionality combined with small size and low energy consumption, all this at low cost. Inevitably, very high packaging efficiency is needed and new packaging and substrate technologies will be required. Area array packages, especially chip scale package and flip chip, can provide minimal package size but the new packages require much higher routing capability from the substrates than before. New substrate technologies, such as microvia printed wiring boards have actively been developed in the last years, and they can meet the challenges for some time. However, with the fast integrated circuit development, there is clearly demand for technologies that give the solutions for the future.

Increasing integration levels are the driving force towards systems-on-a-chip. Designing microsystems is an emerging discipline facing specific challenges, resulting from the heterogeneous nature of the components to be integrated. A successful model and a useful simulation must be able to encompass several disciplines, and to adequately describe the coupling among heterogeneous phenomena. The functionality often depends on phenomena taking place at largely different scales, both in space and in time, making multi-scale simulation a necessity. Adequate multi-scale, multi-discipline modeling is a pre-requisite for closed loop optimizers, automating microsystems design. This paper contains an overview of some recent developments in this area.

Trends in silicon process and packaging technologies require a tighter integration among manufacturing steps historically well distinct. It is becoming increasingly difficult to design and manufacture the most complex systems-on-a-chip (SOC) without a unified approach which allows taking into account the relationship between the package and the integrated circuits (IC) design flows. We present a new methodology, able to convey board- and package-related information into the classical IC design flow and vice versa. This is the key to ensure the physical implementation is correct the first time, meeting high-density and high-speed design challenges. ICPack (IC & Package Design Integration) is a flexible and adaptable EDA environment, Java- and Web-based, which aims at reducing the number of iterations required to meet the design objectives in terms of quality, reliability, productivity and time to qualification.

Today's industry is expanding the high performance microprocessor market into the consumer market place. This market requires very low cost, high reliability, stricter SPQL levels, and very high yields. A New Diagnostic Methodology is required to meet these new demands. This paper addresses a broad scope of issues from Product Design and Manufacturing Test, to Diagnostic and Data Analysis Tools. It describes a beta test case currently in operation on IBM's latest PowerPC products in their copper and SOI technologies.

An important contributor to the success of any complex database development is the comprehensive and accurate capture and recording of the users’ information requirements. Indeed, both the technical and economic success of the system under development is likely to rest largely on the quality of the data structure design and the information requirement analysis on which it is based. The data models, which represent the results of the analysis and design activities necessary to achieve this quality outcome, are therefore critical components of the database development process. Nevertheless, research suggests that this modeling is not always done well and in some cases is not done at all (e.g., Hitchman, 1995). However, implicit in the creation of a database is the design of a data model, and thus the only optional feature is the level of formality that has been followed in its development (Simsion, 1994). Since the publication of Chen’s (1976) original description of an Entity-relationship (E-R) model, a significant amount of academic research into data modeling has concentrated on providing ever richer, more complex and more formal models with which to better represent reality (Hirschheim, Klein & Lyytinen, 1995). In addition, researchers and practitioners have also recognized the importance of data models as a means of communication. However, little attention has been given to examining the appropriateness of various modeling techniques to the very different requirements of the analysis and design activities that they support, although matching tools to activities would seem to be an essential prerequisite for success. The INTECoM framework, described in this chapter, was developed to emphasize and better serve the differing nature of these activities, and also to improve access for all users to both the process and the outcome of data modeling. The framework was initially instantiated with two widely used data modeling techniques, the NIAM-CSDP (Natural Language Information Analysis-Conceptual Schema Design Procedure) and the Entity-Relationship (E-R) approach. This instantiation was chosen primarily because the two techniques represent significantly different ways of working (Bronts, Brouwer, Martens & Proper, 1995) towards the construction of a relational database. This is not to suggest that other instantiations are not possible or desirable, particularly where the target DBMS is of a different paradigm.

The goal of this paper is to discuss the development of standard cell library creation by the Library Development Group, Microelectronics Lab, MIMOS. This involves creating new design rules, layout design, simulation and verification of each standard cell and finally characterization of all cells for timing and functional properties. The library implemented in this work is designed based on technology developed by MIMOS Wafer Fab processes.

Collaborative technology is a rapidly evolving area, specifically in the arena of microelectronics. The vast developments in microelectronics and VLSIC have been changing the world’s culture in many aspects since the inception of the Solid-State Transistor (1947). The following 20 years witnessed the initial IC concept as proposed by J. Kolby and R. Noyce (1956) and the resulting development of monolithic integrated circuits. Reduction in size and cost of microelectronic systems has been a consistency reoccurring phenomena. The 80’s and 90’s marked an era of more complex competition from the device/circuit level into effective use of design automation tools. This paper discusses contemporary integrated circuit development technologies and associated collaborative courses using a variety of methodologies including distributed education. The goal is to suggest techniques for proper identification, definition, and application of mixed-domain technologies for Systemon-a-Chip (SOC) development involving multidisciplinary and collaborative design. These elements are crucial aspects in evolving a successful graduate class or classes on microsystems, and “smart system” integration in the new Millennium. This type of course is necessary since the new collaborative technology is creating paradigms for large complex microsystem design which requires that multidisciplinary skills be introduced and understood in academic, research and development environments.

The answer to the question of whether failure analysis can keep pace with IC technology development is yes from a technical viewpoint, if some new recipes for new materials and packages can be established, but the realization will be a revolution in failure analysis (FA) in terms of methods, skills and tools. From a business point of view, the answer is only yes if FA can offer adequate results for reasonable costs in order to fulfil the cost reduction requirements of semiconductor products. With all the innovations in FA necessary to meet semiconductor development requirements, FA becomes a relevant cost factor in IC business. FA road maps are discussed for their implications on investment, required analyst skills, lab organization and time to results. This presentation concludes that the resulting FA cost explosion cannot be compensated by any conceivable measures to enhance FA productivity. This holds even under the assumption that a rising number of current FA problems will be solved by modern testing techniques. Several strategies to reduce FA costs while keeping techniques state-of-the-art are presented. The most important approach is to integrate FA in semiconductor product and technology development and introduce it as part of their projects. Only in this way can F/A deliver custom-tailored solutions that are optimized in terms of productivity and time to result.

The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHIENIX detector at the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. The PHENIX detector is a large multi-component detector at the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Laboratory. PHENIX has over 400,000 channels of electronics, most of which is implemented using custom integrated circuits. We presently have responsibility for developing and manufacturing electronics for the event vertexfinding subsystem, the pads tracking subsystem, the electromagnetic calorimeter subsystem, and the muon tracking/identification subsystems. We have developed an architecture utilizing simultaneous read-write analog memories used throughout the detector that allows data to be continuously taken even during event readout (a deadtime-less system). The manufacturing technologies being used range from multi-layer printed-circuit boards to multi-layer, multi-chip modules (MCMs). The germanium spectrometer electronics for the Naval Research Laboratory consist of low-noise preamplifier-shapers-peak stretchers and discriminators. The preamplifiers have been optimized for detector capacitances of approximately 10 pF and shaping times of 5-10 .ts. This paper will present the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented. Keywords: Physics, electronics, CMOS

This report summarizes work on the development of ultra-low power microwave CHFET integrated circuit development. Power consumption of microwave circuits has been reduced by factors of 50--1,000 over commercially available circuits. Positive threshold field effect transistors (nJFETs and PHEMTs) have been used to design and fabricate microwave circuits with power levels of 1 milliwatt or less. 0.7 {micro}m gate nJFETs are suitable for both digital CHFET integrated circuits as well as low power microwave circuits. Both hybrid amplifiers and MMICs were demonstrated at the 1 mW level at 2.4 GHz. Advanced devices were also developed and characterized for even lower power levels. Amplifiers with 0.3 {micro}m JFETs were simulated with 8--10 dB gain down to power levels of 250 microwatts ({mu}W). However 0.25 {micro}m PHEMTs proved superior to the JFETs with amplifier gain of 8 dB at 217 MHz and 50 {mu}W power levels but they are not integrable with the digital CHFET technology.

The term interconnection has traditionally implied a ‘robust’ connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses ‘unimpeded’ transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC’s. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in ‘system-on-a-chip’ implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that ‘in-house’ chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC’s. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A ‘back-plane’ chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM’s.

The article presents the methodology of Integrated Product Development. Integrated Product Development offers a frame for structuring and integrating development acitivites and methods which are necessary for the development of complex industrial products. Conceptual Product Design is introduced and described as an essential part of Integrated Product Development in order to methodically support the development process. Conceptual Product Design aims to ensure the fulfilment of requirements, the basic workability, and the expected economic success as early as possible. Finally, information technology tools necessary to support Conceptual Product Design are explained.

This paper presents a methodology to incorporate hierarchy in the design verification process of large full custom digital CMOS circuits including the effects of statistical process variation and variation in external parameters like temperature and supply voltage. Behavioural models are used to describe sub-circuits on a high level of abstraction. Statistical tolerance information from the circuit level is mapped onto the behavioural models. By means of a case study on a large full custom design we show that this design verification methodology can be very efficient. >

Very large scale integrated circuits (VLSI) are growing in size, complexity, and circuit density at a very fast pace. There is no limit in the foreseeable future to the amount of intelligence architects would like to see on a single piece of silicon. Technology is keeping good pace with the growing demand of complete "systems" by increasing density. A few million transistors on one chip are already becoming common-place. The development of the architecture of such chips is, however, hampered by the lack of tools. This paper focuses on a very crucial issue, one of confidence in the internal architecture of a VLSI circuit before committing the design to silicon. The SES/Workbench by Scientific and Engineering Software has proven to be a useful tool in early architectural analysis of complex VLSI circuits. The circuit's system level architecture can be modelled fairly quickly to yield results that can save time, money, and resources to design optimum circuits with well understood performance characteristics, without taking recourse to fabricating the chip prototypes. The simulations on the resulting model "run" in reasonable time (million clocks/hr) to provide "on-line" feedback for fine tuning the design.

International audience; The authors introduce the motion of object-oriented design in the construction of circuit analysis software through a reflection on the basic objects and object classes of circuit analysis. Simple architectures of the three fundamental families of circuit analysis objects are given. With these fundamental families of classes, it is shown that it is as easy to build a frequency analysis of a linear circuit as to build a harmonic balance analysis of a nonlinear circuit. It is noted the object-oriented concept allows CAD (computer-aided design) tools to easily follow the state-of-the-art knowledge in circuit theory and to quickly respond to the increasing MMIC (monolithic microwave integrated circuit) design demand.

A practical methodology for the statistical design of complex, logic integrated circuit products is described. It virtually eliminates the overhead associated with statistical modeling by combining a fully automatic, computationally-efficient statistical circuit simulator and worst case simulation tools into a hierarchical design flow.

Characterization and subsequent corrective actions play an important role in complex integrated circuit development and manufacturing. Information on yield is an especially critical factor since it relates directly to manufacturing cost. In the early days of integrated circuit manufacturing, this type of information was obtained from the product itself through the use of visual inspection, microprobing and final testing. This approach was possible since the chip design was quite simple with large feature size and single level metallization, and the manufacturing cycle was very short. Decreasing feature size, increasing circuit density and very low defect density combine to make inspection with optical microscopes or SEM’s very time consuming. If a limited sample size is used in order to reduce inspection time, the results can also be misleading. Physical unlayering of the product after final test is still an important tool. Its feedback time, however, is considerably long since the manufacturing cycle can be greater than three months.

Recent developments in deep-submicron technology challenge current integrated circuit testing methods. The increasing complexity of designed systems makes test development more time-consuming. Moreover, nanometer technology introduces new defects or higher data rate errors. To reduce manufacturing costs and time to market, we must develop efficient fault detection and location methods. Using high-level fault simulation stimulates the development of new, fast test-generation algorithms that take into consideration functional features of the system under test or its components. Moreover, all synthesis tools migrate to higher levels, and we believe that this will improve ATPG tools as well.

The minimum feature size of CMOS technology will reach 10nm in ten years. Beyond that benchmark, the present scaling approach may have to take a different route. The grand challenge to integrated circuit design community is to identify alternative technologies, such as carbon-based electronics, integrate them into the circuit architecture, and enable continuous growth of chip scale and performance. Predictive Technology Model (PTM), which bridges the process development and circuit simulation through device modeling, is essential in assessing potentials and limits of new technology and in supporting early design prototyping.

This tutorial presents an overview of timing verification techniques which are used in the synthesis of IC layout. Issues which are covered include: delay estimation, transistor sizing, timing-driven placement and routing, circuit extraction, timing analysis and timing simulation. The role of each of these analysis techniques in the design flow is presented and numerous examples of associated CAD tools are described.

At various steps of integrated circuit manufacturing, defects need to be inspected to ensure process integrity. Based on the observation that good patterns usually repeat many times while defective patterns are different from others, we here propose an inspection methodology called dynamic self-inspection (DSI). We present a generic and systematic algorithm of DSI based on relative characteristic code space and code vectors. We also present a few specific examples of its implementations, using Euclidian distance between edge traces as relative characteristics.

The ability to clean advanced lithographic masks in a cost-effective manner is becoming increasingly important as the semiconductor industry continues integrated circuit development with ever-decreasing feature sizes. The plasma mechanical activation and extraction of particle contamination (PLASMAX) particle removal process, under development by Beta Squared, Inc., provides a means to achieve the industry’s needs for both the current optical and next-generation lithography (NGL) masks. This cleaning procedure is imperative since all NGL technologies are unable to use a conventional protective pellicle. The cleaning process implements a charged plasma flow in conjunction with mechanical excitation. This article presents the results of research to identify the optimal procedures to mechanically oscillate 6 in. fused silica reticles and electron-beam projection lithography masks. Using both numerical and experimental methods, the analysis characterizes the dynamic response of lithographic masks to quantify ...

The general problem of reducing data available in the integrated circuit environment is addressed. One can consider the circuit to be essentially composed of identification and performance data. Opportunities exist at every level of manufacturing and testing to aid in the final interpretation of the results. Without disturbing the technology or actual circuit design, some general methods for improving testing techniques are discussed. Examples of data reduction and presentation techniques are given where relation between performance and identification can be seen.

Recent advances in integrated circuit technology have involved process development, device, and circuit optimization under scaled design rules. It is advantageous to be able to simulate the overall circuit performance under different conditions. A simulator which performs this task at the logic gate level becomes important. This paper describes such a simulator for digital bipolar integrated circuit families: WATPAC. WATPAC uses the process simulator SUPREM, the device simulator BIPOLE, and the circuit simulator WATAND. The input parameters to WATPAC are entered interactively. These consist of fabrication process parameters, layout design rules, a specification of the logic family, and a WATPAC predefined logic function. The WATPAC output consists of overall circuit performance data for the simulated function block. The output of WATPAC also includes the intermediate outputs of the process simulator, device simulator, and the circuit simulator.

An approach to design is described which allows the designer to statistically analyze a circuit's output characteristics. The results of this analysis give the designer the ability to reduce the sensitivity and to optimize these output characteristics with respect to process, package, and environmental variations. In addition, the authors demonstrate the means by which to establish output specifications before time and money are invested in fabricating devices in silicon. Finally, examples of the successful application of this technique to the design and development of an ECL (emitter-coupled logic) family are discussed. The methods for applying the results from this statistical technique to manufacturing and testing are also shown. >

A general and practical method for design rule optimization (i.e. IC cost minimization) is presented, and then demonstrated in detail for specific examples. The optimum design rules are shown to be insensitive to chip area or defect density, but strongly dependent on tolerance sizes, number of masking levels, and to a parameter which will be defined as the `area overhead factor'. Throughout the development, limitations and assumptions are thoroughly discussed, with the overall result that the method is shown to be immediately useful for arbitrary, but well characterized, fabrication processes and lithography equipment.

The artwork of integrated circuit designs is usually available in the form of hierarchical specification, in which each cell is made up of geometric primitives and references to other cells. Such a representation captures structure and repetition in the layout. As the realizable device count of integrated circuits increases with every passing year there is an increasing trend towards structured design approaches that result in even greater degrees of regularity and hierarchy. Yet the typical approach to design verification requires fully instantiating the hierarchical representation thereby removing all structure from it. Consequently much time is spent repeating the analyses of identical cells. This paper presents a general approach to exploiting hierarchy and repetition in the analysis of integrated circuit designs, and includes details of a circuit extraction algorithm that uses this approach. The implementation and performance of such a system is also described.

X-ray lithography is a technology which has been waiting for a problem to solve that is tougher than its own problems. Development of X-ray lithography dates from the early 1970's [1]--[3] and since that time, improvements in resolution of optical and near UV projection aligners and step-and-repeat systems have kept pace with processing ability for fabrication of smaller components in silicon integrated circuits (IC's). However, 1 µm or smaller features are now a design requirement for semiconductor integrated circuits (SIC's) which will have a significant performance advantage over current manufacture [4], [5]. In addition practical means for fabricating high quality X-ray masks have been found [6] along with sensitive resists and resist systems which are designed for reactive ion etching (RIE) processes [7], [8]. Reliable, economical, and long-lived X-ray sources have also been developed, [9], thus enabling us to design and build X-ray exposure tools for SIC and other fabrication. In this paper the X-ray lithography system developed at Bell Laboratories will be described along with evaluation of its use in a laboratory SIC fabrication facility. Projections for future developments in X-ray lithography will be given.