461 results on '"Kuroda, Tadahiro"'
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152. A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS
153. A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface
154. A low power, area efficient frequency acquisition circuit with array oscillator for pulse-based inductive-coupling transceiver
155. 1.2 nJ/classification 2.4 mm2asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18 µm CMOS
156. Adaptive window search using semantic texton forests for real-time object detection
157. Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links
158. A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface
159. A 0.7V intermittently operating LNA with optimal on-time controller for pulse-based inductive-coupling transceiver
160. A 3 Gbps Non-Contact Inter-Module Link with Twofold Transmission Line Couplers and Low Frequency Compensation Equalizer
161. A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines
162. Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications
163. A 4-10bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS with Wide Supply Voltage Range SAR Controller
164. An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40nm CMOS
165. Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs
166. A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA
167. Symbol-Rate Clock Recovery for Integrating DFE Receivers
168. An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories.
169. A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating
170. Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect
171. A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS
172. 1-W 3.3–16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller
173. Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication
174. A 0.025–0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards
175. Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card
176. Low-latency wireless 3D NoCs via randomized shortcut chips.
177. An 8bit 0.35–0.8V 0.5–30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator
178. A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS
179. A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers
180. CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect
181. A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration
182. A 1 TB/s 1 pJ/b 6.4 ${\rm mm}^{2}/{\rm TB/s}$ QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM
183. Near-field wireless connection for 3D-system integration
184. Wearable sensor-based human activity recognition from environmental background sounds
185. A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS
186. A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS
187. A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors
188. Session 23 overview: Advances in heterogeneous integration: Technology directions subcommittee
189. A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme
190. Asynchronous Pulse Transmitter for Power Reduction in Inductive-Coupling Link
191. A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line
192. A 9-bit 100MS/s SAR ADC with Digitally Assisted Background Calibration
193. 3D Jisso Technology Opened-up by Near-Field Wireless Communications
194. A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS
195. 6W/25mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing
196. Proximity IOs using inductive coupling
197. 1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller
198. A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators
199. Hybrid Speaker Recognition Using Universal Acoustic Model
200. A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface
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