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Network-on-Chip (NoC) is emerging as a promising communication paradigm to overcome bottleneck of traditional bus-based interconnects for future micro-architectures (MPSoC and CMP). One of current issue in NoC routing is the use of acyclic channel dependency graph (ACDG) for deadlock freedom prohibiting certain routing turns. Thus, ACDG reduces the degree of adaptiveness. In this paper, we propose a novel nonminimal turn model which allows cycles in channel dependency graph provided that extended channel dependency graph is acyclic. Proposed turn model reduces number of restrictions on routing turns (specially on 90-degree), hence able to provide additional minimal and non-minimal routes between source and destination. We also propose a non-minimal and congestion-aware adaptive routing algorithm based on proposed turn model to demonstrate advantages. From results, we can observe that proposed method improves the network performance by distributing the traffic load in the non-congested regions.

In this paper, we propose a novel highly adaptive and congestion aware routing algorithm 3D meshes which is equally applicable to 2D meshes as well. The proposed algorithm allows cyclic dependencies in channel dependency graph (CDG) providing higher degree of adaptiveness. The algorithm uses congestion-aware channel selection strategy that results balanced distribution of traffic flows across the network. A packet follows non-minimal paths only when minimal paths are congested at the neighboring channels. The deadlock avoidance methodology adopted by our algorithm remains cost-efficient as it uses one extra virtual channel along each of Y and Z dimensions to achieve deadlock freedom.

Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs {causing delay failures and reliability-related concerns}. The widespread utilization of multiple supply voltages in contemporary VLSI designs and {emerging test methods} poses a critical concern as to whether conventional models for resistive opens will still be effective. Conventional models do not explicitly model the $V_{DD}$ effect on fault behavior and detectability. We have empirically observed that a sensitized ROF could exhibit multiple behaviors across its resistance continuum. We also observed that the detectable resistance range versus $V_{DD}$ varies with test speed. We consequently propose a voltage-aware model which divides the full range of open resistances ($RO$) into continuous behavioral intervals and three detectability ranges.The presented model is expected to substantially enhance multi-voltage test generation and fault distinction

Network-on-Chip (NoC) has emerged as a long-term and efficient on-chip communication solution for MCSoC and CMP micro-architectures to overcome bottleneck of traditional bus-based interconnects. Performance of NoC is highly dependent on routing algorithm we choose. In this paper, we present a highly adaptive and deadlock free routing algorithm for 2D mesh topology to mitigate congestion. Proposed algorithm provides a high degree of adaptive ness by allowing cycles in channel dependency graph and using one additional virtual channel along the Y dimension only. It uses all available minimal/non-minimal paths between source and destination nodes. A packet is routed along the non-minimal path only when minimal paths get congested at the neighboring nodes. Results show that proposed congestion-aware routing algorithm improves network performance by routing packets through non-congested areas.

A technique is described for the automatic insertion of fault models into VHDL gate models, using shared variables and linked lists. This procedure does not require any modification to the structural description of a circuit using these models. A method for automatic sequential fault simulation is further demonstrated.

Many pattern recognition systems need to estimate an underlying probability density function (pdf). Mixture models are commonly used for this purpose in which an underlying pdf is estimated by a finite mixing of distributions. The basic computational element of a density mixture model is a component with a nonlinear mapping function, which takes part in mixing. Selecting an optimal set of components for mixture models is important to ensure an efficient and accurate estimate of an underlying pdf. Previous work has commonly estimated an underlying pdf based on the information contained in patterns. In this paper, mutual information theory is employed to measure whether two components are statistically dependent. If a component has small mutual information, it is statistically independent of the other components. Hence, that component makes a significant contribution to the system pdf and should not be removed. However, if a particular component has large mutual information, it is unlikely to be statistically independent of the other components and may be removed without significant damage to the estimated pdf. Continuing to remove components with large and positive mutual information will give a density mixture model with an optimal structure, which is very close to the true pdf.

To assess the effectiveness of a testing strategy for an integrated circuit, the potential structural faults in a circuit must be modelled. Analogue fault simulation is conventionally done at the transistor level. Behavioural fault models are desirable to speed up the simulations. Behavioural fault modelling needs faults to be grouped. However, it is not easy to group faults using a Euclidean measurement of the distance between faults, if the populations of the circuit faults have distributions with differing variances. Mutual information theory is suggested here as a robust method for clustering circuit faults. The bootstrap technique is proposed to speed up the process of generating statistical data. Statistical data on the performance of circuits under fault conditions is generated using HSPICE. A software program has been written to implement clustering of responses using mutual information theory and to generate statistical data using bootstrap. The technique is shown to generate a suitable set of parameters for a regression function. The simulation results for the behavioural models are close to those of the full circuit model. Mutual information theory is a useful technique for clustering responses of circuits under fault conditions.

The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques such as neural networks have been employed to automate classification. The major drawback to such techniques has been the implicit assumption that the variances of the responses of faulty circuits have been the same as each other and the same as that of the fault-free circuit. This assumption can be shown to be false. Neural networks, moreover, have proved to be slow. This paper describes a new neural network structure that clusters responses assuming different means and variances. Sophisticated statistical techniques are employed to handle situations where the variance tends to zero, such as happens with a fault that causes a response to be stuck at a supply rail. Two example circuits are used to show that this technique is significantly more accurate than other classification methods. A set of responses can be classified in the order of 1 s.

Recent years have seen rapid progress in using digital microfluidics based biochips for biomedical assays. The testing and reliability of these biochips is crucial when they are used in point-of-care diagnostics applications. As the scalability and complexity of biomedical assays increases, there is a need for efficient testing methodologies to ensure reliability of these biochips. The conventional testing methodologies will not be sufficient for the recently proposed and highly scalable Micro-electrode-dot array (MEDA) architecture based digital microfluidics. This is because of the advanced fluidic movement operations incorporated in the MEDA architecture. This paper investigates the testing methodologies for conventional digital microfluidics based biochips and their relevancy to the MEDA architecture based digital microfluidics biochips.

This paper proposes a method to recast the classic circuit simulation algorithm to maximize parallelism by formulating the circuit equations as state variable equations and using an integration method such as Runge Kutta as the foundation to break the time dependencies. A brief introduction to the SPICE algorithm and previous attempts to exploit parallelism is given. The implementation of the new algorithm for both linear and non-linear circuits is presented and results are compared with the traditional method. The opportunities for extracting parallelism are discussed.

The power and energy consumed by a chip have become primary design constraints for embedded systems and are largely affected by software. However, there is a gap between software and hardware that makes it hard to predict which code consumes the least power before running it. Therefore, it is vital to discover which factors affect a program's energy consumption. In this paper we present an instruction-level power model for a single core, in-order RISC processor architecture. We do not analyze each instruction individually, but we study the average power and running time instead. We find the power in a processor is nearly constant, no matter what instructions are run, but the IO port power is related to the behavior of the program. Furthermore, we provide a model that takes the cache miss rate into consideration.

Process variation has an increasingly dramatic effect on delay and power as process geometries shrink. Even if the amount of variation remains the same as in previous generations, it accounts for a greater percentage of process geometries as they get smaller. So an accurate prediction of path delay and power variability for real digital circuits in the current technologies is very important; however, its main drawback is the high runtime cost. In this paper, we present a new fast EDA tool which accelerates Monte Carlo based statistical static timing analysis (SSTA) for complex digital circuit. Parallel platforms like Message Passing Interface and POSIX® Threads and also the GPU-based CUDA platform suggests a natural fit for this analysis. So using these platforms, Monte Carlo based SSTA for complex digital circuits at 32, 45 and 65 nm has been performed. and of the pin-to-output delay and power distributions for all basic gates are extracted using a memory lookup from Hspice and then the results are extended to the complex digital circuit in a hierarchal manner on the parallel platforms. Results show that the GPU-based platform has the highest performance (speedup of 19×). The correctness of the Monte Carlo based SSTA implemented on a GPU has been verified by comparing its results with a CPU based implementation.

We have newly introduced the expert designer/user session (EDS) to ISPD in 2013, which is tailor-made for designers and users of physical design (PD) tools. Since ISPD is the premium PD-centric symposium, it is a great opportunity for designers, tools developers and PD researchers to interact and learn from each other. The benefit of including EDS in ISPD's program is twofold.(1) It provides a focus session and friendly environment, which stimulates technical discussion among industry and academia. Experienced PD users would have a chance to get exposed to the detail of the latest state-ofthe- art research in the field of physical design.(2) The session brings in designers experience of PD tools, which includes opportunities and challenges from users' prospective. This would directly drive the PD research direction in the future, and tighten the bond between users, researchers and developers in the PD community. In turn, it eventually helps improving the PD tools from EDA vendors.In this Expert Designer Session (EDS), we carefully selected and invited a list of six expert designers/users around the world to present their on-hand design and tool experience.The topics covered include tree-mesh clock distribution, large block placement, place-and-route for custom designs, layout dependent effects, metal-based ECO, and clock aware timing closure flow.The format of EDS consists of an oral presentation session, immediately followed by a poster session. This encourages deep discussion and professional networking between PD users, researchers and developers.

Conventionally, the decoding energy consumption Epr of turbo codes were not a significant contribution to the overall energy consumption of a system, since the popular applications of turbo codes were focused on long-range communication systems, such as mobile phone networks or deep space communications. However, with advances in IC fabrication, sophisticated Error-Correcting Codes (ECCs), such as turbo codes, may be embedded into low-cost Wireless Sensor Networks (WSNs). In this paper, it is demonstrated that to design a turbo code for WSNs, the processing energy must be considered as an important factor during the early design stage. However, conventionally, the processing energy has not been considered in the design process, since no technique has been available for estimating it using conventional designs. Hence, we proposed a processing energy estimation framework for minimising the overall energy consumption of a turbo coded scheme at the code design stage.

In this paper we demonstrate a dynamical system simulator that runs on a single GPU. The model (running on an NVIDIA GT325M with 1GB of memory) is up to 50 times faster than a CPU version when more than 10 million adaptive Hopf oscillators have been simulated. The simulation shows that the oscillators tune to the correct frequencies for both discrete and continuous spectra. Due to its dynamic nature the system is also capable to track non-stationary spectra. With the help of this model the frequency spectrum of an ECG signal (as a non-stationary signal) obtained and was showed that frequency domain representation of signal (i.e. FFT) is the same as one MATLAB generates.

Variability in performance and power of 40nm and 28nm CMOS cells is highly dependent on the context in which the cells are used. In this study, the effects of context on a number of clock tree cells from standard cell libraries have been investigated. The study also demonstrated how the Litho Electrical Analyzer (LEA) tool from Cadence® is used to analyze the context-dependent variability. During the study, it was observed that the device characteristics including Vth, Idsat, and Ioff are significantly affected by Layout Dependent Effects (LDE), resulting in variability of performance and power of standard cells. Moreover, the dummy diffusions acting as mitigation process offered limited improvement for the effects of context. On the other hand, the cell level variability due to stress was analyzed. So, it is suggested that the relative variability of a cell is determined by its size and structure, and the variability can be improved to some extent by editing the cells' structure. Based on the analysis of the physical sources and properties of LDE, this paper presents a set of layout guidelines for mitigating layout dependent variability of 40 and 28nm CMOS cells.

Packet filtering is core functionality in many academic and corporate network systems. Firewalls use a rule database to decide which packets will be allowed from one network onto another thereby implementing a security policy. With the introduction of new types of services and applications there is a growing demand for larger bandwidth and also for improved security. Both demands are in conflict since providing security partly relies on screening packet traffic, which implies a considerable overhead. In such a scenario as LAN and WAN speeds are becoming comparable, a single firewall can become a bottleneck and reduces the overall throughput of the network. A firewall with heavy load and limited processing power, which is supposed to be a first line of defence against attacks, becomes susceptible to Denial of Service (DoS) attacks. Many research groups have proposed different methods to improve efficiency and throughput to optimize firewalls. This paper presents and analyse various parallel implementations of packet filtering running on cost effective GPGPU. We describe an approach to efficiently exploit the massively parallel capabilities of the GPGPU.

In this paper, a new VLSI implementable Hopf oscillator with dynamic plasticity is proposed for next-generation portable signal processing application. A circuit-realizable piece-wise linear function has been used to govern the frequency adaptation characteristic of the proposed oscillator. Furthermore, a straightforward method is suggested to extract the frequency component of the input signal. Mathematical model of the oscillator is derived and it is shown, using VHDL-AMS model, that despite using a new nonlinear function, the oscillator exhibits the same characteristics and learning behavior as the original one with improved learning time. Subsequently, an equivalent circuit model and transistor level implementation for the oscillator is suggested and the mathematical model is confirmed with system and circuit level simulations. Capability of such oscillator to extract frequency futures without doing explicit signal processing is shown with examples of both synthetic and real-life EMG signals.

Soft errors induced by radiation, causing malfunctions in electronic systems and circuits, have become one of the most challenging issues that impact the reliability of the modern processors even in sea-level applications. In this paper we present two novel radiation-hardening techniques at Gate-level. We present a Single-Event-Upset (SEU) tolerant Flip-Flop design with 38% less power overhead and 25% less area overhead at 65nm technology comparing to the conventional Triple Modular Redundancy (TMR) for Flip-Flop design. We also present an SEU-tolerant Clock-Gating scheme with less than 50% area-power overheads and no performance penalty comparing to the conventional TMR for clock-gating. Our simulations show that the proposed schemes can recover from SEU errors in 99% of the cases.

Soft errors are a significant reliability issue for Ultra Deep-Sub-Micron (UDSM) CMOS circuits. Therefore, an accurate assessment of the Soft Error Rate (SER) is crucial. In this paper, we argue that the conventional definitions for the Window of Vulnerability (WOV) under-estimate the risk. We propose a new method for determining the timing factors and WOV for the sequential elements from the susceptibility perspective rather than the conventional performance perspective. We also discuss that the process variation does not have any special impact on the WOV. Our methodology leads to a more realistic definition of the WOV for SER computation.

The scaling of MOSFETs has improved performance and lowered the cost per function of CMOS integrated circuits and systems over the last 40 years, but devices are subject to increasing amounts of statistical variability within the deca-nano domain. The causes of these statistical variations and their effects on device performance have been extensively studied, but there have been few systematic studies of their impact on circuit performance. This paper describes a method for modelling the impact of random intra-die statistical variations on digital circuit timing and power consumption. The method allows the variation modelled by large-scale statistical transistor simulations to be propagated up the design flow to the circuit level, by making use of commercial STA and standard cell characterisation tools. The method provides circuit designers with the information required to analyse power, performance and yield trade-offs when fabricating a design, while removing the large levels of pessimism generated by traditional Corner Based Analysis.

Logic simulation of a VLSI chip is a computationally intensive process. There exists an urgent need to map functional validation algorithms onto parallel architectures to aid hardware designers in meeting time-to-market constraints. In this paper, we propose three novel methods for logic simulation of combinational circuits on GPGPUs. Initial experiments run on two methods using benchmark circuits using NVIDIA GPGPUs suggest that these methods can be used for accelerating the EDA design flow process.

Smart cards are an example of advanced chip technology. They allow information transfer between the card holder and the system over secure networks, but they contain sensitive data related to both the card holder and the system, that has to be kept private and confidential. The objective of this work is to create an executable model of a smart card system, including the security protocols and transactions, and to examine the strengths and determine the weaknesses by running tests on the model. The security objectives have to be considered during the early stages of systems development and design, an executable model will give the designer the advantage of exploring the vulnerabilities early, and therefore enhancing the system security. The Unified Modeling Language (UML) 2.0 is used to model the smart card security protocol. The executable model is programmed in SystemC with the Transaction Level Modeling (TLM) extensions. The final model was used to examine the effectiveness of a number of authentication mechanisms with different probabilities of failure. In addition, a number of probable attacks on the current security protocol were modeled to examine the vulnerabilities. The executable model shows that the smart card system security protocols and transactions need further improvement to withstand different types of security attacks.

SpiNNaker (Spiking Neural Network architecture) is a massively parallel computing machine, comprising a million ARM9 cores. These are realised on 50000 chips, 20 cores/chip. While it could be classed as a MIMD machine, there is no unifying bus structure, and there is no attempt to maintain cross-system memory coherence. Inter-core communication is brokered by a fast message-passing system, built in and managed at the hardware level - thus there is an inevitable tension between speed and flexibility.The message passing infrastructure was designed to be fast and have a high bandwidth; a consequence of this design decision is that the effective data payload is only 32 bits/packet. Whilst this is ample for a wide range of applications, when the system is initialising, it is necessary to transport relatively large and sophisticated data structures across the system. This can be slow and cumbersome, and makes some form of internal self-organisation extremely attractive. This is described in outline here.

The Izhikevich neuron model reproduces the spiking and bursting behaviour of certain types of cortical neurons. This model has a second order non-linearity that makes it difficult to implement in hardware. We propose a simplified version of the model that has a piecewise-linear relationship. This modification simplifies the hardware implementation but demonstrates similar dynamic behaviour.

Circuit-level simulation is a computationally-intensive problem that has proven to be particularly difficult to parallelize. While device evaluation can be performed in parallel in conventional circuit simulators, the execution overhead is high. We show that, by partitioning a circuit, OpenMP can be used to solve sub-circuits in different threads, without compromising accuracy. It is shown that execution time can be reduced proportionally to the number of threads.

A program for the generation of Weinberger arrays from Boolean expressions is described. To minimize the area required to implement a function, an array may be folded. A new algorithm is presented that further minimizes the area by causing transistors from adjacent rows to be interleaved. The interleaving process allows area reductions beyond the folding limit, and it can be included in the optimization process either as an additional task after folding, as in the paper, or, alternatively, during folding.

Mixed-mode simulation is a compromise between an accurate and expensive modelling technique (that solves circuit equations), and a less accurate, but cheaper, technique (that manipulates a finite algebra). The combination of these modelling regimes requires a mapping between two ‘state vectors’ that is neither unique nor context-independent. To address this, a duple, {state, confidence} , is associated with each node at each timepoint. Confidence is a set of flags that is used to indicate that the simulator has made a decision with which the user may be unhappy. Graphical postprocessing allows the user to scan for combinations of flags. This creates a ‘flag-browsing’ capability that allows rapid access to areas of uncertainty in the time histories.

This paper presents a novel structure for the adaptive frequency Hopf oscillator where the nonlinear function is modified to make the system realizable using analog circuit components. A mathematical model is derived and it is shown using VHDL-AMS model that despite using a new nonlinear function, the oscillator exhibits the same characteristics as the original. Our simulation results show the same learning behavior with improved learning time. Subsequently, an equivalent circuit model and transistor level implementation for the oscillator is suggested and the mathematical model is confirmed with system and circuit level simulations.

This paper presents a new analytical propagation delay model for nanoscale CMOS inverters. By using a non-saturation current model, the analytical input-output transfer responses and propagation delay model are derived. The model is used for calculating inverter delays for different input transition times, load capacitances and supply voltages. Delays predicted by the proposed model are in good agreement with those of transistor level simulation results from SPICE, with accuracy of 3% or better.

Channel random discrete doping (RDD), one of the main sources of MOSFET intrinsic parameter fluctuations, significantly affects the stability of CMOS SRAM. This paper describes a behavioural model for 35 nm CMOS technology SRAM cells with random discrete dopants using VHDL-AMS (Analogue and Mixed Signal). The static transfer characteristic (STC) is described in the VHDL-AMS model. Monte Carlo simulation results of the behavioural model are close to those at SPICE level. The VHDL-AMS model can predict the worst case STC behaviour for SRAM induced by RDD but also improves the simulation speed by five times compared to SPICE.

With the growing density of very large scale integrated (VLSI) circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The trade off between accurate simulations at transistor level, as in SPICE and fast simulation at gate level using a Hardware Descriptive Language (HDL) can be achieved by using behavioural modelling languages such as VHDL-AMS. In this paper, we have demonstrated that behavioural fault simulation for resistive faults can produce fast and accurate results.

Estimation of asynchronous circuit performances, such as speed, is one of the major issues that make that design style still less popular than it deserves to be. Evaluating the worst case delays in the paths of an asynchronous circuit using a simple logic simulator would be very useful in overcoming this problem. In this paper a method for timing analysis of the asynchronous non-sequential circuits using a VHDL simulator is presented. With an appropriate extension of the standard logic simulation process, all worst case delays for all paths in a digital circuit with only one run of the simulation can be obtained. High levels of accuracy are achieved using different gate modelling and statistical analysis of the results. Due to the lack of asynchronous benchmark circuits, the method is verified on a set of asynchronous circuit selected by the authors.

Dual Rail Precharge circuits offer an effective way to address Differential Power Analysis Attacks, provided routing of differential signals is fully balanced. Fat Wire [1] and Backend Duplication [2] methods address this problem. However they do not consider the effect of coupling capacitance on adjacent differential signals. In this paper we propose a new method, Divided Backend Duplication, which is based on Divided Wave Dynamic Differential Logic [3] and Backend Duplication [2], that effectively addresses balanced routing problem of Dual Rail Precharge circuits. Experimental results on an AES test circuit in 130nm technology show improvements in achieving a balanced dual rail design. Further our method can also be successfully applied to FPGAs. Results from an sbox test circuit implementation on a Xilinx FPGA are presented.

The negative bias temperature instability (NBTI) of p-MOSFET has the greatest impact on the long term reliability of nano-scale devices and circuits. For several decades, NBTI research has been focused at the device physics level or on the characterization methodology, with little attention paid to the impact of NBTI on the performance of basic digital circuits. This paper discusses the effects of NBTI on 35 nm technology CMOS inverters and SRAM. The delay degradation and power dissipation of the inverters, as well as the static noise margin degradation of the SRAM are analysed. Moreover, the effects of power supply voltage on inverters and the cell ratio on SRAM under NBTI are also discussed.

The Lee routing algorithm is one of the earliest routing algorithms, and has been widely used and analysed for most aspects of automated wiring. The paper contains details of yet another modification to the basic algorithm that attempts to keep the average wiring density even over a large chip. Despite the large amount that has been published on the Lee algorithm, this particular adaptation has not been reported before. It is shown that the modification described can decrease the standard deviation of the channel wiring density by 25%.

The use of multiple voltages for different cores is becoming a widely accepted technique for efficient power management. Level shifters are used as interfaces between voltage domains. Through extensive transistor level simulations of resistive open, bridging and resistive short faults, we have classified the testing of level shifters into PASSIVE and ACTIVE modes. We examine if high test coverage can be achieved in the PASSIVE mode. We consider resistive opens and shorts and show that, for testing purposes, consideration of purely digital fault effects is sufficient. Thus conventional digital DfT can be employed to test level shifters. In all cases, we conclude that using sets of single supply voltages for testing is sufficient.

This paper addresses the problem of choosing different word-lengths for each functional unit in fixed-point implementations of DSP algorithms. A symbolic-noise analysis method is introduced for high-level synthesis of DSP algorithms in digital hardware, together with a vector evaluated genetic algorithm for multiple objective optimization. The ability of this method to combine word-length optimization with high-level synthesis parameters and costs to minimize the over all design cost is demonstrated by example designs.

Differential power analysis (DPA) attack is a major concern for secure embedded devices (Ravi et al., 2004)-(Ors et al., 2004). Currently proposed countermeasures (Pramstaller, 2005)-(Tin and Verbauwhede, 2004) to prevent DPA imposes significant area, power and performance overheads. In addition they either require special standard cell library and design flows or algorithmic modifications. Recently, random dynamic voltage and frequency scaling (RDVFS) has been proposed (Yang et al., 2005) as a DPA countermeasure, which has less area, power and performance overheads and it does not require special cell library nor design flows nor algorithmic modifications. However, in a synchronous digital circuit, the operating frequency can be detected by monitoring glitches on the power line. In this paper, the authors show that using this information, it is possible to mount a DPA attack on circuits employing RDVFS countermeasure. The authors propose an alternative technique which only varies the supply voltage randomly. Experimental results on AES core with SPICE level simulations show that our proposed method significantly weakens the DPA attack by reducing the correlation of power to processed data.

Differential Power Analysis (DPA) presents a major challenge to mathematically-secure cryptographic protocols. Attackers can break the encryption by measuring the energy consumed in the working digital circuit. To prevent this type of attack, this paper proposes the use of reversible logic for designing the ALU of a cryptosystem. Ideally, reversible circuits dissipate zero energy. Thus, it would be of great significance to apply reversible logic to designing secure cryptosystems. As far as is known, this is the first attempt to apply reversible logic to developing secure cryptosystems. In a prototype of a reversible ALU for a crypto-processor, reversible designs of adders and Montgomery multipliers are presented. The reversible designs of a carry propagate adder, four-to-two and five-to-two carry save adders are presented using a reversible TSG gate. One of the important properties of the TSG gate is that it can work singly as a reversible full adder. In order to design the reversible Montgomery multiplier, novel reversible sequential circuits are also proposed which are integrated with the proposed adders to design a reversible modulo multiplier. It is intended that this paper will provide a starting point for developing cryptosystems secure against DPA attacks., Comment: Published in the proceedings of the The 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2006), Puerto Rico, August 2006. Nominated for the Student Paper Award

In this paper artificial neural networks (ANNs) are applied to diagnosis of catastrophic defects in the digital part of a nonlinear mixed-mode circuit. The approach is demonstrated on the example of a relatively complex sigma-delta modulator. A set of faults is selected first. Then, fault dictionary is created, by simulation, using the response of the circuit to an input ramp signal. It is represented in a form of a look-up table. Artificial neural network is then trained for modeling (memorizing) the look-up table. The diagnosis is performed so that the ANN is excited by faulty responses in order to present the fault codes at its output. There were no errors in identifying the faults during diagnosis

The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover.

The word-length of functional units (FU) has a great impact on design costs. This paper addresses the problem of choosing different word-lengths for each FU while considering circuit area and power consumption. A high-level synthesis tool is used to minimize the circuit area and power consumption by selecting an optimal word-length for each FU in the system. Our results demonstrate that by customizing word lengths to non-standard sizes, savings can be made in the overall area and power without losing accuracy

The design of Micro-Electrical-Mechanical Systems requires that the entire system can be modelled and simulated. Additionally, behaviour under fault conditions must be simulated to determine test and diagnosis strategies. While the electrical parts of a system can be modelled at transistor, gate or behavioural levels, the mechanical parts are conventionally modelled in terms of partial differential equations (PDEs). Mixed-signal electrical simulations are possible, using e.g. VHDL-AMS, but simulations that include PDEs are prohibitively expensive. Here, we show that complex PDEs can be replaced by black-box functional models and, importantly, such models can be characterized automatically and rapidly using artificial neural networks (ANNs). We demonstrate a significant increase in simulation speed and show that test and diagnosis strategies can be derived using such models.

New concepts of simulation, testing and diagnosis of MEMS are proposed, intended to boost the time to market and dependability of such systems. Black-box modeling of nonelectronic parts is introduced using artificial neural networks, so enabling radically faster simulation without concurrent algorithms and parallel computation. A lumped model of the capacitive transducer, being the part of a micro-electro-mechanical capacitive pressure sensing system, is created using an ANN. Faults are then introduced to the sensing system and simulation of the fault-free and faulty circuits are demonstrated.

The synthesis of a hardware implementation of a Viterbi decoder from a behavioural specification is discussed. This is applied to a parallelized version of a BCH decoder. A parameterizable high-level VHDL model of the parallel decoder has been developed. Scalability of the parallel decoder in hardware is demonstrated. An extension of this technique to an adaptive decoder is discussed.

In this paper we propose a platform for high level synthesis of DSP algorithms while emphasising the differences between DSP systems and other digital systems. Accordingly, we allow variable word lengths within the system in order to optimize the system digital noise versus area. Using particular target architecture, a suitable cost function, together with a synthesiser and optimizer and intermediate data bases have been implemented. Optimization is based on a genetic algorithm. (6 pages)

Analogue fault simulation is needed to evaluate the quality of tests, but is very computationally intensive. Behavioural simulation is more abstract and thus faster than fault simulation. Using a phase-locked loop as a case study, we show how behavioural fault models can be derived from transistor-level fault simulations and that faulty behaviour can be accurately modeled.

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.