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484 results on '"Ortmanns, Maurits"'

159. A 0.4-V $G_{m}$ – $C$ Proportional-Integrator-Based Continuous-Time $\Delta\Sigma$ Modulator With 50-kHz BW and 74.4-dB SNDR.

Author

Lv, Lishan, Jain, Ankesh, Zhou, Xiong, Becker, Joachim, Li, Qiang, and Ortmanns, Maurits

Subjects
CONTINUOUS time systems, FINITE impulse response filters
Abstract

This paper presents a $G_{m}$ – $C$ -based $\Delta \Sigma $ modulator under 0.4-V supply. A 3rd-order continuous-time $\Delta \Sigma $ modulator is proposed by cascading three $G_{m}$ – $C$ proportional integra- tors (PIs) with a feedforward resistor for the proportional path, which minimizes the output swing of each integrator and ensures that the last two transconductors operate within their linear input range. A nine-tap finite-impulse response (FIR) digital to analog converter (DAC) in front of the first $G_{m}$ – $C$ integrator filters the large out-of-band quantization noise from the feedback signal, generating a quiet input of the first transconductor for better linearity. A feedback bias control technique is proposed to achieve a stable transconductance of the $G_{m}$ cells under low supply voltages. The proposed $\Delta \Sigma $ modulator is fabricated in a 90-nm CMOS and achieves 74.4-dB peak signal-to-noise and distortion ratio (SNDR), 85.2-dB peak spurious free dynamic range (SFDR), and 78.5-dB dynamic range (DR) within a 50-kHz bandwidth, which is the first demonstration of $G_{m}$ – $C$ -based modulators under near-threshold supply voltages. The FoMw is 61.2 fJ/conversion-step, and FoMs is 167 dB, outperforming the reported low-voltage $\Delta \Sigma $ modulator designs. [ABSTRACT FROM AUTHOR]

Published
2018
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172. A 0.1% THD, 1-M $\Omega$ to 1-G $\Omega$ Tunable, Temperature-Compensated Transimpedance Amplifier Using a Multi-Element Pseudo-Resistor.

Author

Djekic, Denis, Fantner, Georg, Lips, Klaus, Ortmanns, Maurits, and Anders, Jens

Subjects
ELECTRIC impedance, ELECTRONIC amplifiers, ELECTRIC resistors
Abstract

In this paper, a transimpedance amplifier (TIA) is presented that utilizes a modified pseudo-resistor (PR) with improved robustness against temperature and process variations, enhanced linearity, and reduced parasitics. Using a biasing scheme named pseudo current mirror, the conventional dependence on absolute process parameters is reduced to a dependence on matching of alike devices. The linearity and noise performance as well as the immunity against process variations of the presented TIA are improved by the series connection of multiple PR elements. Moreover, it is shown how implementing the design in a silicon-on-insulator (SOI) technology reduces critical parasitics, which in turn enables the use of the multi-element PR in high-speed, high-gain, and low-distortion TIAs. A prototype realization in a 180-nm CMOS SOI technology achieves a tunability in transimpedance of three orders of magnitude from ${1}~{\mathrm {G}\Omega }$ down to ${1}~{\mathrm {M}\Omega }$ with corresponding bandwidths from ${8}~{\mathrm {kHz}}$ to 2 MHz. By design, the contribution of shot noise is rendered negligible and the white noise floor of the prototype realization approaches the theoretical thermal noise limit, e.g., ${5.5}~{\mathrm {fA}/\sqrt {\mathrm {Hz}}}$ for a transimpedance of ${1}~{\mathrm {G}\Omega }$ and ${140}~{\mathrm {fA}/\sqrt {\mathrm {Hz}}}$ for ${1}~{\mathrm {M}\Omega }$. Total harmonic distortion values of less than 0.1% are achieved for an input amplitude of ${300}\,\,{\mathrm {pA}_{\mathrm {p{-}p}}}$ for ${1}~{\mathrm {G}\Omega }$ , ${4.0}\,\,{\mathrm {nA}_{\mathrm {p{-}p}}}$ for ${100}~{\mathrm {M}\Omega }$ , and ${40}\,\,{\mathrm {nA}_{\mathrm {p{-}p}}}$ for ${10}~{\mathrm {M}\Omega }$ , and less than 1% is achieved for an input amplitude of ${550}\,\,{\mathrm {nA}_{\mathrm {p{-}p}}}$ for ${1}~{\mathrm {M}\Omega }$. The presented TIA consumes an area of 0.07 mm2 and dissipates a power of 9.3 mW for the opamp and a maximum power of 0.2 mW for the PR from a 1.8-V supply. [ABSTRACT FROM AUTHOR]

Published
2018
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