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In this paper, we present a performance-oriented implementation flow for WCHB QDI asynchronous circuits aiming to be fully compatible with conventional EDA tools for synchronous designs. Starting from a simple standard-cell library for asynchronous logic, this flow builds pseudo-synchronous models of the cells. With these models, a simple set of pseudo-synchronous timing constraints can be given to industrial EDA tools to benefit from their optimization strategies, through all steps from synthesis to place & route. This flow was benchmarked against regular asynchronous implementation relying on maximum delay constraints. Pseudo-synchronous modeling allows achieving significantly better performance and regularity than asynchronous modeling, for faster run times and reduced design effort. The proposed flow was used for the physical implementation of a 20-node network-on-chip in the ST Microelectronics 65nm low-power technology. It achieves an end-to-end asynchronous throughput of 850Mflit/s in typical conditions, making it faster than all connected synchronous IPs.

For the third time, ASYNC is co-located with the ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2012). The two conferences are back-to-back, ASYNC runs May 7-9, and NOCS runs May 9-11. We hope that attendees will find the time to attend both conferences, and we hope attendees will appreciate avoiding some travel. We received 44 regular paper submissions, of which 18 were accepted for final publication and presentation at the symposium. The program chairs were impressed by the quality and range of submissions. The Program Committee members and external reviewers provided four in-depth reviews of each submission. The selection process emphasized novelty of contribution. We are pleased to see several newcomers amongst the authors whose papers have been accepted. The final program is wideranging, covering: performance analysis and optimization; processor case studies; asynchronous memories; synthesis and CAD; arithmetic circuits; GALS and signaling; and fault tolerance. The call for papers also invited submissions for two special tracks: "Asynchrony in biology-inspired computing" and "Industrial applications of asynchronous design."

In advanced CMOS technology, Single Event Effects due to high energy particle may cause different types of electrical effects when crossing silicon: from small delay variations, to bit flips, until permanent damage. Quasi Delay Insensitive asynchronous circuits are the most immune to delay variations thanks to the use of Delay Insensitive codes, but can be very sensitive to bit flips since a Single Event Effect may corrupt the handshake protocol. This paper presents a design technique to mitigate Single Event Effect by adding temporal redundancy to Delay Insensitive codes. This multiple bit fault tolerant design technique is adaptable to any 1-of-N DI code, and is particularly well suited to asynchronous Networks-on-Chip. The proposed Temporally Redundant Delay Insensitive codes have been evaluated using a Single Event Effect digital fault characterization environment. The result shows better SEE tolerance and reduced area and performance impact.

3D stacking is seen as one of the most interesting technologies for System-on-Chip (SoC) developments. However, 3D technologies using Through Silicon Vias (TSV) have not yet proved their viability for being deployed in large-range of products. In this paper, we are investigating 3D Network-on-Chip has a promising solution for increased modularity and scalability. We show that an efficient implementation based on asynchronous logic provides an available bandwidth of 64GB/s for only 700 TSV, outperforming classical interfaces while simplifying the assembly process. We also point out the benefit in terms of power consumption for these new interfaces with a gain of 5 times compared to classical LPDDR2 interfaces.

In this paper we propose a fine-grain Adaptive Voltage and Frequency Scaling (LAVFS) architecture to optimize energy efficiency in presence of in-die variability. For each System-on-Chip power domain, we use a Dynamic Voltage Scaling technique called ‘Vdd-Hopping’ as efficient as DC/DC power converters but much easier to integrate and control at fine-grain. Unlike previous AVS schemes, the supply voltages are fixed and the functional core frequencies are adjusted according to local variability. The hopping ratio is then dynamically determined to achieve an applicative performance target. The proposed Local AVFS architecture based on the dynamic hopping solution and its application to GALS architectures is proposed.

International audience; With growing integration, power consumption is becoming a major issue for multi-core chips. At system level, per-core Dynamic Voltage and Frequency scaling (DVFS) is expected to save substantial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respects throughput and latency constraints. The approach has been fully validated on a real Multiple Input Multiple Output (MIMO) Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved.

3D technologies using Through Silicon Vias (TSV) have not yet proved their viability for being deployed in large-range products. In this paper, we investigate three promising perspectives for short to medium terms adoption of such technology in high-end System-on-Chip built around multi-core architectures: the wide bus concept will help solving high bandwidth requirements with external memory. 3D Network-on-Chip is a promising solution for increased modularity and scalability. We show that an efficient implementation provides an available bandwidth outperforming classical interfaces. Finally, we put in perspective the active interposer concept which aims at simplifying and improving power, test and debug management.

International audience; With growing integration, power consumption is becoming a major issue for multi-core chips. At system level, per-core DVFS is expected to save substantial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respects throughput and latency constraints. The approach has been fully validated on a real MIMO Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved.

Chips for digital baseband processing have long been based on simple fixed pipeline structures connecting processing elements. The emergence of complex multi-modes applications like 3GPP-LTE, Software Defined Radio or Cognitive Radio leads to fast handover need between Telecommunication protocols. On one hand, to fulfill these new requirements, more flexible architectures are required. On the other hand, such applications demand more computing performance, and thus power consumption is a concern. In this paper, we present a new chip dedicated to baseband processing. Based on an asynchronous Network-on-Chip and 23 processing units, it delivers 37 GOPS of peak performance. A dynamic reconfiguration management is deployed on the chip for fast handover between modes, with less than 50 µs of full reconfiguration. The asynchronous Network-on-Chip used to communicate allows a complete frequency decoupling between the units. A distributed power management strategy leads to less than 500 mW power consumption in typical use.

Baseband processing for advanced Telecom applications have to face two contradictory issues [1]. The first one is the flexibility required, with the exploding number of modes for a single protocol (e.g. 63 for 3GPP-LTE), the number of protocols to be supported by a single chip (≫10 in 2010) and new applications requiring a handover between protocols. The second concern is related to performance and power consumption: performance demands are exploding (up to 100GOPS are now required) with decreasing power consumption constraints (roughly 500mW).

The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot be satisfied only by point-to-point or shared-bus interconnects. By providing more bandwidth at reasonable power consumption, new communication infrastructures like NoCs seem promising, but are still limited by implementation issues. We present in this paper an Asynchronous Network-on- Chip architecture with two main innovations. Firstly, an automatic power regulation scheme is proposed to dynamically save leakage and dynamic power consumption. Secondly, due to the current lack of testing methodology for asynchronous logic, we propose a novel DfT solution to allow acceptance of the asynchronous NoC. The proposed architecture has been fully implemented in a STMicroelectronics CMOS 65nm technology, integrated in a complex test-chip and fabricated.

As Globally Asynchronous Locally Synchronous (GALS) systems are becoming preponderant in complex SoC and NoC, we present the design and implementation of a new GALS adapter to be used in ANoC, an asynchronous NoC architecture. The proposed GALS adapter is a complete IP integration module, including a new FIFO based design using a Johnson-encoding principle for timing domains interfacing, and a local programmable clock generator for the IP unit. The GALS adapter has been implemented in a ST 65nm technology in standard-cell based design. It is provided as a hard-macro for easy IP integration, can generate 256 clock frequencies from 25 MHz to 1 GHz, and achieves 500 MHz nominal throughput from a clocked domain to a QDI asynchronous logic NoC.

International audience; This paper presents a physical implementation of the DSPIN network-on-chip in the FAUST architecture. FAUST is a stream-oriented multi- application SoC platform for telecommunications addressing IEEE 802.11a and MC-CDMA standards. The original asynchronous network-on-chip (ANOC) of FAUST has been replaced by the multi-synchronous DSPIN network-on-chip. In this paper, we analyze how the DSPIN network-on-chip, originally designed to support shared memory and multi-processors architectures, can support stream-oriented architectures. The physical implementation of both ANOC and DSPIN are presented. Finally, a comparison between ANOC and DSPIN designs in a 130 nm technology is carried out in terms of area, throughput, packet latency, and power consumption.

In systems-on-chip, dynamic voltage scaling allows energy savings. If only one global voltage is scaled down, the voltage cannot be lower than the voltage required by the most constrained functional unit to meet its timing constraints. Fine-grained dynamic voltage scaling allows better energy savings since each functional unit has its own independent clock and voltage, making the chip globally asynchronous and locally synchronous. In this paper we propose a local dynamic voltage scaling architecture, adapted to globally asynchronous and locally synchronous systems, based on a technique called Vdd-hopping. Compared to traditional power converters, the proposed power supply selector is small and power-efficient, with no needs for large passives or costly technological options. This design has been validated in a STMicroelectronics CMOS 65nm low-power technology.

3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (

Current computing architectures for data-intensive applications are facing severe memory access limitations.Power hungry caches are not efficient anymore, the memory available to the cores is more and more limited in both capacity and latency.Unfortunately, the trend in memory technologies does not scale as fast as the computing performances, leading to the so called memory wall.To address these challenges, the main directions followed in the research community are both at the architecture level and technology level: new architecture with computation immersed in memory, coupled to on-chip Non-Volatile Memory (NVM) for increased density, and advanced 3D architectures for increased memory capacity while offering more tightly coupled computing and memory.As a first step towards these directions, this PhD thesis addresses the architectural study of computation immersed in memory architecture with an increased memory sizing, scalability and reconfigurability using standard CMOS technologies.Recent techniques that bringing computing as close as possible to the memory array such as, In-Memory Computing (IMC), Near-Memory Computing (NMC), are expected to solve these limitations, but are facing limitations such as, fixed vector size and total available memory capacity.To process data-intensive applications with larger datasets, in this thesis, I propose a scalable and reconfigurable tile-based architecture composed of SRAM-based NMC tiles, each enabling arithmetic and logic operations within the memory.The combination of a horizontal scalability scheme and a vertical data communication offers an adaptive vector size for maximum performance onto the NMC tiles.In terms of programming model, this architecture can be programmed as an accelerator and executes vector-based kernels available on existing SIMD engines.For architecture exploration, performance and energy of data-intensive kernels are quantified using an instruction-accurate simulation platform using SystemC/TLM, calibrated on existing NMC SRAM tile designed in 22 nm FDSOI technology.Compared to 512-bit SIMD architecture, the proposed NMC architecture achieves an Energy-Delay Product (EDP) reduction up to 52x and 71x for linear and quadratic computational complexity kernels, respectively., Les architectures de calcul actuelles dédiée aux applications gourmandes en données sont confrontées à de graves limitations d'accès à la mémoire.Les caches gourmands en énergie ne sont plus efficaces et la mémoire disponible pour les processeurs est de plus en plus limitée en termes de capacité et de latence.Malheureusement, l'évolution technologique des mémoires ne s'adapte pas aussi rapidement que les performances de calcul, ce qui conduit à ce que l'on appelle le "mur mémoire".Pour relever ces défis, les principaux axes de recherche suivies dans la communauté se situent à la fois au niveau de l'architecture et au niveau technologique : des nouvelles architectures avec du calcul immergé dans la mémoire, couplée à une mémoire non-volatile (NVM) sur puce pour une densité accrue, et des architectures 3D pour une capacité de mémoire accrue tout en offrant un couplage étroit entre le calcul et la mémoire.Afin d'avancer vers ces directions, cette thèse de doctorat porte sur l'étude architecturale du calcul immergé dans la mémoire, de son dimensionnement, son extensibilité et sa reconfigurabilité en utilisant des technologies CMOS standard.Les techniques récentes qui rapprochent le plus possible le calcul de la matrice mémoire, telles que le calcul en-mémoire (IMC) et le calcul proche-mémoire (NMC), devraient permettre de résoudre ces problèmes, mais sont confrontées à des limitations telles que la taille fixe des vecteurs et la capacité totale de mémoire disponible.Pour traiter des applications avec des ensembles de données plus importants, je propose dans cette thèse, une architecture modulable et reconfigurable basée sur des tuiles NMC à base de SRAM, chacune permettant des opérations arithmétiques et logiques au sein de la mémoire.La combinaison d'un schéma d'extensibilité horizontale et d'une communication de données verticale offre une taille de vecteur adaptable pour des performances maximales sur les tuiles NMC.En termes de modèle de programmation, cette architecture peut être programmée comme un accélérateur et exécute les applications vectorisées disponibles sur les accélérateurs SIMD existants.Pour l'exploration architecturale, les performances et l'énergie des applications à forte intensité de données sont quantifiées à l'aide d'une plateforme de simulation précise à l'instruction, utilisant le langage SystemC/TLM et calibrée sur une implémentation de la tuile NMC en SRAM conçue avec la technologie FDSOI 22 nm.Par rapport à l'architecture SIMD 512 bits, l'architecture NMC proposée permet une réduction énergétique et des délais (EDP) allant jusqu'à 52x et 71x pour les applications à complexité de calcul linéaire et quadratique, respectivement.

The integration of multiple chips in a 3D stack serves as another path to move forward in the more-than-Moore domain. 3D integration technology consists in interconnecting the integrated circuits in three dimensions using inter-die interconnects (μ-bumps or Cu-Cu interconnects) and Through Silicon Vias (TSV). This changeover from horizontal to vertical interconnection is very promising in terms of speed and overall performances (RC delay, power consumption and form factor). On the other side, for technology development of 3D integration before the production of the 300 mm wafers with all FEOL and BEOL layers, several short-loops must been carried out to enable incremental characterization and structural test of 3D interconnects in order to evaluate the electrical performances (R, L, C …). In the other hand, the test of application circuits consists in adding testability features (Boundary-Scan-Cells (BSCs), Built-In-Self-Test (BIST) and scan chains …) for functional test of the hardware product design (including the different stacked dies and the 3D interconnections) . The added Design-For-Test (DFT) architecture make it easier to develop and apply manufacturing tests to the designed hardware. Compared to μ-bumps, Cu-Cu hybrid bonding provides an alternative for future scaling below 10μm pitch with improved physical properties but that generates new challenges for test and characterization; the smaller the Cu pad size, the more the fabrication and bonding defects have an important impact on yield and performance. Defects such as bonding misalignment, micro-voids and contact defects at the copper surface, can affect the electrical characteristics and the life time of 3D-IC considerably. Moreover, test infrastructure insertion for HD 3D-ICs presents new challenges because of the high interconnects density and the area cost for test features. Hence, in this thesis work, an innovative misalignment test structure has been developed and implemented in short-loop way. The proposed approach allows to measure accurately bonding misalignment, know the misalignment direction and estimate the contact resistance. Afterwards, a theoretical study has been performed to define the most optimized DFT infrastructure depending on the minimum acceptable pitch value for a given technology node to ensure the testability of high-density 3D-ICs. Furthermore, an optimized DFT architecture allowing pre-bond and post-bond for high-bandwidth and high-density 3D-IC application (SRAM-on-Logic) has been proposed. Finally, to assess performance of HD 3D-ICs, two complementary BISTs has been implemented in an application circuit using the same misalignment test structure developed above and a daisy chain of Cu-Cu interconnects. Using test results, on the one hand, the impact of misalignment defect on the propagation delay has been studied and on the other hand full open and μ-voids defects at the contact surface level has been detected., L'intégration de plusieurs puces dans un empilement 3D constitue un autre moyen d'avancer dans le domaine « More-than-Moore ». L’intégration 3D consiste à interconnecter les circuits intégrés en trois dimensions à l'aide des interconnexions inter-puces (µ-bumps ou Cu-Cu interconnexions) et les TSVs (Through Silicon Vias). Ce passage d'une interconnexion horizontale à une interconnexion verticale est très prometteur en termes de rapidité et de performances globales (délai RC, consommation et facteur de forme). D'autre part, pour le développement technologique de l’intégration 3D avant la production des plaques (wafers) de 300 mm avec toutes les couches FEOL et BEOL, plusieurs plaques (short-loop) doivent être réalisées pour permettre la caractérisation incrémentale et le test structurel des interconnexions 3D afin d'évaluer la performances électriques (R, L, C…). D'autre part, le test des circuits d'application consiste à ajouter des fonctionnalités de testabilité (Boundary-Scan-Cells (BSC), Built-In-Self-Test (BIST) et des chaînes de scan …) pour le test fonctionnel du circuit 3D (y compris les puces empilées et les interconnexions 3D). L'architecture DFT (Design-For-Test) ajoutée facilite le développement et l'application des tests de fabrication au circuit conçu. Par rapport aux interconnexions µ-bumps, la liaison hybride Cu-Cu offre une alternative pour descendre au-dessous de 10µm de pas entre les interconnexions (pitch) avec des propriétés physiques améliorées, mais cela génère de nouveaux défis pour les tests et la caractérisation; plus la taille de la plaque de cuivre est petite, plus les défauts de fabrication et de liaison ont un impact important sur le rendement et les performances. Des défauts tels que le désalignement, des « µ-voids » et des défauts de contact à la surface du cuivre peuvent affecter considérablement les caractéristiques électriques et la durée de vie du circuit 3D. De plus, l'insertion d'une infrastructure de test pour les circuits intégrés 3D HD présente de nouveaux défis en raison de la densité d'interconnexions élevée et du coût de l’insertion de l’infrastructure du test. C’est dans ce contexte que s’inscrit cette thèse de doctorat dans laquelle une structure de test innovante de désalignement a été développée. L’approche proposée permet de mesurer avec précision le désalignement des interconnexions, de connaître la direction du désalignement et d’estimer la résistance de contact. Une étude théorique a ensuite été réalisée pour définir l’infrastructure DFT la plus optimisée en fonction de la valeur du pas minimal acceptable pour un nœud technologique donné, afin de garantir la testabilité des circuits 3D haute densité. De plus, une architecture DFT optimisée permettant un test avant et après assemblage des circuits 3D haute densité (Mémoire-sur-Logique) a été proposée. Enfin, pour évaluer les performances des circuits 3D haute densité, deux BISTs complémentaires ont été mis en œuvre dans un circuit d’application utilisant la même structure de test de désalignement développée ci-dessus et une chaîne d’interconnexions Cu-Cu. En utilisant les résultats des tests, d’une part, l’impact du défaut de désalignement sur le temps de propagation a été étudié et, d’autre part, les défauts de contact et les « µ-voids » au niveau de la surface de contact ont été détectés.