437 results on '"Raik, Jaan"'
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152. Fault-resilient NoC router with transparent resource allocation
153. Automated area and coverage optimization of minimal latency checkers
154. Comprehensive performance and robustness analysis of 2D turn models for network-on-chips
155. A scalable technique to identify true critical paths in sequential circuits
156. From online fault detection to fault management in Network-on-Chips: A ground-up approach
157. Measuring and Identifying Aging-Critical Paths in FPGAs
158. BASTION: Board and SoC test instrumentation for ageing and no failure found
159. A novel random approach to diagnostic test generation
160. Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs
161. A tool for random test generation targeting high diagnostic resolution
162. Logic-based implementation of fault-tolerant routing in 3D network-on-chips
163. Foreword
164. Designing reliable cyber-physical systems overview associated to the special session at FDL'16
165. SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints
166. Gate-level modelling of NBTI-induced delays under process variations
167. A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage
168. Scalable algorithm for structural fault collapsing in digital circuits
169. Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits
170. A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers
171. A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers
172. FSMD RTL design manipulation for clock interface abstraction
173. Immortalizing many-core systems early experiences of the horizon 2020 action IMMORTAL
174. Automated minimization of concurrent online checkers for Network-on-Chips
175. SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic
176. SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores
177. New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams
178. Code Coverage Analysis for Concurrent Programming Languages Using High-Level Decision Diagrams
179. Design and Test Technology for Dependable Systems-on-chip
180. Testing Strategies for Networks on Chip
181. Sequential Test Set Compaction in LFSR Reseeding
182. High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis
183. Web-Based Environment for Digital Electronics Test Tools
184. Diagnostic Modeling of Digital Systems with Multi-Level Decision Diagrams
185. Distributed Approach for Genetic Test Generation in the Field of Digital Electronics
186. Extended checkers for Logic-Based Distributed Routing in Network-on-Chips
187. Critical Path Tracing Based Simulation of Transition Delay Faults
188. Logic simulation and fault collapsing with shared structurally synthesized bdds
189. Advanced technical education in the age of cyber physical systems
190. A synthesis-agnostic behavioral fault model for high gate-level fault coverage.
191. Hierarchical identification of NBTI-critical gates in nanoscale logic
192. Abstraction of clock interface for conversion of RTL VHDL to SystemC
193. Automated Design Error Localization in RTL Designs
194. Decision Diagram Based Test Methods for Digital Systems
195. At-speed self-testing of high-performance pipe-lined processing architectures
196. Comparison of Model-Based Error Localization algorithms for C designs
197. Identifying NBTI-Critical Paths in Nanoscale Logic
198. Performance analysis of cosimulating processor core in VHDL and SystemC
199. Assessment of diagnostic test for automated bug localization
200. Foreword to the 16th IEEE DDECS Symposium
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