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This paper describes the design of an active, integrated CMOS sensor array for fluorescence applications which enables time-gated, time-resolved fluorescence spectroscopy. The 64-by-64 array is sensitive to photon densities as low as 8.8 x 10[sup6] photons/cm[sup2] with 64-point averaging and, through a differential pixel design, has a measured impulse response of better than 800 ps. Applications include both active microarrays and high-frame-rate imagers for fluorescence lifetime imaging microscopy. [ABSTRACT FROM AUTHOR]

Active deskewing is an important technique for managing variability in clock distributions but introduces latency and power-supply-noise sensitivity into the resulting networks. In this paper, an adaptively deskewed resonant clock network, based on an injection-locked distributed differential oscillator, is described, in which the delay lines required for deskewing are incorporated into the injection-lock source, dramatically improving jitter immunity. A power management system based on automatic amplitude control of the resonant grid further enhances energy efficiency. A prototype system operates at a nominal 2-GHz frequency in a 0.18 μm technology with on-chip jitter and skew measurement circuits and with more than 25 pF/mm² of clock loading. [ABSTRACT FROM AUTHOR]

Well-designed circuits are one key "insulating" layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to "hide" more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation. [ABSTRACT FROM AUTHOR]

In this paper, we describe the use of distributed loss compensation to provide nearly transmission-line behavior for long on-chip interconnects. Negative impedance converters (NICs) inserted at regular intervals along an on-chip line are shown to reduce losses from more than 1 dB/mm to less than 0.3 dB/mm at 10 GHz. Results are presented for a 14-mm 3-Gb/s on-chip double-data-rate (DDR) link in 0.18-µm CMOS technology, with a measured latency of 12.1 ps/mm and an energy consumption of less than 2 pJ/b with a BER < 10-14. This constitutes a factor-of-three improvement in power and a one-and-a-half-times improvement in latency over an optimally repeated RC line of the same wire width. [ABSTRACT FROM AUTHOR]

Surface-based sensing assays based on fluorescence-based detection have become commonplace for both environmental and biomedical diagnostics. Traditional array scanners are expensive, large, and complex instruments. This paper describes the design of an active CMOS biosensor substrate for fluorescence-based assays that enables time-gated, time-resolved fluorescence spectroscopy without the need for an external reader. The array is sensitive to photon densities as low as 1.15 × 108/cm², has a dynamic range of over 74 dB, and has subnanosecond timing resolution. Sensitivity is achieved through subsampling and averaging. [ABSTRACT FROM AUTHOR]

In this paper, we describe the design and implementation of a continuous-time finite-impulse-response processor chain, which includes a 6-bit asynchronous ADC, an asynchronous digital core, and an 8-bit asynchronous DAC designed in TSMC 0.25-µm technology. The continuous-time, discrete-amplitude systems combine benefits associated with analog and digital systems. Discrete-amplitude representations leverage the noise immunity and robustness of digital implementations. Continuous-time, nonsampled operation prevents aliasing and reduces the in-band quantization noise associated with the aliasing of subharmonic components. We present measurement results demonstrating an audio low-pass filter with a bandwidth of 6.0 kHz. [ABSTRACT FROM AUTHOR]

This paper presents a distributed differential oscillator global clock network where the clock capacitance is rendered resonant with a set of on-chip spiral inductors. The clock amplitude and clock phase are both uniform across the entire global distribution, making this design scalable and compatible with existing local clocking methodologies. The resonant network, combined with phase averaging of the distributed oscillator, provides high immunity to process-, voltage-, and temperature-variation-induced timing uncertainty. Measurement results from a prototype design implemented in a 0.18-µm CMOS technology show almost an order of magnitude less jitter and power than a traditional tree-driven grid global clock distribution. On-chip measurement circuits are used to characterize the jitter on the test chip, while a simulation model is used to examine skew and higher-order resonances in the resonant clock network. [ABSTRACT FROM AUTHOR]

In this paper, we describe a technique for delivering power to a digital integrated circuit at high voltages, reducing current demands and easing requirements on power-ground network impedances. The design approach consists of stacking CMOS logic domains to operate from a voltage supply that is a multiple of the nominal supply voltage. DC-DC downconversion is performed using charge recycling without the need for explicit downconverters. Experimental results are presented for the prototype system in a 0.18-μm CMOS technology operating at both 3.6 V and 5.4 V. Peak energy efficiencies as high as 93% are demonstrated at 3.6 V. [ABSTRACT FROM AUTHOR]

In this paper, we describe the design of on-chip repeater-less interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8-Gb/s serial link employing this pulsed current-mode signaling in a 0.18-µm CMOS process is described and measured. [ABSTRACT FROM AUTHOR]

This paper describes an energy-efficient means to achieve on-chip dc-dc conversion for digital CMOS circuits. The approach uses balanced voltage island running at fractions of the off-chip supply voltage. Charge "discarded" by one domain is "recycled" to supply energy for another. When the domains are ideally balanced, all the energy dissipated by electrons in "dropping" to lower potentials is used for active computation. We describe the design and measurement of a prototype system in a 0.18 µm CMOS process that provides active on-chip voltage regulation and controlled dc-dc conversion with this technique. [ABSTRACT FROM AUTHOR]

This paper presents a new approach to global clock distribution in which tree-driven grids are augmented with on-chip spiral inductors to resonate the clock capacitance. In this scheme, the energy of the fundamental frequency resonates between electric and magnetic forms, with the reduced admittance of the clock network allowing for significantly lower gain requirements in the buffering network. The substantial improvements in jitter and power resulting from this approach are presented using measurement results from two test chips, one fabricated in a 90-nm and the other in a 0.18-µm CMOS technology. [ABSTRACT FROM AUTHOR]

In this paper, we report the development of a full-chip, three-dimensional, shapes-based, resistence-inductance- capacitance extraction tool, which was developed as part of a university-industry collaboration. The technique of return-limited inductances is used to provide a sparse, frequency-independent inductance and resistance network with self-inductances that represent sensible "nominal" values in the absence of mutual coupling. Mutual inductances are extracted for accurate crosstalk analysis. The tool exploits high-capacity scan-band techniques and disk caching. Accuracy is validated by comparison with full-wave finite-element field solvers. [ABSTRACT FROM AUTHOR]

It is widely recognized that adaptive control of the power supply is one of the most effective variables to achieve energy-efficient computation. Most on-chip dc-dc conversion systems have relied on buck converters with off-chip LC filters. In this paper, we describe the development of a software controllable, fully integrated on-chip dc-dc downconversion system that combines switched-capacitor voltage dividers and linear regulators to efficiently regulate from 2.5 V down to about 0.65 V. The use of switched-capacitor supplies offers better efficiencies than what is achievable with linear regulators alone. [ABSTRACT FROM AUTHOR]