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Presents a performance model for the University of Michigan MCM (multichip module)-based GaAs microcomputer. The model takes into account architectural as well as MCM packaging considerations such as the chip-to-substrate bonding method, the dielectric constant of the insulator, and the resistivity of the metal conductor. The authors illustrate the use of the model by finding the I-cache size which maximizes the MIPS (millions of instructions per second) rating for given MCM technology parameters. >

A simplified version of a RISC (reduced instruction set computer) microprocessor has been implemented with E/D MESFET DCFL (direct coupled FET logic) in the Vitesse HGaAs II process. This chip was designed to drive the development of digital GaAs design automation tools. The processor architecture was modified to fit DCFL technology. The 60,500-transistor circuit executes a set of 29 basic instructions. It dissipates 11 W and operates at over 100 MHz. >

We present a procedure, based on dimensional analysis, to simplify macromodeling. By combining variables according to their units, simpler equations involving dimensionless variables can be derived. The procedure is illustrated by developing macromodels for power dissipation, supply current, and propagation delay of a CMOS inverter. >

The paper is an overview of the architecture, technology and CAD tools used in the design of an experimental 250 MHz 'micro-supercomputer' which is being designed for a sustained performance of 170 MIPS. The system will include a gallium arsenide processor which executes the MIPS instruction set and a two-level cache memory system, packaged on a multi-chip module. The risk in undertaking this project is minimized by using existing but advanced GaAs technology (GaAs MESFET enhancement/depletion direct-coupled FET logic (E/D DCFL)), by building needed CAD tools on top of commercial tools, and by using a standard instruction-set architecture. >

In this paper, a novel hardware design for an Internet Protocol Version 6 router using field programmable gate arrays is proposed. A dataflow, parallel, pipelined and scalable architecture is presented that has the potential of matching the enormous communication bandwidths of transmission links. A ternary content addressable memory (CAM) in the form of cache is adopted as a routing table search engine. It can offer O(1) search time with just O(N) memory words. Adding a sorting (priority) mechanism by caching the routing table in CAM and using a modified form of sector mapping technique eliminates the slow insertion and deletion times without adding significant additional hardware costs.

With improvements in technology, accurate delay modeling of interconnects is becoming increasingly important. Due to decreasing feature sizes, the spacing between the signal lines is also decreasing. Consequently, the switching activities on the neighboring lines can have a significant impact on the delay of the line of interest, and can no longer be ignored. Accurate modeling of this phenomenon, which we call the proximity effect, is the subject of this paper. This is similar to the state-dependency of logic gate delays, where signal delay can be affected by the switching activities on the side inputs of a gate. We describe an efficient and accurate delay computation method using precomputed interconnect moments that treats the coupled lines as uniform, distributed RC lines and does not make any lumped approximations. This allows the proposed delay model to be used in a timing analysis tool operating over both gate and interconnect domains while accounting for state-dependency.

We present the design of a firewall for IP networks using a field-programmable gate array (FPGA). The FPGA implements, in hardware, the accept or deny rules of the firewall. A hardware-based firewall offers the advantages of speed over a software firewall, in addition to direct interfacing with network devices, such as an Ethernet or a serial line transceiver. This paper shows how the rules are translated to VHDL and then implemented in hardware, and how the hardware is utilized to filter network traffic in a packet-by-packet fashion, or based on connection information, with a speed of more than 500,000 packets per second.

The goal of this paper is to present a design methodology for developing energy aware algorithms. The key idea revolves around identifying operations called kernels, which are frequently used operations in the algorithm that can be implemented in hardware. Optimising these kernels for performance or energy would then lead to a major impact in energy saving. We propose a six-step methodology for design of energy aware algorithms. The method includes: high-level algorithm analysis, identifying high frequency kernels, determining the order of computation for each kernel via asymptotic analysis, prioritising kernels in terms of energy impact, proposing alternative implementations to the kernels that cause high energy consumption and investigating further opportunities for energy optimisation specific to the studied algorithm. We further propose a simple and efficient method for estimating a kernel's energy cost. The method was successfully tested with back-propagation (BP) neural network algorithm to identify the kernels targeted for energy optimisation. Based on the findings, we proposed several custom changes to the BP algorithms for lower energy alternatives to kernels, including options that trade off computational accuracy for higher energy saving.

The sensitive role that wireless sensor networks (WSNs) play in interpreting the environment characteristics and the need for ensuring the integrity of the sensor readings, necessitate the use of security mechanisms. One of the main security issues in WSNs is manifested when malicious nodes spoof their identities and locations. In this paper, we propose a decentralised malicious node detection technique based on the received signal strength indicator (RSSI). The method is probabilistic, taking into account shadowing and fading effects. An empirical pathloss model is generated at each node during a discovery phase. This method takes into consideration mobility, channel conditions, and network density among other factors. In addition, the developed technique is able to localise the detected node within a small area. Simulation results highlight the high detection rate of the method under varying conditions.

In this paper, we present PATROL, a general and comprehensive reputation-based trust model for distributed computing. The proposed model is an enhancement over our previous model, TRUMMAR, and aims at achieving a truly unique model that incorporates most concepts that are essential to determining trust-based decisions. Among the concepts upon which the trust model is based are reputation values, direct experiences, trust in the credibility of a host to give recommendations, decay of information with time based on a dynamic decay factor, first impressions, similarity, popularity, activity, cooperation between hosts, in addition to a hierarchy of host systems. The simulations performed on this model confirm its correctness and its adaptability to different environments and situations.

Due to the endless attempts at breaching the security of distributed systems, it has become a necessity to investigate an entity's trustworthiness and reliability before interacting with it. The ideal solution is to have a trusted environment, but since this is impractical, efforts have focused on devising frameworks for computing trust through reputation. This paper presents a reputation-based trust model that allows hosts in distributed systems to protect their resources from other malicious hosts. This model is unique in being a truly comprehensive model since it accounts, in a unified framework, for a multitude of concepts such as prior-derived reputation, first impression, loss of reputation information with time, hierarchy of host systems (neighbours, friends, and strangers), and the inclusion of interaction results in reputation calculation. We show both the simulation and implementation results that verify the correctness of this model and the effects of its various model parameters.

In this chapter, we present a brief survey on the latest advancements in Network-as-a-Service (NaaS) platforms based on the software-defined networking (SDN) model. This survey sheds light on the main advantages of network virtualization and programmability in cloud computing environments that led to the provisioning of dynamic, flexible, and secure virtual network services. In spite of the great benefits provided by network virtualization in the cloud, further research is still needed to tackle a plethora of technical challenges in the fields of dynamic NaaS configuration and operation. This chapter paves the way for a better understanding of the problems hindering the NaaS adoption in current cloud architectures and represents a call for action on the need for having a dynamic NaaS configuration service to tackle these problems. Accordingly, the chapter proposes the design and implementation of a centralized cloud service for creating virtual networks (VNets) in SDN-based cloud architectures.