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On capacity considerations it is clear that it is advantageous to use non-binary neural networks.

This paper studies a simple synthesis algorithm of desired cellular automata (ab. CAs) based on a binary neural network (ab. BNN). The CAs have binary state variable and the BNN has bipolar connection parameters. In order to realize dynamics of the CA, the bipolar parameters of BNN are determined using the genetic algorithm. Performing basic numerical experiments we show that the BNN can realize desired dynamics with small number of hidden layers for a class of CAs. We also consider the case of noisy teacher signals. These results provide basic information for application to signal processing, analysis of digital nonlinear phenomena, and so on.

Discrete-Time Two-State Systems Asynchronous Operating Hopfield Neural Network An Alternative Version of the Asynchronous Binary Neural Network Neural Network in Synchronous Mode of Operation Block Sequential Operation of the Hopfield Neural Network Concluding Remarks Problems ]]>

In this paper, we analyze characteristics of GA-based learning method of Binary Neural Networks (BNN). First, we consider coding methods to a chromosome in a GA and discuss the necessary chromosome length for a learning of BNN. Then, we compare some selection methods in a GA. We show that the learning results can be obtained in the less number of generations by properly setting selection methods and parameters in a GA. We also show that the quality of the learning results can be almost the same as that of the conventional method. These results can be verified by numerical experiments.

This chapter describes a rather less traditional technique of text processing. The technique is based on the binary neural network Correlation Matrix Memory. We propose using the neural network for text searching tasks. Two methods of coding input words are described and tested. Further, we discuss the problems of using this approach for text processing.

A distributed neural network referred to as a neuromic array, which is restricted to binary alphabets, has been previously introduced (Porter, 1988). The present study loosens this restriction by demonstrating the design extension to the quartic case. A natural morphism between the quartic-valued and binary-valued vector spaces is used to establish a design equivalence between the two settings. The study compares the robustness and performance of equivalent binary and quartic designs. Extensive simulations indicated that the performance of binary design eroded only slightly when transported to the quartic case. The quartic design required fewer neurons, and a higher density was achieved. >

We report on an initial study on the dynamic behaviors of two neural networks that interact with each other. We demonstrate how to tame chaos and oscillations in a higher order binary neural network by adjusting the strength of interactions between the two neural networks.

We compute the capacity of a binary neural network with dynamic depressing synapses to store and retrieve an infinite number of patterns. We use a biologically motivated model of synaptic depression and a standard mean-field approach. We find that at T=0 the critical storage capacity decreases with the degree of the depression. We confirm the validity of our main mean-field results with numerical simulations.

A new constructive learning algorithm, called Hamming clustering (HC), for binary neural networks is proposed. It is able to generate a set of rules in if-then form underlying an unknown classification problem starting from a training set of samples. The performance of HC has been evaluated through a variety of artificial and real-world benchmarks. In particular, its application in the diagnosis of breast cancer has led to the derivation of a reduced set of rules solving the associated classification problem.

This paper describes research into the hardware implementation of a binary correlation matrix memory (CMM) neural network. It shows that the network can be implemented with on-board training and testing that operates at over 200 times the speed of a current mid-range workstation, and is scalable to very large problems. The paper describes the network, how it is implemented and its performance.

Binary neural networks are a very important and active research topic. In the present paper a geometrical constructive approach is discussed in comparison with similar methods, with the aim of obtaining nets with optimal structural complexity. Experiments show promising results.

This paper presents an ultra-high-speed sorter based upon a simplified parallel sorting algorithm using a binary neural network which consists both of binary neurons and of AND-OR synaptic connections to solve sorting problems at two and only two clock cycles. Our simplified algorithm is based on the super parallel sorting algorithm proposed by Takefuji and Lee. Nevertheless, our algorithm does not need any adders, while Takefuji's algorithm needs n×(n−1) analog adders of which each has multiple input ports. For an example of the simplified parallel sorter, a hardware design and its implementation will be introduced in this paper, which performs a sorting operation at two clock cycles. Both results of a logic circuit simulation and of an algorithm simulation show the justice of our hardware implementation even if in the practical size of the problem.

A neural network emulator is described in this paper. The device can implement neural networks of various architectures, provided that the inputs and outputs of neurons are binary.

The paper describes a binary neural network architecture and its performance in pattern classification. The network is called binary because its inputs are binary and its main components are composed of binary neurons. Apart from the usual input and output layers, the network has two 'hidden' layers, called code layer and linear plane, connected in a feedforward structure. The weights of these feedforward connections are also binary. The performance of the network is demonstrated through binary pattern classification experiments. Comparisons with many one- and two-hidden-layer backpropagation networks are included. The proposed network shows superior performance in all the cases that have been studied. >

This paper presents a novel ferroelectric field-effect transistor (FeFET) in-memory computing architecture dedicated to accelerate Binary Neural Networks (BNNs). We present in-memory convolution, batch normalization and dense layer processing through a grid of small crossbars with reduced unit size, which enables multiple bit operation and value accumulation. Additionally, we explore the possible operations parallelization for maximized computational performance. Simulation results show that our new architecture achieves a computing performance up to 2.46 TOPS while achieving a high power efficiency reaching 111.8 TOPS/Watt and an area of 0.026 mm2 in 22nm FDSOI technology.