201. Hardware Architecture Design of Video Compression for Multimedia Communication Systems.
- Author
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Shao-Yi Chien, Yu-Wen Huang, Ching-Yeh Chen, Chen, Homer H., and Liang-Gee Chen
- Subjects
VIDEO compression ,VERY large scale circuit integration ,IMAGE compression ,MULTIMEDIA communications ,ALGORITHMS ,MPEG (Video coding standard) ,TELECOMMUNICATION systems - Abstract
VLSI realization of video compression is the key to many real-time multimedia communications systems. Among the video compression algorithms, the newly established MPEG-4 and, in particular, H.264 standards have become increasingly popular. However, the high coding efficiency of such video coding algorithms comes at the cost of a dramatic increase in complexity. Effective and efficient hardware solution to this problem are necesary IN this article we present an overview of the hardware design issues of MPEG-4 and H.264. Both mudule and system architectures of these two coding of encoding the D1 resolotion (720 X 48 ) video at 30 Hz. is presented as an example. In addition, the system integration issues of video compression engines with multimedia communication systems and a general hardware platform for various application are discussed. [ABSTRACT FROM AUTHOR]
- Published
- 2005
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