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Hippocampal cholinergic neurostimulating peptide (HCNP) induces the synthesis of acetylcholine in medial septal nucleus in vitro and in vivo. HCNP precursor protein (HCNP-pp) is a multifunctional protein that participates in a number of signaling pathways, including MAPK/extracellular signal and G-protein-coupled receptor kinase 2. We recently demonstrated that the amount of collapsin response mediator protein-2 (CRMP-2) is increased in hippocampus of HCNP-pp transgenic mice. To clarify the interaction between HCNP/HCNP-pp and CRMP-2 and its role in synaptic function, we investigated whether HCNP-pp is localized to the synapse and if it affects protein expression. Here, we demonstrate that HCNP-pp co-localizes with CRMP-2 at presynaptic terminals. Furthermore, HCNP-pp overexpression increases synaptophysin levels. These findings suggest that HCNP-pp, in association with CRMP-2, plays an important role in presynaptic function in the hippocampus.

A nine-year-old Japanese girl with Turner syndrome (45, X/46, Xr (X)) showed poor GH secretion, normal response of TSH, and slightly increased secretion of LH and FSH with increased basic levels, after injection of insulin, TRH, and LH-RH respectively. Since then, r-hGH at 0.5 IU/kg/W has been given for five years under the diagnosis of pituitary dwarfism with Turner syndrome, and an increase of 26 cm in height has been obtained, though menstruation has not been observed till now. Autoimmune diseases such as diabetes mellitus, Addison's disease or thyroid dysfunction have not been observed, up to the age of 14 years. At 15 years, however, regular examination for side-effects of r-hGH revealed hyperthyroidism with 0.1 μU /ml of TSH, 15.7 μg/dl of T4, 4.22 ng/dl of free T4, positive thyroid test, positive microsome test, increased TSAb (1.4 μU/ml) and +32% of BMR, though she has not complained of any kind of clinical symptoms for six months.

We present a 6Gb/s wireline receiver having Frequency Division Multiplexing (FDM) with four frequency sub-channels. Its 6GS/s discrete-time filter consumes less power than a conventional filter which requires the same number of high-speed analog mixers as sub-channels and provides channel filtering of FDM signals that contain four 1.5GSymbol/s data. Improved I/Q-based phase detection using only in-phase amplitude makes possible low-power symbol-rate clock recovery. The FDM receiver fabricated in 90nm CMOS process achieves BER

The detection of small defects in an SRAM cell with our WL-pulse timing-margin measurement scheme has been demonstrated on a 90nm 2Mb SRAM. WL-width control with a high resolution of 24.1ps and a wide range improves the sensitivity of detection for delay and SNM variations with only a 0.6% area overhead, and statistical analysis makes possible the detection of small-delay defects that, in conventional testing, would be buried due to delay variations in peripheral circuitry.

A 15-Mbps, single-channel wireless source synchronous (SWSS) transceiver with a 1-mm on-chip integrated loop antenna has been developed in 90-nm CMOS for 1.25-cm ‘touch-and-proceed communication’ between electronic devices. A newly developed FDM-based SWSS architecture makes simultaneous CLOCK and DATA transmission possible with only a single antenna as well as the elimination of PLL and clock recovery blocks in Rx. We have successfully demonstrated a 1.0-cm robust alignment of antenna position for 1.0-cm communication distance with a 1-mm on-chip antenna at BER

We present a new low-cost technique for detecting gate-oxide early-life failures (ELF) to overcome reliability challenges in robust systems without requiring expensive concurrent error detection. Our approach is enabled by an on-chip clock control technique, applied during periodic on-line self-test and diagnostics, to detect delay shifts over time before functional failures occur. Using 90nm test chips, we demonstrate the following key results: 1. A gate-oxide ELF transistor inside a combinational logic circuit results in delay shifts over time before functional failures appear. 2. The delay shifts can be successfully detected during on-line self-test and diagnostics using our on-chip clock control technique.

An on-chip transformer-based digital isolator for intelligent power management (IPM) systems is proposed. It greatly reduces the number of chips in IPM systems by allowing integration of isolators in a CMOS chip together with MPUs or gate drivers. With a proposed pulse generation / detection scheme that enables a 5V standard CMOS transistor to utilize GHz-band signals, transformer area is reduced to 1/4∼1/8 that of conventional transformers. A test chip achieves a 2.5kV isolation voltage, a 35kV/us CMR, a 1.6mA static current and a 250Mbps data rate, all which are equal to or superior to those of photo couplers or conventional digital isolators. The high-speed low-power capability expands the application potential to include isolated serial links, medical devices, displays, sensors, etc.

This paper presents experimental data from digital circuits on 90nm test chips, together with circuit simulations, to establish the following results: 1. The presence of a gate-oxide early-life failure (ELF) candidate transistor (also called infant mortality) in a logic gate results in delay shifts over time; 2. Delay shifts can be effective indicators of gate-oxide ELF suspects that may be detected using inexpensive digital techniques. These results can be utilized to overcome scaled-CMOS reliability challenges through effective ELF screening during production test or on-line during system operation for systems with built-in self-healing.

1. 1. Twenty perchloric acid-soluble glycoprotein fractions (PASFs) were separated from carcinomatous and non-carcinomatous regions of the livers of 5 patients with primary hepatocellular carcinoma (HCC) and 5 patients with a complication of HCC and hepatocirrhosis (HC). 2. 2. In autoradiography using 125 ,I-labelled Vicia unijuga lectin (VUA) and 125 I-labelled Arachis hypogaea anti-T lectin as probes, 10 PASFs from carcinomatous regions of the livers of 10 patients gave 1 Vgu glycoprotein with T activity and/or 1–4 Vgu glycoproteins, respectively, and among 10 PASFs from non-carcinomatous regions of the livers of 10 patients, 7 PASFs gave no glycoproteins, respectively. li ]3. These results show that a Vgu glycoprotein with T activity and Vgu glycoproteins occur in HCC and in a complication of HCC and HC as oncofetal antigens.

Large scale integration with advanced CMOS technologies has been reducing cost, but maintaining chip dependability is becoming more and more difficult. This is due to increasing complexity of system design and increasing uncertainty of signal timing and level. Chip dependability can be realized at low cost and maintain high efficiency by combining technologies of (A) “Never produce defects” during chip design and manufacturing, (B) “Never let defects escape” during chip testing, and (C) “Never let defects lead to failure” during operations, as shown in Fig. 1.

Acute heart failure syndromes (AHFS) are likely to increase in the future, and the high readmission rate of patients with AHFS is an important issue in Western countries. However, there are very few published epidemiological studies on AHFS in the Asia Pacific region. Because AHFS are heterogeneous, the characteristics, clinical profile, and management of AHFS should be clarified in an epidemiological study. The acute decompensated heart failure syndromes (ATTEND) registry is a prospective, observational, multicenter cohort study being performed in Japan and is the first epidemiological study of AHFS in the Asia Pacific region. This study is designed to investigate several aspects of AHFS as follows: (1) the registry allows patient-based data collection for precise evaluation of patient characteristics and short-term outcomes, including the readmission rate; (2) confirmation of clinical assessments can be performed, and new clinical assessments can be created; and (3) feedback allows the modification of guidelines for clinical management. The present report describes the clinical characteristics of patients with AHFS in Japan based on the preliminary data collected in this study, and the similarities and differences in characteristics of these patients compared with those in Western countries. Although most of the patient characteristics did not differ from those reported in Western studies, there are some unique findings in this study, including a high rate of treatment with carperitide (69.4%) and angiotensin II receptor blockers (53.9%) at discharge and a longer hospital stay (median 21 days). The ATTEND registry is designed to provide valuable information to clarify the characteristics of patients with AHFS to improve their management.

Both insulin resistance and increased oxidative stress in the liver are associated with the pathogenesis of nonalcoholic fatty liver disease (NAFLD). Senescence marker protein-30 (SMP30) was initially identified as a novel protein in the rat liver, and acts as an antioxidant and antiapoptotic protein. Our aim was to determine whether hepatic SMP30 levels are associated with the development and progression of NAFLD.Liver biopsies and blood samples were obtained from patients with an NAFLD activity score (NAS)or = 2 (n = 18), NAS of 3-4 (n = 14), and NASor = 5 (n = 66).Patients with NASor = 5 had significantly lower hepatic SMP30 levels (12.5 +/- 8.4 ng/mg protein) than patients with NASor = 2 (30.5 +/- 14.2 ng/mg protein) and patients with NAS = 3-4 (24.6 +/- 12.2 ng/mg protein). Hepatic SMP30 decreased in a fibrosis stage-dependent manner. Hepatic SMP30 levels were correlated positively with the platelet count (r = 0.291) and negatively with the homeostasis model assessment of insulin resistance (r = -0.298), the net electronegative charge modified-low-density lipoprotein (r = -0.442), and type IV collagen 7S (r = -0.350). The immunostaining intensity levels of 4-hydroxynonenal in the liver were significantly and inversely correlated with hepatic SMP30 levels. Both serum large very low-density lipoprotein (VLDL) and very small low-density lipoprotein (LDL) levels in patients with NASor = 5 were significantly higher than those seen in patients with NASor = 2, and these lipoprotein fractions were significantly and inversely correlated with hepatic SMP30.These results suggest that hepatic SMP30 is closely associated with the pathogenesis of NAFLD, although it is not known whether decreased hepatic SMP30 is a result or a cause of cirrhosis.

Large-scale experimental data from 90nm test chips consisting of 49,152 transistors, and experiments on 90nm test chips containing inverter chains are used to establish: 1. A gate-oxide early-life failure (ELF, also called infant mortality) candidate transistor produces gradually degraded drive currents over time; 2. A digital circuit path consisting of a gate-oxide ELF candidate transistor experiences gradual delay shifts over time before the circuit produces functional failures. These results may be utilized to effectively overcome ELF challenges in scaled CMOS technologies.

The cost for screening test on wafer has continually increased each year; the test cost especially for low-price IC chips, for example, exceeds one-third of total chip cost. Furthermore, screening test on wafer to select good dies (Known-Good-Die) will become more significant to improve the yields of up-to-date packages such as Chip-on-Chip and 3D-LSI. Therefore, the cost reduction for screening test will be a key issue to maintain continuous LSI-performance scaling.

Histopathologically, early lesions of primary biliary cirrhosis (PBC) are focal within the liver and there is segmental involvement of the bile ducts. In addition, the development of PBC is variable within the liver. PBC is characterized by the following laparoscopic findings: reddish patch, mesh-like white marking and gentle undulation, etc. In the present study, we analyzed the correlation between the laparoscopic findings and the histological stage as per Scheuer's classification in 22 patients with PBC. The results of this study are summarized as follows: 1) Reddish patch was frequently observed in the early stage of PBC. 2) Mesh-like white marking was observed in cases of stage I, II and III. 3) Gentle undulation was seen in stage II and III. The absence of this finding is useful in the diagnosis of stage I. 4) In stage IV, these three findings were not observed. 5) From these three findings, it was difficult to differentiate stage II or III. But the presence of portal hypertension and increased vascularity of the liver capsule were observed in accordance with the progression of the disease. Indications of portal hypertension were seen even in the early stage and in some asymptomatic cases of PBC. In conclusion, the laparoscopic findings such as reddish patch, mesh-like white marking, gentle undulaion and portal hypertension are very valuable for stage diagnosis and the evaluation of prognosis in patients with PBC.

A questionnaire survey including hepatic function test values was performed to elucidate the medical treatment of hepatic diseases by gastroenterologists and general internists. Serum ALT level was considered to be an index of destruction of hepatic cells in 94 and 80% of gastroenterologists and general internists, respectively. Serum gamma-GTP values were used as an index of bile stasis and destruction of the bile duct cells by 93% and 70% of the gastroenterologists, respectively and in 61% and 49% of the internists, respectively. In addition, for hepatitis C, gastroenterologists considered the mean serum ALT values (standard values for drug therapy introduction) asor =62IU/L, while general internists considered it asor =79IU/L. In the case of fatty liver, the mean serum ALT values considered by gastroenterologists and general internists wereor =93IU/L andor =90IU/L, respectively. These survey results suggest that there is a need for research-based clarification of hepatic function test values regulating therapy and unification of guidelines for standard values in medical treatment.

Up to now, SiP integration is widely used to increase chip integration density as well as flexibility of combination in heterogeneous devices. Emerging integration and stacking technologies such as 3D integration, TSV (Through Silicon Via), die-to-die proximity communications, EAD (Embedded Active Devices) are becoming greater attention. If we call the first generation SiP integration as “SiP1.0”, what is “SiP2.0” ? When and how is it practical? Each panelists will give their anticipation of future SiP, or “SiP2.0”. This panel talk is not an “A vs. B” type of debate, but more like an evening talk where each panelist presents their visions on the next generation SiP.

Presented here is a thermal sensor, based on transistor off-leakage current, that allows measurement error of less than 3.1degC at 90degC and less than 2degC at 10% Vdd deviation. For experimental evaluation, 11 thermal sensors, each of which occupied only 35 mum times 35 mum area, were placed on a chip, and both the location of a hotspot and the overall temperature distribution were successfully measured and agreed with simulation.

As continuous process scaling produces large-scale chips, small-delay defects become one of the major chip-reliability limiters. Small-delay defect detection techniques for LSI screening have been developed, which can successfully detect outlier chips among normally-distributed chips in a short testing time. In our experiments with 90 nm CMOS 100 MHz test chips, we have successfully detected around 1-ns path-delay shift caused by small-delay defects in only 1/25 of testing time.

We developed a waveguide-integrated Si nano-photodiode (PD) with a surface plasmon (SP) antenna for on-chip optical clock distribution. The interfacial periodic nano-scale metal-semiconductor-metal Schottky electrodes were shown to function as an SP optical antenna and also as an optical coupler between a SiON waveguide and a very thin Si-absorption layer. Furthermore, a very high speed response of 17 ps as well as enhanced photoresponsivity was achieved for a 10-mum coupling length. By using this technology, we fabricated a prototype of a large-scale-integration (LSI) on-chip optical clock system and demonstrated 5 GHz of optical clock circuit operation connected with a 4-branching H-tree structure.

Mitogenであるlead nitrate (LN)によるラット肝の過形成性状態は肝細胞の脱落壊死(apoptosis,制御された細胞死)により正常化することが知られている.本研究では,これら一連の過程をBrdU標識法および顕微蛍光測光法を用いて細胞動態の面から解析し,apoptosisの細胞動態における意義を明らかにすることを目的とした.肝の増殖活性はLN投与後亢進し,36時間目にピークに達し,以後減少した.増殖活性が落ち着き,肝臓が増大した96時間目には多倍体細胞(1核8倍体や2核4倍体細胞,等)の増加が認められた.しかし,apoptosisによる肝重量の正常化にもとない,多倍体細胞の比率は減少した.このことより,多倍体細胞のapoptosisによる排除が示唆された.

Our RF signal-quality measurement macro employs 1) the new window-shifting measurement technique, which can obtain power of high-frequency component with lower-frequency measurements, and 2) the new stair-like weighted addition technique, which can decrease the error due to harmonic power of measured signals. The macro was only 1/10 area of conventional spectrum analyzers. Carrier power of 2.4 GHz-Tx with the measurement error of -20dBm) were successfully detected.

The first achievement of intra-symbol adaptively intermittent receiver has been developed with an inductor-less LNA by 90-nm digital CMOS, and Rx characteristics have been measured (Rx power: 4.5 mW, BER: 4.1times10-5, received signal intensity: -73 dBm, when Rx is enabled within only 8.2% of a single symbol period) with an on-chip stair-like shaping PA (3rd order harmonics of -40.6 dBc) and a digitally controlled direct RF carrier phase modulator (ACPR

A periodically all-in-phase clock generator and a skew-tolerant bus wrapper have been developed for multi-core SOC platforms. The clock generator produces clock frequencies in 81-steps, and the bus wrapper makes possible deterministic data transfer among different frequency clocks even when inter-clock skew is as high as 2 clock cycle times. A combination of the clock generator, the bus wrapper, and loosely balanced global clock distribution serves to ease chip-timing design while maintaining deterministic chip behavior.

Chip production yield of 70% can be increased to 91 % by using fine-grain redundant logic in which only the defective portion of the main circuit is switched to a redundant subcircuit block. In addition, defect-prediction flip-flops prevent over 80% of in-field failures caused by latent defects, while maintaining correct operation. All flip-flops are connected via a scan chain, which can be employed to reproduce states used in avoiding defects, and to trace defect points.

A locally asynchronous, globally synchronous (LAGS) system with data/instruction grain control is presented for the optimization of power supply voltage, speed performance, PVT and noise tolerance. A LAGS CPU with on-chip DC-DC converter that occupies 250times60mum2 in 90nm CMOS has 0.98V to 0.68V VDD control with 50ns/85ns transition time and a speedtracing accuracy of 5%

A clock generator fabricated in 90nm CMOS occupies 300times128mum2 die area and dissipates 40mW at 1.2V. An interleaved clock-edge control technique extends the frequency tuning range and enables control of both rising and falling edge timing. A clock-period dithering technique enhances frequency tuning resolution. Disturbance-control functions that control jitter, duty cycle, and clock skew make timing margin testing possible

We experienced a case of drug-induced hypersensitivity syndrome (DIHS) for salazosulfapyridine (SASP). After we started administration of SASP in a 26-year old man with ulcerative colitis (UC), he had symptoms resembling infectious mononucleosis, high fever, skin eruption, cervical lymphadenopathy, elevate white blood cell count with atypical lymphocyte, and liver dysfunction. We diagnosed the illness as drug-induced hypersensitivity syndrome (DIHS) due to SASP. We halted SASP and started administration of methylprednisolone and prednisolone but his condition deteriorated. We changed to administration of betamethasone and he recovered. In cases of DIHS accompanied by UC, we should administer drugs carefully and recognize serious complications.

With the further scaling of feature size in the nanotechnology era, on-chip optical interconnection will be essential for meeting high-capacity data transmission needs. This paper describes a silicon photonics approach to achieving cost-effective and low-power-consumption on-chip optical interconnects, which includes the use of a small ceramic electro-optical modulator and a Si nano-photodiode coupled with a SiON/SiO2 waveguide, and discusses it in comparison with other approaches.

We propose a three-terminal solid-electrolyte nanometer switch, where the control gate is separated from the current path. This novel switch resolves the issues arising from large current during switching (>1mA) in a two-terminal solid-electrolyte switch. We demonstrate that the drain current reversibly switches when a metallic bridge electrochemically forms or dissolves between the source and drain by applying gate voltage. The ON resistance is 200-300Omega and the ON/OFF current ratio is as high as 105. Each state is nonvolatile

Optoelectronic and electrooptic elements are integrated on VLSI chips. The junction capacitance of a nano-photodiode is extremely low ( 150pm/V) suitable for on-chip modulators. This paper introduces a new approach for realizing high-speed optical interconnects on silicon chips. This concept uses nano-photodiodes on silicon with extremely low parasitic capacitance (less than 10aF) enabling robust communication at very high frequencies. The results demonstrate 5GHz clocking with the promise of up to 20GHz. The authors will also discuss how the silicon nano-photodiode can be used for wavelength-division multiplexing and low-voltage electro-optic modulators for on-chip and off-chip optical communications

The demand for low-power and high-speed chip-to-chip communication between stacked chips in a system in a package (SiP) is increasing day by day. We have proposed and investigated a novel current-sensing technique in an inductive-coupling inter-chip link. Our current-sensing technique reduces total power dissipation by 60% compared with the conventional voltage-sensing technique without sacrificing either data rate (1 Gbit/s per channel) or bit error rate (

This paper reports the development of an in-field real-time successive jitter-measurement macro whose features include 1-ps resolution jitter measurement. The newly developed jitter-measurement macro has four key features: 1) interpolated jitter oversampling; 2) a hierarchical Vernier delay line; and 3)feedforward calibration, each of which helps attain high jitter-measurement resolution; as well as 4) an oversampling rate and measurement range-control technique. A test chip of the macro has been fabricated in a 90-nm process. It successfully measures small random jitter with 1-ps resolution, and large deterministic jitter can also be measured by extending the jitter-measurement range by a factor of 4

Periodically all-in-phase clocking (8-step frequency increments with a 4.5 ns switching time) and deterministic synchronous bus wrappers (synchronized data transfer among different frequency cores) are developed for dynamic voltage- and frequency-scaling multi-core SoCs. A maximum of 60% power reduction in MPEG-4 decoding with 1.5 to 2/spl times/ throughput increase are confirmed.

The aim of this study was to assess and compare the sensitivity of power Doppler sonography, contrast-enhanced sonography, plain computed tomography (CT), and dynamic magnetic resonance imaging (MRI) for detecting hepatocellular carcinoma (HCC) nodules incompletely treated with transcatheter arterial embolization (TAE).A total of 63 unresectable HCC nodules were examined in this study. The HCCs were treated with TAE. All patients underwent plain CT, power Doppler sonography, contrast-enhanced harmonic power Doppler sonography, and dynamic MRI 1 week after TAE. The sensitivity of each modality to incompletely treated HCC nodules was compared. Detection of the residual viable HCC on angiography or tumor biopsy was regarded as the gold standard for the diagnosis of incomplete treatment.Twenty-four nodules (38%) were diagnosed as incompletely treated. The sensitivities of plain CT, power Doppler sonography, contrast-enhanced harmonic power Doppler sonography, and dynamic MRI to these incompletely treated nodules were 42% (10/24), 46% (11/24), 88% (21/24), and 79% (19/24), respectively. Eighty percent (19 nodules) of the 24 incompletely treated nodules were located within a depth of less than 8 cm. The sensitivities of plain CT, power Doppler sonography, contrast-enhanced harmonic power Doppler sonography, and dynamic MRI to these superficial incompletely treated nodules were 37% (7/19), 53% (10/19), 100% (19/19), and 74% (14/19), respectively. In contrast, the sensitivities of each modality to deeply located nodules were 60% (3/5), 20% (1/5), 40% (2/5), and 100% (5/5), respectively.Plain CT and power Doppler sonography had a low sensitivity to HCC nodules incompletely treated with TAE. Except for those that were deeply located, contrast-enhanced harmonic sonography showed the highest sensitivity in detecting incompletely treated HCC nodules.

Proposed here is a new clock-distribution network for multiple clock domain SoCs, one that employs vernier clock generators. Although only one global-clock frequency is used, the clock frequency of individual IP cores can be varied. Furthermore, these variations can be conducted adaptively in fine increments under operating conditions, and clock signals can be stopped/restarted quickly (within a few cycles). These are important advantages for low-power sophisticated SoCs. This paper presents the vernier clock generator, the circuit which is key to making the clock-distribution network practical. A 1.0-GHz vernier clock generator employing a 90-nm CMOS technology is shown to successfully vary output from 0.5 to 1.0 GHz in 8 steps.

A 42-year-old man was treated under a diagnosis of Churg-Strauss syndrome with predonisolone pulse therapy. Three days later, he developed cardiogenic shock following acute myocardial infarction. Coronary angiography showed total occlusions in three peripheral coronary vessels. Intraaortic balloon pumping was used to maintain hemodynamics and predonisolone pulse therapy was repeated. However, he developed cardiogenic shock again after the second pulse therapy and needed percutaneous cardiopulmonary support and intraaortic balloon pumping. Accordingly, combination therapy of predonisolone and cyclophosphamide was given. He then recovered. Follow-up angiography showed recanalization of the infarct-related arteries.

A sampling oscilloscope macro which is easily embedded in an actually operating LSI in the field has been developed to enable practical use of the feedback physical design methodology. The macro features (1) a high-speed input-isolated comparator to measure signals on GHz-digital-LSIs, (2) a voltage-range converter to widen the input range to 2 V at a 1-V supply voltage, (3) D/A converters to eliminate the use of analog I/O for the macro, (4) an on-chip power supply noise filter to eliminate the need for a dedicated power supply, and (5) an embedded clock generator to eliminate the need for a dedicated clock signal. By using the macro, the world's first measurement of an undershooting waveform caused by an on-chip inductive effect has been demonstrated.

An on-chip jitter-spectrum analyzer (JSA) implemented in 0.18/spl mu/m CMOS can locate and analyze trouble-spots in on- and off-chip power and clock distribution networks during the actual operations in the field. A feedback design-flow using JSA improves the performance of 1GHz digital LSIs.

A package-process-oriented multilevel 5-/spl mu/m-thick Cu wiring technology has been developed for low resistance power supply wirings in high-speed ULSIs. A thick Cu wiring fabricated by pulse periodic reverse electroplating achieves the good thickness uniformity without CMP process. A photosensitive resin as interlayer dielectric eliminates dry etching steps. Three layers of thick Cu wirings have been successfully fabricated on the top of a 0.13-/spl mu/m CMOS ULSI with three layers of 0.5 /spl mu/m-thick Al wiring. The total thick Cu wiring resistance is confirmed to be five times as small as that of the conventional two layers of 0.5-/spl mu/m-thick Al wirings. This simple technology is suitable for future low-cost ULSI global wirings.